Storage unit on-board measuring method

Memory in plate test method

technical field

The invention relates to a test method, claims a using circuit board in the scanning component when the testing to the memory particularly method.

background technology

The test of memory is divided into two types, a device is mounted to the plate test method, namely of the memory is a been welded on the PCB is the special the memory tester for testing to the memory. Other is mounted on the plate test method, namely to the memory is welded on the printed circuit board (PCB) testing memory.

Test of the plate is the memory, mainly with self-check system and method for online testing (ICT) device test method. The system self-check method, the testing unit of memory is capable of BIOS or the quick flash storage. The system and time, the operations measuring method is placed on the self-checking to the memory; if finding of false, and report subassembly or the display device is. A the system self-check method for testing the main side of the memory is a itself system capable of normally, and system is device to the normal, wherein the device for judging to the memory fault or the system is units faults. Wherein each different operation system in different and therefore, the testing unit lacks the versatility and probability; and a test of each circuit board which to develop the special test unit particularly. , Wherein each test unit itself which are symmetrically several storage space; and system self-check is device to for testing in the storage unit is directly when the testing to the memory is directly. And and connecting device of the program testing side internet, is increased the design method, difficulty is reliability system.

Digital 1 are is a plate test method, namely of method for memory by ICT device. Shown as a digital 1, wherein the method is memory is a wire, an wires and data wire on the ICT a probe, a test the driving signal of the probe is composed of ICT testing unit according compiles and an appliance to the memory on and is placed on the memory failure analysis with a probe recycling test response signal. Is a ICT testing device memory to a uses the expensive device, and which the developing specialists expertise the ICT testing turn, therefore the average consumer surface and a incapable, generally of the production base is. A clock, the contact of the probe and memory is a physical contact, the invention which a preserved test point when the circuit board design, wherein possibly exists each of the fault miscarriage of justice for bad contact and.

invention content

For on the problem of existence, the target of the invention is connected with a new memory in plate test method, the method by hand rely on the normal operation, and a is needed is a expensive ICT testing device and compilation corresponding test unit, therefore hole is the memory testing charging.

According to the invention memory testing method comprising a ladder of: (1) Is the memory on the circumference with scanning device circuit board, the BS device is comprises a test data input ports and multiple is connected with the boundary scanning unit for the test data located on component outputs the scanning boundary ring is the (TDO) port, composed(2) Scanning boundary any connected with the data wire, an wire or a wire unit and a storage; (3) Is scanning boundary connected with the boundary scanning unit connected data wire, an wire or a wire, the test data reading and store the memory; And (4) and the number of determining reading data and expected value memory for with fault and a fault sample.

According to the memory of the invention is a boundary scanning device according plate and test method using tolerance circuit board with, and is needed to increase the special test apparatus and test unit, after the invention is the cost. Meanwhile, the method and is needed to all the lower system work state, a long and a power and testing, therefore is convenient for the separation test system fault.

Brief for describing the drawings

The is a further understand the invention to the composed of the present invention good embodiment the light of on digital the target, and keys;: Digital are 1 to test method for memory by ICT device; Digital 2 is a scanning boundary component structure drawing leds; Digital 3 is a 16 state machine drawings leds of boundary scanning component; Digital 4 are on a circuit board in the scanning component in the system structure of drawing plate test chip; deviceDigital 5 is in a memory of the JTAG interface and scanning boundary ring of boundary scanning component connected; a

Digital 6 is connected with said image checkerboard method for testing memories unit flow chart; And digital 7 is connected with said image checkerboard method for testing memories unit flow chart.

Detailed composed of illustrated embodiments

The scanning boundary (Scanning Boundary, is mounted BS technology) is arranged tested the input and output pins and based on circuit and introducing boundary scanning unit (BSC), so as to be testing the device and peripheral circuit with a tool of the scanning boundary detecting units the test, so enhanced device controllability and observability. Layer boundary scanning technology solves the problem of the modern electronic technology development with brought, the obtained widespread application layer of the; and circuit board according now generating with the boundary scanning component generally is facilitating the device mounted to the circuit board on the test. The related scanning boundary of detailed rendering can see further IEEE 1149.1 Zhun Dial. With a aid for digital 2 and digital 3 brief rendering scanning boundary processing device of working.

Shown as a digital 2, the waterproof scanning component comprises a connection and circuit based on an edge scanning unit (BSC) and corresponding to the control unit pins, the control unit comprises testing for groove (TAP) and instruction register and data register set (DR) and TAP controller. TAP is a scanning boundary component with the interface of the external device with, comprising the clock input (Test ClocK Input, the following relation is mounted TCI) of the test mode input selection (Test Mode Line, the following relation is mounted TMS) of the test data input (TestData Input, the following relation is mounted TDI) of the testing rod (input Test Reset Input, the following relation is mounted TRST) of the test data output (Test Data Output, the following relation is mounted TDO) is; the input end TRST to be selected. The following sides of brief rendering: (1) And the clock input (TCK) is used for providing the clock signal, keeps the TCK frequency relatively independent, which can not on any system clock the interference. Automatic data of the TDI end moves to the lift of TCK clock pulse, a data of TDO end emigration for dropping of TCK clock pulse the effective. A system input end of the data input end of the lift of TCK clock pulse of performing.

(2) Is test mode input selection (TMS) is used for providing test mode; and logical signal of a bearing (0 or 1) are compromised and been used for controlling operation of the TAP controller. The TCK increasing to the TMS signal pickup, the sampled signal of the TAP controller is decoded, so generating chip and a control signal.

(3) And the data input end is used by the serial manner the test data of the boundary scanning unit based on input circuit, according to TAP controller and data - of input selection indication register or data register. The data of the input with a along the TCK lift.

(4) Is test data outputting the (TDO) is used by the serial manner the test data (the boundary scanning unit) and indication register or data register outputs of the based on circuit, the TAP controller and welded with the data is connected with the indication register or data register. Data of serial output drops the TCK along the emigration, wherein without the data in the TDO output; the TDO end usually and the high-impedance and.

(5) And the reset input (TRST) is used for input logic 0 test reset input to the TRST base pin, a logic asynchronous forcible of TAP wherein an reset mode. Signal wire of the TRST line can be selected, under the state, a long and TMS (5 TCK clocks' high layer, scanning boundary logic circuit and automatically reset.

the TAP controller is a sequence circuit, and data register for control command the operation of register. The TAP controller is driven by test mode selection and testing clock signal, wherein operation head shown the digital 3 of the is diagram according IEEE 1149.1 Dial Zhun defines both. The digital 3, wherein the TAP controller of phase transitions (with arrow expression of) occurred the lift of test clock pulse TCK, and logic is connected with TAP (register and a) on function occurred the lift of TCK along the glue is. The arrow of value of TMS is arranged on the TCK lift along the value. The images as a state of the identification and the main state, the non-shadow's state for by hand between the system function and connected with the process control the auxiliary state.

Digital 4 are on a circuit board in the scanning component in the system structure of drawing plate test chip device. The detection system, a conformed to the IEEE 1149.1 Dial Zhun JTAG controller and computer and comprises a circuit board having parts of irradiation detector is composed of. The computer device and software for scanning boundary detection method, the software is to the circuit board, an circuit board information and part information, the root and transmission according to multiple test algorithm for generating test stimulation signal to the JTAG controller. A JTAG controller is connected with the computer and circuit boards, the driving signal sorting for emitting is for receiving is a JTAG signal (a TDI, TMS and TCK signal) and flow the circuit board is scanning device and corresponding port, at the same time a JTAG controller is emitting for scanning device TDO port for test response signal from the circuit board and a to the computer is a wherein analysis.

Digital 5 is in a arranged JTAG memory controller interface and scanning boundary ring of boundary scanning device by a. Shown as a digital 5, scans the device is composed of the inner with been is repeatedly the TDI end; multiple a connecting the waterproof scanning unit and TDO end of the scanning boundary rod; the TDI end and TDO end and JTAG the test data input end and is connected with the output end, a clock, and a wire, a data wire or an wire memory with a boundary scanning unit connected, the invention can realize of a memory cells of boundary scanning unit and a storage.

The following with a tool of 16 machine is composed a scanning boundary parts according shown the digital 3 the test data storage shell and a memory reading test data path.

The process of test data fixing carrier, a JTAG first controller for making the BS device is at the serial shift (shift-DR) state, under the state, testing the driving signal initializes of the serial shift path of the TDI end and TDO end in corresponding boundary scanning unit, when the test stimulation signal is information according to the memory and fault model; a represented to the memory preset address writing preset data to the evaluation of the address wire, a data line and a wire needed how, wherein the channel is describe the invention conducted the external memory interconnecting test and an internal device for testing the detailed rendering to act according to the memory and fault model for fixing store's data. Then a JTAG controller in the BS device by a series of auxiliary state inlet and main for updating (Update-DR) state, under the state, a signal is the waterproof scanning unit and a storage location is connected with the address wire, a data wire or the driver wire, setting of with realising memory reading operation.

A process of memory reading test data, a JTAG controller first and BS device is at the serial shift (shift-DR) state, under the state, testing the driving signal initializes of the serial shift path of the TDI end and TDO end in corresponding boundary scanning unit, when the test stimulation signal is represented from the storage preset address the preset data to evaluation of the address wire and a wire a. Then a JTAG controller in the BS device by a series of auxiliary state inlet and main for updating (Update-DR) state, under the state, a signal is the scanning boundary flow unit is connected with the address wire and a wire of the selected address of memory. , And the waterproof scanning component experiences a series of auxiliary state water inlet under the control of JTAG controller and main for capturing (Capture-DR) state, a signal in memory data line introduces under the state of the connected in scanning unit. Terminal, the BS device comprises a serial shift state, the outer wall of the BS device by the data of the serial shift is a buckle, thus realizing operation for reading data memory.

And the seen, wherein the waterproof scanning component of the circuit board with capable of realizing memory reading and writing portable operation; and invention in the read-write operation of memory is formed by rule according to the memory and fault model, and connected to the memory fault for with the number of reading data.

The following by the read-write memory and non-erasable memory (ROM) for the memory device of faults by the object space test data as a describing the method.

Flow the read-write memory, wherein test comprises an external interconnecting test and an internal testing unit, the external interconnecting test apparatus and detecting to the data line, an wire and a cable fault memory, and inner unit testing to memory memory cells fault and a detection. The external test and an internal testing with different fault model, therefore that is lighter and is using different test algorithm for an different test. The following arranged in the detailed rendering: A memory. for testing (1) fault model to analyze to the fault mechanism, so provided with a corresponding fault model is a confirmatory test side algorithm. Is the external interconnecting test instrument, matter using is the permanent fault model. The fact, the permanent fault is further memory input circuit fault major. A fault model comprises fixed logic fault; a fault and a connection short-circuit fault indicator.

and a fixing logic fault (Stuck-at fault) is logic fault reference data wire or the address supply condition layer, the physical defect and is not input the controller, and constantly for logic 0 or 1 logic state fault, comprising a logic state voltage is 1 S-A-1 (Stuck-at-1) and fault logic state voltage is 0 S-A-0 (Stuck-at-0) fault. The permanent fault is mounted the delay fault.

b and fixed opening fault (Stuck-open fault) is a fault reference fault of each circuit opening and. The external interconnecting test, to according to the circuit concrete structure, fixed opening fault is a equal to S-A-0 or the S-A-1 fixed logic fault.

c and a connection short-circuit fault indicator (Short fault) is connection short-circuit fault indicator reference, each 2 or is more than 2 input and output wire short-circuits the fault of, comprising 0) is control troubles SMS (Short 0-Dominant fault) and 1 to control the short-distance troubles (1-Dominant Short-circuit fault).

(2) And the pace for an upper external for fault model, the invention claims inventor and a device is mounted to the pace of the algorithm, the algorithm are capable of discover the external for fault, wherein a precisely the locating fault. The following to claims 1 to the pace the test process.

1 Meter

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The meter 1 first step test through the A1 any two different addresses writing full 0 of A0 and an and total 1 data and a data reading and two addresses to position detecting data wire for with a fault. Intercom rack, and said full 0 a card reading full 0, compromised of the data line with S-A-1 fault, the value is 1 data line is provided with a S-A-1 fault line position. And said full 1 a card reading full 1, compromised of the data line with S-A-0 fault, the value is 0 data wire is provided with a fault S-A-0 data line position.

The second paces of the test data line for with short-circuit fault indicator. Shown as the meter 1, first and data line n to different address A0 and A1 ......A corresponding 11 writing according to 1 is algorithm for generating n data D0 and A ......Dn (further arranged with test vector) and n is addresses by the data line reading data, initial data D0 is 100 ......0. Wire 1 algorithm (Walk-1) meaning, the test vector the generation type through the value the preceding test vector is 1 unidirection orientation shifting is a rear test vector generating. For example and test vector the n is 7, the initial test vector 1000000, according to wire 1 algorithm, the test vector can be connected in sequence: 1000000, 0100000, 0010000, 0001000, 0000100, 0000010 And 0000001, further - comprising the initial test vector 0000000, according to wire 1 algorithm, the test vector can be connected in sequence: 0000000th, 1000000, 0100000, 0010000, 0001000, 0000100 And 0000010.

Is arranged in the data line to the n different address A0 and A1 ......A corresponding 11 writing according to 0 is algorithm extension n data D0 and A ......Dn (further arranged with test vector) and n is addresses by the data line reading data, initial data D0 is 011 ......1. Wire 0 algorithms (Walk-0) is 1 algorithm is supplementary, namely wherein test vector's generation type through the value the preceding test vector is 0 unidirections orientation shifting is a rear test vector generating. For example and test vector the n is further 7, wherein the initial test vector is 0111111 mm, and test vector can be 0111111, 1011111, 1101111, 1110111, 1111011, 1111101 and 1111110, further - comprising the initial test vector is 1111111 mm, and test vector can be 1111111, 0111111, 1011111, 1101111, 1110111, 1111011 and 1111101.

And a short-circuit fault indicator to short-circuit fault indicator of data line position for judging according to the second step test result, a and second step test result of meter 2 or explain to for as a how is placed on the diagnosis to the fault, matter test data line is b3b2b1b0, the test vector (i.e. reusing a data line value logic) arrange is r1 and ...... r7, initial test vector arrange and r4 is 1000 and 0111.

And seen the meter 2, according to the second step test a set of detection results the invention can determine for with short-circuit fault indicator of data line position, wherein a determining for short-circuit fault indicator of the sample, and a differentiate 1) is control short - circuit and 0 to control the short - circuit.

2 Meter

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The guaranteeing the data line without the fault, when the third step test testing to the address wire for with opening or the short-circuit fault indicator. First by to an wire 1 algorithm of a selected address n the data line 0 ", A groove 1 ......A - n writing n different data OF of a groove, 0 ' OF 1 ......The three-dimensional character and n of n addresses through the data line reading data, and an initial A groove 0 and 000 ......0. Then by to an wire 0 algorithm of a designations n address the data line 0 ", A groove 1 ......A - n writing n different data OF of a groove, 0 ' OF 1 ......The three-dimensional character and n of n addresses through the data line reading data, and an initial A groove 0 and 111 ......1.

Second step the third the step; the second step test, writing any one group can be differentiate the address data according to 1 is algorithm or is 0 algorithm extension, and third step test, and is any data of a group of differentiate a fixed part according to 1 is algorithm or is the addresses of 0 algorithm of a designations, and an initial for 0 or 1 full. The following and third step test result of meter 3 to the meter for as a how is placed on the diagnosis to the fault, matter address wire a3a2a1a0 according to is 1 or 0 wire algorithm the; the initial address is 0000, the address number of the invention is arranged 5, further data D0, D1, D2; and After D4 for reading and are mutually different.

And seen the meter 3, according to the step test a set of detection results the invention can determine for with short-circuit fault indicator of an wire position, wherein a determining for short-circuit fault indicator of the sample, and a differentiate 1) is control short - circuit and 0 to control the short - circuit.

3 Meter

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The B. the memory testing unit (1) fault model is memory, a writing the driving circuit and read amplifying circuit; the storage unit array and input part and a decoding composed of. The fault according the position is composed of a storage unit array fault and an decoding circuit fault and an logic fault differently:

Fault of the storage unit array comprises the following: sample(1 )Is logic fault (Stuck-at fault): The logic unit and a not changing along the use of unit, by the unit influences, sending the delay fault, comprising a fixing is 1 or fastener is 2 situations (S-A-0 or S-A-1); (2 )Is a fault (Stuck-open fault): Fault of the circuit opening; a(3 )And transition fault (Transition fault): 0□1 Or 1□0 phase transition at least one correctly does not of the; (4 )Data keeps the fault (Data-maintaining fault): The storage unit (to the method a logic connection of multiple time; (5 )And a fault (Circuit fault): And said of j unit is at the specific the y (yχ device} 0,1), the bus) is a fixed value x (xχ device} 0,1), and sending unit) couplings of j unit. The low-temperature relation is necessarily with a symmetrically arranged, for unit) in couplings unit, j uncertain j unit is a coupling device AND.

(6 )Multiple writing fault (multiple and fault): ) With the x (xχ device} 0,1) to the j unit is a fixed the x to the unit, and said for unit) with multiple writing fault. Multiple writing fault the necessarily with are.

Fault of the address decoding circuit comprises the following: sample(1 )With a any uses a storing unit; (2 )Adopts the selection unit, and a uses the device.

The fault a decoder of equivalent for fault of the storage unit array, for example fault (1 )is equivalent to the opening fault, the fault (2 )is equivalent multiple writing fault.

The fault the read-write logic comprises the following: sample(1 )Is input and output wire one or multiple fixing logic, faults(2 )Is buffers latch is one or multiple fixing opening; faults(3 )Is buffers or state latch faults connection between any two.

The fault the read-write logic circuit is equivalent is fault of the storage unit array, for example fault (1 )equivalent the fixing logic fault, fault (2 )is equivalent to the opening fault, fault (3 )equivalent the connection state fault.

(2) With said image checkerboard method in the fault model for an upper memory, the invention claims inventor and a device is mounted with said time checkerboard method algorithms, the algorithm electric voltage to said time reading and writing operations to memory are memory cells, therefore is mounted in said with multiple, and further each writing the two storage unit data is connected to supplementarily, is similar to the chess checkerboard, therefore is mounted in checkerboard image, and is mounted is in said a checkerboard image and method. Nine-stroke a checkerboard image method of when the comprehensive test to the storage unit, the decoding circuit and read-write logic memory, a performing flow rack to digital 6 and 7 or.

Digital and 7 comprises 5 cyclic in the digital 6, wherein the described according to the order: A cyclic process 1 address pointer points of the lowest address position, namely 0000 ......00th, At the time of boundary scanning unit, writing of n is the same address of memory 0 and double-state data data 1 of internet of 0101 ......01st, And an indicator of the adjacent and an, namely 0000 ......01st, Writing the n position double-state data data to the address 0101 ......01st, The connection process traversing features are addresses of the low level to the upper digital till the address pointer. Matter n is a data line of.

A cyclic process 2 and an address pointer to ferrule alignment the lowest address position which multiple, which is a boundary scanning unit, a data line memory from the data and n position double-state data data of the address reading and writing 0101 ......01 Comparisons, comprising a, matched with that is indicated for storing unit with the fault; And writing n to the address 1 and double-state data data 0 of internet in 1010 ......10. Then the display direction of the adjacent and an, namely 0000 ......01st, Duplicates the upper reader, and an operation handwriting on the address. The process with continued till the address pointer direction highest in an.

A cyclic process 3 and address pointer to ferrule alignment the lowest address position which multiple, which is a boundary scanning unit, a data line memory from the data and n position double-state data data of the address reading and writing 1010 ......10 Comparisons, comprising a, matched with that is indicated for storing unit with the fault; And writing n to the address 0 and double-state data data 1 of internet of 0101 ......01. Then the display direction of the adjacent and an, namely 0000 ......01st, Duplicates the upper reader, and an operation handwriting on the address. The process with continued till the address pointer direction highest in an.

Cyclic process display 4, wherein the shown 7 of the current time, the address pointer points of the highest address position, namely 1111 ......11th, At the time of boundary scanning unit, a data line memory from the data and n position double-state data data of the address reading and writing 0101 ......01 Comparisons, comprising a, matched with that is indicated for storing unit with the fault; And writing n to the address 1 and double-state data data 0 of internet in 1010 ......10. Then the display direction of the adjacent and an, namely 1111 ......10th, Duplicates the upper reader, and an operation handwriting on the address. The process with continued till the address pointer direction of the low address.

A cyclic process 5 and address pointer to ferrule alignment the highest address position which multiple, then the waterproof scanning unit, a data line memory from the data and n position double-state data data of the address reading and writing 1010 ......10 Comparisons, comprising a, matched with that is indicated for storing unit with the fault; And writing n to the address 0 and double-state data data 1 of internet of 0101 ......01. Then the display direction of the adjacent and an duplicates, wherein the reader, and an operation handwriting on the address. The process with continued till the address pointer direction of the low address.

And seen, wherein the cyclic process 1 operation result writing logic value to the address of the memory cells of an direction of the low address 0 or 1. A cyclic process 2 operation results of the low address the address of the storage unit logic reading values and writing logic values of an direction is 0 memory cells writing logic value 1, further - comprising a fixed on the logical value is 1 storage unit writing logic 0 value. A cyclic process 3 operation results of the low address the address of the storage unit logic reading values and writing logic values of an direction is 1 storage unit writing logic value 0, further - comprising a fixed on the logical value is 0 memory cells writing logic 1 value. By the three cyclic process of determining fixed logic fault and fixed opening fault, 0□1 and 1□0 the phase transition fault and data keeps the faults. A cyclic process 4 operation results and writing logic value to the low address of the storage unit logic reading values of an direction of the address is 0 memory cells writing logic value 1, further - comprising a fixed on the logical value is 1 storage unit writing logic 0 value. A cyclic process 5 operation results and writing logic value to the low address of the storage unit logic reading values of an direction of the address is 0 memory cells writing logic value 1, further - comprising a fixed on the logical value is 1 storage unit writing logic 0 value. With the upper 5 cyclic process of determining to the connection state fault and multiple writing fault. The summary, Figure 6 and 7 are uniformly arranged with checkerboard image method in the fault model of storing unit faults to the upper memory (comprising a fixing logic fault; a fault and phase transition fault and a state fault and multiple writing fault) and is source and algorithm.

The C. non-erasable memory (ROM) testing unit is ROM, layer is device to look to the read-write memory such to the inner shell unit data, therefore which is other method for when the test.

Comparing the checking and a expected value of the ROM with the simple quick method, and tallies, and judging ROM function of normal, otherwise the data of judging ROM in a errors.

For testing method to the address so the reading a ROM to position is placed on the expected and data by a comparison, and data reading and expected value of the matching cases, and judging ROM function of normal, otherwise the data of judging ROM in a errors. Is needed when the lighter integrity detecting to the ROM by the method.