CA2874891C

A multiformat digital audio interface

Abstract

Embodiments of various methods, devices and systems are described herein that use a unified bus communication protocol. One such device comprises an interface for sending and receiving signals, and a mux and sync engine coupled to the interface and configured to determine time slots for sent and received signals according to a unified bitstream frame format. The unified bitstream frame format comprises a plurality of frame channels for transmitting data in a bitstream mode of communication such that data from the frame channels are time-multiplexed across the frame channels one bit at a time, wherein one of the frame channels is allocated as a control channel comprising individual control bits from control data, and at least one of the frame channels is allocated as a virtual frame channel comprising individual data bits taken from digital word data.

CA2874891C, drawing sheet 1 — Sheet 1 of 19

Term

6.4 yearsleft in the term

Expires 5 March 2033.

25 claims: 17 independent, 8 dependent

1
CA 02874891 2016-05-05 269 What is claimed is:1. A method for communicating between devices coupled to a bus, wherein the method comprises: using a unified frame format for data transmitted in a bitstream mode of communication, the unified frame format comprising two or more frame channels, each of the frame channels given an assigned time slot in the unified frame format;and sending bits on a single wire between at least two of the devices coupled to the bus by sending one bit from a first of the frame channels at the time slot assigned to the first of the frame channels, then sending one bit from a next of the frame channels at the time slot assigned to the next of the frame channels, and so on until one bit from each of the frame channels has been sent, and then resuming sending from the first of the frame channels, wherein one of the frame channels is used as a control channel carrying individual control bits from control data and one or more of the other frame channels are used as virtual frame channels carrying individual data bits taken from digital word data.
4
The method of any one of claims 1 to 3, wherein the digital word data corresponds to different digital word data channels, and for each of the different digital word data channels, the individual data bits taken from that digital word data channel are carried by a unique one of the virtual frame channels. CA 02874891 2016-05-05 270
5
The method of any one of claims 1 to 4, wherein the method further comprises assigning data from a common bitstream data channel to more than one of the frame channels.
6
The method of any one of claims 1 to 5, wherein the method further comprises combining data from a group of bitstream data channels into a common one of the frame channels to reduce bandwidth used by the group of bitstream data channels.
7
The method of any one of claims 1 to 6, wherein one or more of the frame channels are used as bitstream channels carrying individual data bits that are used or generated by one of the devices.
12
The method of any one of claims 1 to 11, wherein the control data comprises at least one of a read operation, a write operation, a ping operation and a function operation. CA 02874891 2016-05-05 271
13
The method of any one of claims 1 to 12, wherein the method further comprises grouping data channels from a port of one of the devices into several subgroups to lower latency, and using unique frame channels for the subgroups.
14
The method of any one of claims 1 to 13, wherein the method further comprises multiplexing data from several data channels into a common frame channel to control bandwidth of data transmitted on the bus.
15
The method of any one of claims 1 to 14, wherein the method further comprises allowing multi-master operation by allowing control words to be written by more than one master device and using arbitration for bus collisions to determine which master device controls the bus.
16
An electronic device that communicates according to a unified bus communication protocol, wherein the device comprises:an interface for sending and receiving signals;and a mux and sync engine coupled to the interface, the mux and sync engine being configured to determine time slots for sent and received signals according to a unified frame format comprising two or more frame channels for transmitting data in a bitstream mode of communication, each of the frame channels given an assigned time slot in the unified frame format, such that bits are sent on a single wire by sending one bit from a first of the frame channels at the time slot assigned to the first of the frame channels, then sending one bit from a next of the frame channels at the time slot assigned to the next of the frame channels, and so on until one bit from each of the frame channels has been sent, and then resuming sending from the first of the frame channels, wherein one of the frame channels is used as a control channel carrying individual control bits from control data, and one or more of the other frame channels are used as virtual frame channels carrying individual data bits taken from digital word data.
19
The device of any one of claims 16 to 18, wherein one or more bits are included in the control channel to synchronize data that extends across multiple frames or to support odd sample rates.
20
The device of any one of claims 16 to 19, wherein two status bits are added in the control data to control validity of transmitted data for asynchronous data flow in word mode, wherein the first status bit indicates if the transmitted data that follows the status bits is valid, and the second status bit indicates whether a receiving device can accept the transmitted data.
21
The device of any one of claims 16 to 20, wherein two status bits are added in front of transmitted data to control validity of the transmitted data for asynchronous data flow in the bitstream mode of communication, wherein the first status bit indicates if the transmitted data that follows the status bits is valid, and the second status bit indicates whether a receiving device can accept the transmitted data.
22
The device of any one of claims 16 to 21, wherein data channels from a port of the devices are grouped into several subgroups to lower latency, and unique frame channels are used for the subgroups.
23
The device of any one of claims 16 to 22, wherein data from several data channels are multiplexed into a common one of the frame channels to control bandwidth of transmitted data.
24
The device of any one of claims 16 to 23, wherein bandwidth of the control channel is controlled by using at least two of the frame channels for a common data channel.
25
A computer readable medium comprising a plurality of instructions executable on a microprocessor of a device for communicating with another device, wherein the method CA 02874891 2016-05-05 273 comprises:which, when executed on the microprocessor, result in the method of any one of claims 1 to 15.

Independent claims17

1,294 paragraphs in 803 sections, as filed

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- 1 TITLE: A MULTIFORMAT DIGITAL AUDIO INTERFACE

FIELD

[0001] The various embodiments described herein generally relate to a method, system and communication protocol for implementing a multiformat digital data interface for bus systems.

BACKGROUND

[0002] In a computer or processor architecture, a bus is a subsystem that transfers data between devices within an electronic device or transfers data between electronic devices. Bus architectures are also used in common data signalling paths for multiple devices rather than having separate connections between each set of devices that may communicate with one another. In other words, the bus structure can be used to allow one or more slave devices to communicate with one or more master devices.

SUMMARY OF THE EMBODIMENTS

[0003] In one aspect, at least one embodiment described herein provides a method for communicating between devices coupled to a bus, wherein the method comprises using a unified bitstream frame format for data transmitted in a bitstream mode of communication, the unified bitstream frame format comprising a plurality of frame channels; using one of the frame channels as a control channel comprising individual control bits from control data; using at least one of the frame channels as a virtual frame channel, the frame channel comprising individual data bits taken from digital word data; and sending at least one of control bits and data bits between at least two of the devices coupled to the bus at times specified by the unified bitstream frame format such that data from each of the frame channels is timemultiplexed across the channels and sent one bit at a time.

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-2[0004] In at least one embodiment, the number of frame channels define a width for the unified bitstream frame format with each of the frame channels being one bit wide and each of the frame channels has a number of bits defining a length for the unified bitstream frame format.

[0005] In at least one embodiment, the method further comprises interlacing data bits taken from digital word data corresponding to different digital word data channels into a common virtual frame channel.

[0006] In at least one embodiment, the method further comprises utilizing a unique virtual channel for data bits taken from digital word data from each digital word data channel.

[0007] In at least one embodiment, the method further comprises assigning data from a common bitstream data channel to more than one frame channel.

[0008] In at least one embodiment, the method further comprises combining data from a group of bitstream data channels into a common frame channel to reduce bandwidth used by the group of bitstream data channels.

[0009] In at least one embodiment, the method further comprises using one of the frame channels as a bitstream channel, the bitstream channel comprising individual data bits that are used or generated by one of the devices.

[0010] In at least one embodiment, the method further comprises using unique frame channels for a plurality of bitstream data channels comprising individual data bits taken from separate bitstream data channels.

[0011] In at least one embodiment, the method further comprises repeatedly using a plurality of bitstream data channels with different sets of unique frame channels defined by a repeat parameter and the plurality of bitstream data channels comprise individual bits taken from separate bitstream data channels.

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-3[0012] In at least one embodiment, sets of unique frame channels are separated by a number of frame channels defined by a skip parameter.

[0013] In at least one embodiment, the control bits are consecutively selected from bits of a synchronization word, and then from bits of an X command word and then from bits of a Y command word.

[0014] In at least one embodiment, the method further comprises using the control channel to send command data comprising a read operation, a write operation, a ping operation and a function operation.

[0015] In at least one embodiment, the method further comprises using 10 the control channel to send synchronization data one bit at a time, the synchronization data comprising an S word having a constant portion used by a slave device for searching purposes and a dynamic portion used by a slave device for verification purposes.

[0016] In at least one embodiment, the method further comprises using 15 a CRC counter to generate the dynamic portion of the S word.

[0017] In at least one embodiment, the method further comprises using the frame channels to implement bi-directional data transfer between at least two of the devices coupled to the bus.

[0018] In at least one embodiment, the method further comprises using 20 a single wire for the bus, and merging clock information, control information, synchronization information and data information for transmission on the single wire.

[0019] In at least one embodiment, the method further comprises using two wires for the bus, wherein a first wire is used to transmit control information, synchronization information and data information, and a second wire is used to transmit clock information.

[0020] In at least one embodiment, the method further comprises including one or more bits in the control channel to synchronize data that extends across multiple frames or to support odd sample rates.

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-4[0021] In at least one embodiment, the method further comprises adding two status bits in the control data to control validity of transmitted data for asynchronous data flow in word mode, wherein the first status bit indicates if the transmitted data that follows the status bits is valid, and the second status bit indicates whether a receiving device can accept the transmitted data.

[0022] In at least one embodiment, the method further comprises adding two status bits in front of transmitted data to control validity of the transmitted data for asynchronous data flow in the bitstream mode of communication, wherein the first status bit indicates if the transmitted data that follows the status bits is valid, and the second status bit indicates whether a receiving device can accept the transmitted data.

[0023] In at least one embodiment, the method further comprises providing data integrity support by monitoring all transmitted data within a frame, calculating the parity of the transmitted data and checking for acknowledgement for a READ or WRITE operation from one or more slave devices attached to the bus that received a command to perform the operation.

[0024] In at least one embodiment, the method further comprises providing data integrity support by monitoring all data transmitted within a frame, calculating the parity of the transmitted data and checking for not acknowledgement for an operation other than a READ or WRITE operation from one or more slave devices attached to the bus that received a command to perform the operation.

[0025] In at least one embodiment, the method further comprises using a portion of a PING operation to indicate which frame format is used for data transmission.

[0026] In at least one embodiment, the method further comprises grouping data channels from a port of one of the devices into several

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-5subgroups to lower latency, and using unique frame channels for the subgroups.

[0027] In at least one embodiment, the method further comprises multiplexing data from several data channels into a common frame channel to control bandwidth of data transmitted on the bus.

[0028] In at least one embodiment, the method further comprises controlling bandwidth of the control channel by using at least two of the frame channels for a common data channel.

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-8[0046] In at least one embodiment, for a unified frame format, the configuring of the synchronized slave devices comprises specifying at least one frame channel as a virtual frame channel which is used to transmit digital word data one bit at a time.

[0047] In at least one embodiment, the configuring of the synchronized slave devices comprises specifying at least one frame channel as a multiplexed frame channel in which bits from different data channels are multiplexed in a common frame channel.

[0048] In at least one embodiment, the configuring of the synchronized slave devices comprises at least one of varying the number of frame channels allocated to one or more data channels to vary bandwidth used by a control frame channel during data transmission and to one or more data channels.

[0049] In at least one embodiment, the configuring of the synchronized slave devices for a given frame comprises at least one of specifying gaps between frame channels allocated to data channels in the given frame, specifying groupings of frame channels allocated to different data channels in the given frame, and specifying a repetition of frame channels allocated to groups of different data channels in the given frame.

[0050] In at least one embodiment, the method further comprises supporting asynchronous data transfer by adding two bits preceding data for a data channel in a first frame used for data transmission, wherein one of the bits indicates if a transmitting device has new data to transmit that is valid and another one of the bits indicates if a receiving device has received the transmitted new data.

[0051] In at least one embodiment, the method further comprises supporting data flows of a fractional nature, by using a bit in a command word to indicate data transfer occurs over several frames rather than one frame.

[0052] In yet another aspect, at least one embodiment described herein provides an electronic device that communicates according to a unified bus communication protocol. The device comprises an interface for sending and

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-9receiving signals; and a mux and sync engine coupled to the interface, the mux and sync engine being configured to determine time slots for sent and received signals according to a unified bitstream frame format comprising a plurality of frame channels for transmitting data in a bitstream mode of communication such that data from the frame channels are time-multiplexed across the frame channels one bit at a time, wherein one of the frame channels is used as a control channel comprising individual control bits from control data, and at least one of the frame channels is used as a virtual frame channel comprising individual data bits taken from digital word data.

[0053] In at least one embodiment, data bits taken from digital word data corresponding to different digital word data channels are interlaced into a common virtual frame channel.

[0054] In at least one embodiment, a unique virtual channel is utilized for data bits taken from digital word data from each digital word data channel.

[0055] In at least one embodiment, data from a common bitstream data channel are assigned to more than one frame channel.

[0056] In at least one embodiment, data from a group of bitstream data channels is combined into a common frame channel to reduce bandwidth used by the group of bitstream data channels.

[0057] In at least one embodiment, one of the frame channels is used as a bitstream channel, the bitstream channel comprising individual data bits that are used or generated by the device.

[0058] In at least one embodiment, unique frame channels are used for a plurality of bitstream data channels, the plurality of bitstream data channels comprising individual data bits taken from separate bitstream data channels.

[0059] In at least one embodiment, a plurality of bitstream data channels are repeatedly used with different sets of unique frame channels according to a repeat parameter and the plurality of bitstream data channels comprising individual bits are taken from separate bitstream data channels.

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- 10[0060] In at least one embodiment, the control channel is used to send command data comprising a read operation, a write operation, a ping operation and a function operation.

[0061] In at least one embodiment, the control channel is used to send 5 synchronization data one bit at a time, the synchronization data comprising an

S word having a constant portion used by a slave device for searching purposes and a dynamic portion used by a slave device for verification purposes.

PCT/CA2013/000198

-13[0082] In at least one embodiment, the device is configured to set the mode of operation by selecting between a word mode of operation and a bitstream mode of operation.

[0083] In at least one embodiment, the device is configured to set the at least one frame format by selecting one of a word frame format, a bitstream frame format and a unified bitstream frame format.

[0084] In at least one embodiment, the device is configured to set the mode of operation by specifying values for at least one of: sampling rate, channel selection, port selection, allocation of frame channels, allocation of subgroups of port channels in the allocation of frame channels, different repetitions of port channels in the allocation of frame channels, and multiplexing of data from different channels into a common frame channel.

[0085] In at least one embodiment, the device is configured to aid in the synchronization of slave devices by transmitting S word data, wherein in word mode, bits of an S word are transmitted consecutively and in bitstream mode, the bits of the S word are multiplexed in time with bits from other frame channels.

[0086] In at least one embodiment, the device is configured to aid in synchronization of slave devices by monitoring bus activity for any newly synchronized slave devices indicated by slave status data and dynamically assigning addresses to the newly synchronized slave devices.

[0087] In at least one embodiment, the device is configured to configure the at least one synchronized slave device by programming at least one port of the at least one synchronized slave device and assigning time slots for transmitting data for selected data channels according to the selected frame format.

[0088] In at least one embodiment, the programing of at least one port comprises at least one of grouping together data channels that receive input data to a first common port, and grouping together data channels that transmit

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- 14output data to a second common port, wherein data for data channels of a given port are sampled at a common frequency.

[0089] In at least one embodiment, in word mode, the configuring of the at least one synchronized slave device comprises defining a size for a subframe, the subframe being a portion of a frame from the beginning of a command word to the beginning of another command word.

[0090] In at least one embodiment, the configuring of the at least one synchronized slave device for a given subframe comprises at least one of specifying gaps between time slots allocated for data for data channels in the given subframe, specifying at least one grouping of different data channels in the given subframe, specifying at least one repetition of at least one grouping of different data channels in the given subframe, and specifying at least one repetition of a single data channel in the given subframe.

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- 17[00102] In at least one embodiment, a clock signal provided to the first bus is kept at a steady voltage level to reduce power consumption in instances where there is no activity on the bus.

[00103] In at least one embodiment, no control information is transmitted 5 when entering the second mode of operation.

[00104] In at least one embodiment, the system receives a first clock signal from an accurate clock source and a second clock signal from a less accurate clock source having a quicker startup time than the accurate clock source, and when the first bus is kept at the steady voltage level the system uses the second clock signal and after activity has resumed on the first bus the system uses the first clock signal.

[00105] In at least one embodiment, a fast startup is enabled after a low power mode by enabling a fast settling oscillator.

[00106] In at least one embodiment, the system comprises a second bus, the first and second buses comprising a separate data line and a separate clock line and the system further comprises first and second groups of slave devices, the first group of slave devices being coupled to the first bus and the second group of slave devices being coupled to second bus and a clock signal on the clock line is run at a lower frequency.

[00107] In at least one embodiment, in the second mode of operation only one master device and one slave device are attached to the first bus, wherein one of the devices drives the first bus when a clock signal is high and the other device drives the first bus when the clock signal is low.

[00108] In at least one embodiment, the slave device is configured to wake up the master device in order to switch to the first mode of operation by transmitting a predefined sequence to the master device and the master device comprises a filter that is configured to filter transmitted data on the first bus to detect the predefined sequence.

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- 18[00109] In at least one embodiment, the master device is configured to change a frequency of the clock signal used for the first bus in order to switch to the first mode of operation.

[00110] In at least one embodiment, the bus communication protocol is 5 adapted to allow two devices to communicate on the first bus at the same time in the second mode of operation resulting in a bus conflict to change to the first mode of operation.

[00111] In at least one embodiment, in the second mode of operation if the at least one slave device loses synchronism with the first bus, the at least one slave device is configured to transmit data at time slots corresponding to an empty column in a frame format used by the bus communication protocol and when the at least one master device detects this activity the at least one master device is configured to switch to the first mode of operation and transmit control information to the at least one slave device for resynchronization.

[00112] In at least one embodiment, in the second mode of operation if the at least one slave device loses synchronism with the first bus, the at least one slave device is configured to transmit data at time slots corresponding to a utilized column in a frame format used by the bus communication protocol thereby resulting in transmission errors and when the at least one master device detects these transmission errors the at least one master device is configured to switch to the first mode of operation and transmit control information to the at least one slave device for resynchronization.

[00113] In yet another aspect, at least one embodiment described herein provides a bus system comprising a bus; at least one receiver coupled to the bus; and a transmitter coupled to the bus, the transmitter being configured to operate in either MONO or STEREO mode based on a value received at an input terminal that is used to select driving the output data during a low clock value or a high clock value or during both clock values in MONO mode, wherein the bus system shall be controlled by a clock signal and the transmitter transmits data in time slots based on the value of the clock signal.

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- 19[00114] In at least one embodiment, the system is configured to automatically adjust internal sampling so that an output sample rate is twice as fast in the MONO mode given a same input clock frequency.

[00115] In at least one embodiment, the selection is determined based on whether the input terminal is connected to a logic low value, a logic high value or is electrically floating.

[00116] In at least one embodiment, the floating condition is utilized to select the MONO mode and data is output on the bus during both high and low portions of the clock signal.

[00117] In at least one embodiment, the transmitter is configured to utilize a multi-level sigma delta converter to convert from analog to digital format and the transmitter is further configured to output a two-level signal.

[00118] In at least one embodiment, the conversion from multiple levels to two levels is done using a digital delta-sigma converter.

[00119] In at least one embodiment, the conversion from multiple levels to two levels is done by mapping from multiple values to single values.

[00120] In yet another aspect, at least one embodiment described herein provides a bus system comprising a first bus; at least one master device coupled to the first bus; at hub device coupled to the first bus; and a plurality of slave devices coupled together in a topology and coupled to the hub device so that the slave devices are not driven at the same time or not all of the slave devices are attached to the first bus.

[00121] In at least one embodiment, a given slave device is coupled to the hub device, the slave devices are separated from one another by a similar physical distance and the given slave device is separated from the hub device by the similar physical distance.

[00122] In at least one embodiment, the slave devices are numbered in a certain way to obtain the similar physical distance between one another.

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-20[00123] In at least one embodiment, bus data is transmitted between the plurality of slave devices in a serial manner and the topology is a pipe structure.

[00124] In at least one embodiment, a second given slave device is coupled to the hub device and bus data is transmitted from the hub device to the given slave device, from the given slave device to the plurality of slave devices and then from the second given slave device to the hub device in a serial manner.

[00125] In at least one embodiment, the topology is a ring structure.

[00126] In at least one embodiment, the topology is a single dimension, staggered ring topology.

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-25[00156] In at least some embodiments, the data, control or synchronization information is transmitted on each clock edge during a clock cycle of the bus during overclocking.

[00157] In at least some embodiments, data, control or synchronization information is not transmitted during an idle period determined by at least by a jitter period represented by the jitter between a clock of the master device and the at least one slave device.

[00158] In yet another aspect, in at least one embodiment described herein therein is provided a bus system comprising a bus; a master device coupled to the bus; and at least one slave device coupled to the bus; wherein the master device and the at least one slave device are configured to use a bus communication protocol to communicate over the bus, the bus communication protocol comprising using multiple voltage levels (i.e. multilevel signaling) during time slots for transmitting multiple bits of information over the bus, the number of bits being based on the number of voltage levels.

[00159] In at least some embodiments of multilevel signaling, four voltage levels are used allowing for two bits of information to be transmitted during a given time slot.

[00160] In at least some embodiments of multilevel signaling, 2N voltage levels are used allowing for N bits of information to be transmitted during a given time slot.

[00161] In at least some embodiments of multilevel signaling, when the information comprises bitstream data, a first bit in time slot N is given by a first bit (BN) and subsequent bits until a last bit in time slot N+1 are given by Bn+i XNOR Bn.

[00162] In at least some embodiments of multilevel signaling, when the information comprises binary data, a first bit in time slot N is given by a first bit (Bn) and subsequent bits until a last bit in time slot N+1 are given by Bn+i

XOR Bn.

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-26[00163] In yet another aspect, in at least one embodiment described herein therein is provided a bus system comprising a bus; a master device coupled to the bus; and at least one slave device coupled to the bus; wherein the master device and the at least one slave device are configured to use a bus communication protocol to communicate over the bus, the protocol comprising using bit inversion with at least a first bit in a series of data bits to convey an edge of a clock signal along with data.

[00164] In at least some embodiments, the bit inversion comprises replicating a first bit in the series of data bits, inverting either the replicated data bit or the first bit and transmitting the replicated data bit before the series of data bits.

[00165] In at least some embodiments, the at least one receiver comprises a phase lock loop, a delay line and an XOR gate coupled to one another and configured to retrieve the clock signal.

[00166] In yet another aspect, in at least one embodiment described herein therein is provided a bus system comprising a bus; a master device coupled to the bus; and at least one slave device coupled to the bus; wherein the master device and the at least one slave device are configured to use a bus communication protocol to communicate over the bus and the at least one slave device is configured to operate in a sleep mode to reduce power consumption and in the sleep mode the at least one slave device will monitor every Mth data frame on the bus and discard all of the other traffic on the bus.

[00167] The parameter M may generally equal to N*L where N is a positive integer and L is a number of constant synchronization codes that are used.

[00168] The parameter M may be selected so that consecutive data frames that are monitored by the at least one slave device have consecutive constant synchronization codes.

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Figure 22b shows an example of a compressed format that can 5 be used to encode the PCLKD field of Figure 16a;

Figure 22c shows an example of an alternative embodiment of various field values that are set depending on the use of isochronous, asynchronous and multi-frame transfers in a given frame;

Figure 23 shows an example of a frame format when using 10 multiple data channels with divisions between the channels from the same port for achieving lower latency in word mode;

Figure 24 shows an example of a frame setup when data from multiple data channels are repeated several times in a frame in word mode;

Figure 25a shows an example of the definition of the 15 COMMAND SEPARATION field depending on the frame type used in the unified bus communication protocol;

Figure 25b shows an example definition of a number of subframe lengths that can be used in bitstream mode to reduce the time for synchronization;

Figure 25c shows an alternative example of the definition of the

COMMAND SEPARATION field depending on the frame type used in the unified bus communication protocol;

Figures 26a and 26b show examples of different frame formats that can be achieved by using different values for the HSTART and VSTART fields in bitstream mode;

Figure 27 shows the definition of the LSB, MSB and LSB+1 bits of the HSPACING and VSPACING fields for an example embodiment in bitstream mode;

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-32Figure 28a shows an example embodiment of a stereo system with current and voltage sensing that uses the unified bus communication protocol;

Figure 28b shows an example of a bitstream frame format that 5 can be used for the stereo system of Figure 28a;

Figure 28c shows another example of a bitstream frame format that can be used for the stereo system of Figure 28a and uses less bandwidth for the sensing signals;

Figure 28d shows an example of a bitstream frame format that 10 can be achieved by setting values for the HSTART, VSTART, HSPACING and VSPACING fields in bitstream mode where the bandwidth between the audio data and the control data is changed so that less bandwidth is used on the control data as compared to the audio data;

Figure 29a is an example embodiment of a definition of registers 15 that can be used for the master device;

Figure 29b is another example embodiment of a definition of registers that can be used for the master device;

Figure 29c is an example of a definition of sampling ratios for a first stage;

Figure 29d is an example of a definition of sampling ratios for an optional stage;

Figure 29e is an example of a definition of sampling ratios for a second stage;

Figure 29f is an example of a definition of sampling ratios for a third stage;

Figure 29g is an example of a multiformat decimator system that may be suitable for multiple sample rate ratios;

Figure 29h is an example of a multiformat interpolator system that may be suitable for multiple sample rate ratios;

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-33Figure 29i is an example of an interpretation of writing to the FRAME CONTROL field;

Figure 30 shows combinations of WRITE and READ operations based on the FRAME CONTROL field and example operations that can be monitored depending on the values of the FRAME CONTROL field in an example embodiment;

Figure 31 shows combinations of WRITE and READ operations based on the FRAME CONTROL field and example operations that can be monitored depending on the values of the FRAME CONTROL field in another example embodiment;

Figure 32a shows an example embodiment of the components of an INTERFACE CONTROL register;

Figure 32b shows another example embodiment of the components of the INTERFACE CONTROL register;

Figure 33a shows an example of how the MCLKD field can be encoded in at least one example embodiment that corresponds to the register definition of Figure 29a;

Figure 33b shows example frequency divisions that may be used to generate a clock signal for the bus in at least one example embodiment that corresponds to the register definition of Figure 29b;

Figure 34a shows an example embodiment of the subfields that can be used in the IRQ MASK register;

Figure 34b shows another example embodiment of the subfields that can be used in the IRQ MASK register;

Figure 35 shows an example timing diagram for changing the

FRAME DONE MASK field;

Figure 36a shows an example embodiment of the components of an INTERFACE STATUS register;

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-34Figure 36b shows another example embodiment of the components of an INTERFACE STATUS register;

Figure 37 shows an example definition for the slave status registers;

Figure 38a shows an example embodiment of a compact encoding format that can be used to encode a device ID for a slave device;

Figure 38b shows an example embodiment of a general encoding format that can be used to encode a device ID for a slave device;

Figure 39 shows a general word frame format used in word 10 mode for a single time frame;

Figure 40 shows an example embodiment of a word frame format for a single time frame;

Figure 41 shows another example embodiment of a word frame format for a single time frame;

Figure 42 shows an example embodiment of a bitstream frame format for a single time frame;

Figure 43 shows an example embodiment of a unified frame format for a single time frame;

Figure 44 shows another example embodiment of a unified 20 frame format for a single time frame;

Figures 45a and 45b show tables of example combinations of bus frequency, number and types of channels for the unified bus communication protocol when operating in word mode;

Figures 46a and 46b show tables of example combinations of 25 bus frequency, number of channels and oversampling rate for the unified bus communication protocol when operating in bitstream mode and using bitstream frame formats;

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-35Figure 47 shows a table of example combinations of bus frequency, number and types of channels for the unified bus communication protocol when operating in a hybrid word mode;

Figures 48a, 48b and 48c show tables of example combinations 5 of bus frequency, number and types of channels for the unified bus communication protocol when operating in bitstream mode and using unified bitstream frame formats;

Figure 49a shows an example embodiment of a general format for encoding N bits in digital word format in the unified bus communication protocol;

Figure 49b shows an example of some common oversampling factors that can be used with a bitstream encoding format for mobile phone systems;

Figure 49c shows an example of possible combinations for a 15 string encoding format;

Figure 50a shows an example embodiment of an algorithm that can be used to implement a fractional flow;

Figure 50b shows an example of the calculations of the algorithm of Figure 50a for an example scenario;

Figure 50c shows an example of various values that can be used for fractional flows for various playback scenarios;

Figure 51a shows an example embodiment of a control system with a display that uses the unified bus communication protocol;

Figure 51b shows an example embodiment of a mobile phone 25 system that uses the unified bus communication protocol;

Figure 52a shows an example embodiment of a house safety system that uses the unified bus communication protocol;

Figure 52b shows an example embodiment of a home entertainment system that uses the unified bus communication protocol;

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-36Figure 52c shows an example embodiment of a home entertainment system that uses the unified bus communication protocol;

Figure 52d shows an example embodiment of an instrumentation system that uses the unified bus communication protocol;

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-39Figure 74 is an example embodiment of a system that uses a single dimension, staggered ring topology to couple devices to a bus and the system uses the unified bus communication protocol;

Figure 75 is an example embodiment of a system that uses a 5 two-dimensional ring topology to couple devices to a bus and the system uses the unified bus communication protocol;

Figure 76 is another example embodiment of a system that uses pipe control to couple many devices to a bus and the system uses the unified bus communication protocol;

Figure 77a is a timing diagram for an example of 2X overclocked data slots;

Figure 77b is a table showing an example embodiment of timing parameter values that may be used for devices that utilize overclocked data slots;

Figure 77c is an illustration of data transfer and timing on a bus for an example in which there is overclocking by a factor of two;

Figure 77d is a table of example settings for a register to implement overclocking and an estimate of associated power savings;

Figure 78a shows a timing and voltage level scheme for sending 20 out multiple bits of data at a time;

Figure 78b is a table of example encoding that may be used when a device sends out multiple packed bits in a data slot using the overclocking mode;

Figure 79 is an example of data seen by a slave device during 25 the MASTER INITIATED DEVICE WAKE UP FROM SLEEP mode;

Figure 80a is an example of an alternative embodiment for various power consumption levels or power management modes that can be set for a port or a device using the unified bus communication protocol;

Figure 80b is a table of an example UART timing specification;

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-40Fig 81a is an example of a single wire signaling system utilizing two slots for synchronization and one for data;

Fig 81b is an example of a single wire signaling system to transfer both clock and data information utilizing two slots for synchronization and four slots for data; and

Fig 81c is an example of a single wire signaling system utilizing one slot for synchronization and four slots for data thereby increasing the bandwidth and lowering the power consumption.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[00177] Various systems or processes will be described below to provide an example of one or more embodiments of the concepts.

It is possible that a system or process described below is not an embodiment that is recited in any of the claims. Any concept disclosed in a system or process described below that is not claimed in this document may be the subject matter of another protective instrument, for example, a continuing patent application, and the applicants, inventors or owners do not intend to abandon, disclaim or dedicate to the public any such concept by its description in this document.

[00178] Furthermore, it will be appreciated that for simplicity and clarity of illustration, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein may be practiced without these specific details. In other

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- 41 instances, well-known methods, procedures and components have not been described in detail so as not to obscure the embodiments described herein.

[00179] It should also be noted that the term coupled as used herein can have several different meanings depending in the context in which the term is used. For example, the term coupling can have a mechanical, electrical, optical or communicative connotation. For example, in some contexts, the term coupling indicates that two elements or devices can be physically connected to one another or connected to one another through one or more intermediate elements or devices via a physical coupling, such as a wire or cable, for example. In some contexts, the term coupling indicates that two elements or devices can be connected through other means such as a wireless signal or an optical signal. In some contexts, the term coupling indicates that elements or devices may be communicatively connected to one another through a signal, such as an electrical, optical or wireless signal, for example. Furthermore, the term “communicative coupling indicates that an element or device can electrically, optically, or wirelessly send data to another element or device as well as receive data from another element or device.

[00180] It should also be noted that the terms “master” and as “slave” as used herein are meant purely from a technological point of view and in particular denotes the technical relationship between a host device or element and a peripheral device or element in which one element or device provides instructions or control signals to another element or device. Accordingly, the use of the terms “master” and “slave” as used herein is not meant to carry any connotation beyond the technical meaning given here.

[00181] It should also be noted that although the communication protocol is described as a bus communication protocol and various example embodiments are provided that show a physical bus that couples elements together, the various embodiments of the communication protocol described

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-42herein can also be implemented over a non-physical interface such as a wireless or optical interface.

[00182] The detailed description begins with a general description of a mobile device and then proceeds to describe example embodiments of a unified bus communication protocol that can be used to couple devices with a fewer number of wires while being able to support different types of data formats. Accordingly, the unified bus communication protocol acts as a unified interface for devices that generate numeric data in different formats but can be coupled to the same bus.

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-52register that provides a separation distance between the start of each block of command data. In another embodiment, the unit of measure is a nibble which equals four (4) bits. The frame length is determined by the command pattern and in one embodiment, in word mode, may be 48 bits with a default sync separation value of 28 nibbles thereby resulting in a frame length of 384 bits.

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-55reduction or avoidance of bus contention, or congestion, when multiple devices try to signal, or communicate over the bus 64, at the same time, since once the bus 64 has been discharged, the discharge of the bus 64 by subsequent devices is not detected and bus collision is not possible.

[00216] As can be seen by the example in Figure 4a, timing is implemented on the bus 64 such that the bus 64 is time-multiplexed in four time intervals. In alternative embodiments, it may be possible to use another number of time intervals. For the example of Figure 4a, in a first time interval, the master device 52 drives the bus 64 active low during the first 25% (i.e.

quarter) of the clock period. In a second time interval, the master device 52 drives the bus 64 active high during the second 25% of the clock period. The low-high clock transition may be used as a continuous sampling clock signal. In the third and fourth time intervals, the master device 52 leaves the bus 64 in a floating state for the remainder of the clock period unless the slave device

54 or the master device 52 pulls the bus low to signal a “1”. For example, in the third interval the slave device 54 may pull the bus 64 active low, for example, starting between 50-62% of the clock period. The bus 64 may typically be fully settled before the clock period is complete. The bus value is sampled in the fourth interval near the end of the clock period, for example, at

88-100% of the clock period, after which the master device 52 will begin to drive the bus 64 active low again. In one embodiment, the first half of the clock cycle may be used for the clock signal while the second half of the clock cycle may be used for the data transmission. However, other divisions of the clock cycle are contemplated in which a first percentage of the clock cycle is used for the clock signal and a second percentage of the clock cycle is used for data transmission, such as 67% for the clock signal and then 33% for the data transmission, for example.

[00217] In the example of Figure 4a, the bus 64 is initially active low at the beginning of the clock cycle. After a particular period of time, the bus 64 is driven active high by the master device 52. As the slave device 54 wishes to transmit a “0”, the slave device 54 does not do anything with the bus 64.

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-56The value of “0” is then read by the master device 52 and the slave device 54 before the master device 52 drives the bus 64 to an active low prior to the next clock cycle. During the second clock cycle, the master device 52 drives the bus 64 to an active high after a particular period of time. As the slave device 54 wishes to transmit a “1”, the slave device 54 pulls or drives the bus 64 to an active low where the value is then read by the master device 52 and the slave device 54. As the bus 64 is active low, the master device 52 does not have to drive the bus 64 active low, although it may perform that function as shown in Figure 4a. In the third clock cycle, after a particular period of time, the master device 52 drives the bus 64 to an active high. As the slave device 54 wishes to transmit a “1”, the slave device 54 pulls or drives the bus 64 to an active low where the value is then read by the master device 52 and the slave device 54. At the start of the fourth clock cycle, the bus 64 is active low and after a particular period of time is driven active high by the master device 52. As the slave device 54 wishes to transmit a “0”, there is no activity on the bus 64 until after the value has been read and then the master device 52 drives the bus 64 active low in preparation for the next clock cycle.

[00218] The bus timing allows for the slave device 54 to continue to pull the bus 64 active low during the period where the master device 52 drives the bus 64 active low. Therefore, the release timing of an output driver of the slave device 54 is not so stringent. However, the slave device 54 generates a floating output when the master device 52 drives the bus 64 active high, including line delays. The reason the floating period is longer than the active low period and the active high period is to allow the slave device 54 to drive the bus 64 active low in the same amount of time as the master device 52, and allow some tolerance to the time instant, when the activation starts, since the slave device 54 depends on the timing of the master device 52. Furthermore, there are delays on the bus 64.

[00219] The timing of when the bus 64 is pulled low by the master device 52 is after a particular period of time so that incorrect data is not sampled by the master device 52 or the slave device 54. Accordingly, the

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-57slave device 54 has a floating output when the master device 52 pulls the bus 64 high.

[00220] When the master device 52 or the slave device 54 enters the tristate, this is represented by dashed lines even though the actual voltage will be determined by the previous values written to the bus 64. As the period during which the bus 64 floats is very short, it may be kept stable due to parasitic capacitances coupled to the bus 64 or may be kept stable for longer periods of time by including at least one bus holder within the system 50. Therefore, the charge and the voltage on the bus 64 may be considered stable, if unloaded statically or loaded by high impedance.

[00221] The slave device 54 activates the bus 64 at certain time intervals, which can be done by implementing a local clock, using a PLL, a Delay Locked Loop (DLL) or a simple delay circuit. The delay circuit may comprise two capacitors that are being alternately charged by a fixed current and then using the charging voltage on the capacitors to determine the points where the bus 64 should be activated and sampled. These two capacitors may be charged from one fixed clock edge to the next fixed clock edge and discharged before starting this cycle. During long periods where information is not transferred, it is possible to let the bus 64 go idle by gating the clock signal to a high level. In this case, there will be a small delay in order to restart the bus 64. Since the master device 52 controls the timing, any analog controlled delays are generally not used.

[00222] In general, a small enough bus capacitance and a clock frequency that is sufficiently high is used so that the reading of the status of the bus 64 during the floating, or tri-state, period is uniquely defined. If the bus system 50 is implemented on a printed circuit board, in some embodiments, a small capacitor may be used to provide a significantly large charge to protect against data errors. In this case, a small but finite bus capacitance is used or alternatively implemented using a bus holder (e.g.

using two inverters coupled back-to-back) to maintain a stable bus value. This method may be chosen for low frequency operation of the bus 64, where

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-58small leakage currents may slowly discharge any charges left on the bus 64, but a bus holder will keep the value stable. The bus holder will normally be implemented in the master device 52 to limit the power efficiency loss associated with its operation but can also be implemented in the slave device

54 for data integrity purposes. The timing characteristics for an example embodiment of when the bus 64 is implemented using a single wire are shown in Table 1.

Table 1: An Example of Timing Characteristics for a Single Wire Bus

<td> PARAMETER</td><td> MIN</td><td> NOM</td><td> MAX</td><td> UNIT</td>

<td> Bus frequency (1.8 m cable) = EXTCLK/divider</td><td> 1</td><td> 6</td><td> 12</td><td> MHz</td>

<td> Duty cycle clock</td><td> 45</td><td> 50</td><td> 55</td><td> %</td>

<td> Setup time (slave device)</td><td></td><td></td><td> 5</td><td> ns</td>

<td> Hold time (slave device)</td><td></td><td></td><td> 5</td><td> ns</td>

<td> Slew rate (master device), charge</td><td> VDD*0.1</td><td></td><td> VDD*0.5</td><td> V/ns</td>

<td> Slew rate, discharge</td><td> VDD*0.1</td><td></td><td> VDD*0.5</td><td> V/ns</td>

[00223] An estimation of the maximum disturbance on the bus 64, if a lower clock frequency of 2 MHz is used (normally a 6 MHz clock frequency is recommended) can be made. Assuming a maximum leakage current of 10 μΑ, a period of 1 ps and a line capacitance of 100 pF, the maximum voltage drop is equal to about 0.05 V. When the clock frequency is increased further, the noise immunity increases. The output impedance of the master device 52 is about 75±12 Ω to match to a 75 Ω transmission line. When received at the end of the transmission line, the reflection will immediately bring the voltage up to the full level with little impact on the slew-rate. With these characteristics, the noise immunity will be better than that of an l2C type implementation. For a 2 meter long cable, an estimate of the cable delay is about 10 ns (delay approximately 20 cm/ns). The use of a 75 Ohm cable to implement the bus 64 has the advantage of lower capacitance per length than a 50 Ohm cable and lower electrical losses. The electrical characteristics for

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-59an example embodiment of the bus 64 when using a single wire is shown in Table 2.

Table 2: An Example of Electrical Characteristics for a Single Wire Bus

<td> PARAMETER</td><td> MIN</td><td> NOM</td><td> MAX</td><td> UNIT</td>

<td> lload (bus stopped, sync off, power transistor on), Vdrop = 300 mV (POWER MODE)</td><td></td><td></td><td> 30</td><td> mA</td>

<td> Bus holder output impedance (master device)</td><td> 600</td><td> 1200</td><td> 1800</td><td> Ω</td>

<td> Slew-rate limit (at master device) with 75 pF load or smaller</td><td> 0.3</td><td> 0.6</td><td> 1.0</td><td> V/ns</td>

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-62characteristics for an example embodiment of the bus 64 when using two wires are shown in Table 3.

<td> Table 3: An Example of Electrical C</td><td colspan="4"> haracteristics for a Two-Wire Bus</td>

<td> PARAMETER</td><td> MIN</td><td> NOM</td><td> MAX</td><td> UNIT</td>

<td> Bus frequency (0.30 cm PCB) = EXTCLK/divider</td><td> 0</td><td> 10</td><td> 20</td><td> MHz</td>

<td> Clock half period (high or low but not both)</td><td> 23</td><td></td><td></td><td> ns</td>

<td> Setup time</td><td></td><td></td><td> 2</td><td> ns</td>

<td> Bus holder (master device only)</td><td> 600</td><td> 1200</td><td> 1800</td><td> Ohm</td>

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-65fields, the fields may be ordered differently, or there may be other fields that are used or other registers that are used.

[00237] The DATA SYNCHRONIZATION field of the S word includes a parity bit PAR (S15) and an acknowledgement bit ACK (S14). The calculation of the parity bit is based on all traffic encountered on the bus 64 including the last parity bit written up to and including the last bit before writing the new parity bit (i.e. the parity may be calculated for a full frame). The parity bit is set to be one if the total number of bits equal to one in a frame is even; otherwise the parity bit is set to be zero. The initial parity value of the master device 52 at power-up is zero. In at least one embodiment, the master device 52 may write parity information for all operations (PING, READ, WRITE and FUNCTION) to ensure that any device that is attached to the bus 64 can detect a signal integrity problem or a data collision.

[00238] The acknowledgement bit is calculated based on traffic on the bus 64 in the last frame. The slave device 54 should signal a logic low, if the data transmission has been corrupted during a READ, WRITE or FUNCTION operation to the slave device 54. If there is no error in parity, the slave device 54 will respond with a logic one. This is useful for added security during I/O WRITE OPERATIONS. Based on the past operation, the slave device 54 sets the acknowledgement bit, since it knows if an error has occurred, e.g. that the parity bit is wrong or a bus error has occurred. If no slave device is present on the bus 64, a logic low will be returned from the bus 64, by nature of the bus signaling scheme indicating a problem to the master device 52. If the previous operation was a PING operation, any slave device that has detected an error based on the parity bit and the entire activity of the past frame may activate this bit (i.e. write a logic one). This means that the acknowledgement bit is effectively inverted during a PING operation (a logic zero means no error). If an error is detected, the master device 52 may activate an IO ERROR bit for a missing ACK bit after a READ, WRITE or

FUNCTION operation and BUS ERROR for NACK during a PING operation. In the example shown in Figure 6, which is a timing diagram showing

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-66operations to the DATA SYNCHRONIZATION field of the S word in word mode, the master device 52 writes an even parity in time slot 96, based on activity in time slots 0-95. The slave device 54 responds in time slot 97. During a READ, WRITE or FUNCTION operation, the slave device 54 will only respond in the case of an error (i.e. by NACK).

[00239] Referring now to Figure 7, shown therein is an example embodiment of the parity and acknowledgement calculation that is done by the master device 52 and the slave device 54 based on different command operations. If there is no error in parity, the device that is being addressed will respond with a logic one (i.e. active action). This is useful for added security during I/O WRITE operations. If there is a parity error during a WRITE operation from the master device 52 to the slave device 54, the slave device 54 does not complete the WRITE operation internally if there is a parity error and the master device 52 will respond to the bus controller with an IO ERROR interrupt. If there is a parity error during a READ operation from the slave device 54, the master device 52 will generate an IO ERROR IRQ, while the slave device 54 will not do anything if the master device 52 does not receive an active ACK. By reading the device register and the last written word, it is possible to identify which device is in question. Before performing a new

-72COMMAND field, two DATA SYNCHRONIZATION fields, a SLAVE DEVICE field, a BANK SELECT field, an ADDRESS field, a SLAVE STATUS field and a FUNCTION field. Some of the fields are only used during certain command operations as will be described. The FUNCTION field will be described when

FUNCTION operations are discussed below. In general, the first three bits (X15-13) are part of a command field that indicates the command that is being issued by the master device 52, such as a READ, WRITE, PING, FUNCTION or OTHER command, while the structure of the remaining bits will depend on the chosen command. Figure 9b provides an alternative embodiment for the

X word that may be used. This encoding has the advantage that it is possible to perform asynchronous, fractional or multiframe data transfers in any operation mode (PING/READ/WRITE/FUNCTION) at the cost of some complexity in decoding and activation of the BANK bit.

[00252] With regards to the COMMAND field (X15:X13), in at least some embodiments, the command can be an 8 or 16 bit READ/WRITE operation, a PING operation or a FUNCTION operation in this example embodiment (more or fewer bits may be used in other embodiments). In general, the PING command is active all the time, unless the master device 52 has received a READ, WRITE or FUNCTION command and is currently processing it.

[00253] In some embodiments, the X12 bit can be a BANK bit or BANK field that is used during a PING operation. When a PING command is issued, the master device 52 uses the BANK bit to indicate which register bank should be used for all devices for internal timing of data transfer. In audio applications, the BANK field can be used to switch between two register banks to avoid any glitches during playback while changing audio modes. In general, the BANK field can be used to switch between different register banks that specify different frame formats for different data modes that can be used for data transmission during a frame. The different data modes can specify different sampling rates, different channel selections, different port selections, using bitstream mode or word mode and the like for different audio scenarios. For example, in one data mode, data from data channels can be

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- 73defined to be placed in a first set of time slots in a frame and in a second data mode, the data from the same data channels can be defined to be placed in a second set of time slots in a frame. During frames that do not use the PING operation, the previous value of the BANK field may be used for register selection. When the slave device 54 is being addressed, it uses the BANK field to select which register bank to perform a READ, WRITE or FUNCTION operation on. The slave device 54 may use at least one shadow register for all registers that change in more than one data mode of operation. It may be used to select between internal registers and/or internal programs. In order to provide robustness against errors, the BANK field can be read more than once, such as twice, with the same value, before a change happens.

[00254] In at least one embodiment, in order to provide robustness against errors, the BANK SELECT field can be read more than once, such as twice, to ensure that there is the same value in this field in at least two consecutive frames, before a change happens, i.e. in this example a change of the register bank will take at least two frames.

[00255] The SLAVE DEVICE field (X11:X8) is used during READ, WRITE and FUNCTION operations. The SLAVE DEVICE field specifies the address of a slave device that is attached to the bus 64. All slave devices start to communicate with the master device 52 using an address of zero after power-up after which they will be assigned a new address by the master device 52. Slave devices with addresses 0-12 can communicate full status information to the master device 52. In this example embodiment, the address 15 is reserved for broadcast of information to all of the devices that are attached to the bus 64. This broadcast may be useful for using one command to reset all slave devices, for example.

[00256] A DATA SYNCHRONIZATION field (DS0-DS1 in X11-10) may be used to synchronize data over several frames and is transmitted during PING operations. The slave device 54 may select this field to synchronize the start of internal counters that select when data starts to be transmitted. If the slave device 54 uses the data synchronization bit DS0 or DS1 and it is set to

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-74one, the slave device 54 resets its internal counters (which can occur at a normal frame start), otherwise if the DSO or DS1 bits are set to 0 these internal counters are not reset. This is useful to synchronize the transmission of data that best fits into several frames e.g. for fractional flows.

[00257] A bit REQUEST (REQ) BUS ACCESS (X9) is used during PING operations. By activating this bit (setting it equal to one), another master device can request access to the bus 64.

[00258] A bit RELEASE (REL) BUS (X8) is used during PING operations. If the current master device activates this bit (a logic value zero for inverted logic), another master device is allowed to begin to send out commands to the bus 64. The current master device 52 may simultaneously send out commands, if it chooses to do so. Data arbitration will determine who wins the request for a specific command if there is contention between the two master devices. If another master device ignores the RELEASE BUS bit and begins to write in the command words when this field is inactive (e.g. logic one), this will be considered a bus error.

[00259] In an alternative embodiment, the X12-X9 bits can be used for data synchronization (DS0-DS3) as described above. Furthermore, the X8 bit can be used as the BANK bit as described above (e.g. see Figure 9b).

[00260] The ADDRESS field (X7:X0) is used during READ, WRITE operations and some FUNCTION operations and is the lower eight bit address that is used to select a specific register address inside the slave device 54. If 16 bit operations are used, the higher 8 bits may be assumed to be zero.

[00261] The SLAVE STATUS field (X7:X0) is used during PING operations and provides the status for a portion of the slave devices ST11 to ST8 (the remaining status information is provided in the Y word as will be described). In this example embodiment, all slave devices include a status register which consists of two bits. The value of the status register is used to determine which action the master device 52 should take for a given slave

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-75device. Each slave device responds with status information by writing to dedicated time slots for each slave device in the X and Y words. In this example, the total number of status bits is 24 and the slave devices transmit the most significant status bit first. The status bits may generate a master interrupt depending on the value of the interrupt mask bit. After a power-on reset event, all slave devices will start responding at slave address zero to signal that they have just been attached to the bus 64. In other embodiments, the status register of the slave devices may have more than two bits if there are more status levels that are used.

[00262] In this example embodiment, using two bits, the slave device 54 can have four different status levels. A status level of Ό0’ is the lowest status level and is the initial value inside the slave device 54 when the slave device 54 first attaches to the bus 64 but is not locked onto the bus 64 (i.e. not synchronized to the master device 52). Only logical ones will affect the physical operation of the bus 64 (due to the signaling scheme used in this example embodiment) so this status value will leave the bus 64 unchanged. A status level of ‘01’ signals that the slave device 54 has locked onto the bus 64 and can be used to detect when the slave device 54 connects to and disconnects from the bus 64. This may be monitored by reading the slave status level and enabling an interrupt using the ATTACHMENT bit. This value affects a PING operation. A status level of ‘10’ is used to request attention to the slave device 54 after it has locked onto the bus 64 (due to buffer level or an error condition, for example). This condition may be monitored by enabling the ATTENTION interrupt mask bit. This status level will delay a READ,

WRITE or FUNCTION operation, if both the SO and the SO DELAY IRQ mask bits are simultaneously active (i.e. a Ί’). A status level of '1T signals that the slave device 54 has an emergency situation that may have to be handled quickly such as, but not limited to, the temperature of the slave device 54 being too hot or there is a critical undervoltage or overvoltage at the slave device 54. This condition may be monitored by enabling the ATTENTION IRQ mask bit. This status level will also delay a READ, WRITE or FUNCTION

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-76operation, if the SO bit and the SO DELAY IRQ mask bit are simultaneously active (i.e. set to logic level ‘1’).

[00263] Referring now to Figure 10, shown therein are various fields and bit allocations for the Y command word for various command operations. The structure of the Y word will also depend on what operation is currently under way. In general, the Y word is used to communicate data and possibly address information between the master device 52 and the one or more slave devices 54. Figure 10 provides some example combinations. In this example embodiment, the Y command word comprises an ADDRESS field, a WRITE

DATA field, a READ DATA field and a FUNCTION field. Some of the fields are only used during certain command operations as will be described. These fields can be implemented using one or more bits of a register. In alternative embodiments, different implementations can be used for these fields, the fields may be ordered differently, or there may be other fields that are used or other registers that are used. The FUNCTION field will be described when FUNCTION operations are discussed.

[00264] The ADDRESS field (ADDR 7-0) is an eight bit address that may be used together with the address field in the X word to form a 16 bit addresses for the slave device 54.

[00265] The WRITE DATA field (WD15:0) includes data from the master device 52 that is to be written to a register in the slave device 54. For 16 bit WRITE operations, the entire word WD15:0 is used. For 8 bit WRITE operations, only WD7:0 is used. The register WD15:0 can be set by external control of the master device 52.

[00266] The READ DATA field (RD15:0) includes data that is to be read from the slave device 54 to the master device 52. For 16 bit READ operations, the entire word RD15:0 is used. For 8 bit READ operations, only RD7:0 is used. The register RD15:0 can be read by external control of the master device 52.

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- 77 [00267] Referring now to Figure 11a, shown therein is an example list of functions and corresponding bit settings in the X word. In other embodiments, other functions and/or bit settings can be used. For example, there can be other embodiments which use different sub-combinations of the functions listed in Figure 11a. These embodiments could add other functions, remove certain functions or both add some functions and remove other functions. The FUNCTION operation may be used to start the execution of special commands that are useful for the control of system functionality and device control. Some functions support broadcast, i.e. all ports (e.g. slave devices) are affected by this command. The upper bits of the FUNCTION field in the X word (X7:X4) is equal to 0000 for all the functions defined in Figure 11a. If a function has not been implemented, the slave device 54 should not acknowledge (ACK) the corresponding request from the master device 52. If the master device 52 is writing to multiple slave devices, the slave devices can use not acknowledge (NACK) instead in this example embodiment.

[00268] The execution of the REQUEST ID function (X3:X0 = 0000) is used to uniquely identify the master device 52 used in a system or to distinguish between multiple slave devices attached to the bus 64 so that the master device 52 is able to differentiate between these slave devices and assign each of them a unique individual slave a number (e.g. 1-14). This enables support for several slave devices to be connected to the master device 52 via the bus 64 at the same time and avoids address collision problems (which are typically seen with the l2C bus protocol). Each slave device has a manufacturer part ID. This name will consist of a manufacturer code and a part number. In at least one embodiment, the manufacturer code is used during arbitration to assign an individual device address to each slave device that is connected to the bus 64. The situation of slave devices having identical part numbers can be handled by adding position information, as described below.

[00269] After a reset event has happened on the bus 64, all slave devices will start by looking at slave address zero (i.e. register address

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-780x0000) for setup information. The master device 52 will initiate the address arbitration process by writing to address zero and then reading from this address as described in the dynamic address assignment process which is described later in this description. Since there is only a single master device

52, the position field will be equal to “0000” when reading from the master device 52.

[00270] After a power-on reset event, all slave devices will set their device address to zero and the master device 52 communicates with the slave devices to assign addresses to them. After the slave device 54 has locked on to the bus 64 it will indicate a status of “01” or higher during a PING operation and the master device 52 will discover that a new device has just attached to the bus 64. The master device 52 will start the arbitration process by activating the REQUEST ID function. When the slave device 54 receives this request, it enables an internal name character counter which is used to encode an internal identification, i.e. a unique name, associated with the slave device 54. Slave devices that have not locked on to the bus 64 at this moment will not be activated and will not respond during this arbitration cycle. Furthermore, if no slave devices are currently connected to the bus 64, the master device 52 continues to complete the frame and then issues a further

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-81 connected in a ring topology). This topology has the advantage that more than 9 positions can be obtained, but the disadvantage that if a single device fails, the enumeration will also fail. Thus, it is more prone to errors and less robust as compared to the configuration in Figure 11b which uses a fixed address of 0-8 in this example (other ranges can be used in other embodiments). In both cases, the devices should first attach to the bus 64 after the enumeration of the internal position has been completed. This process will take longer for the ring topology, since each device typically waits until it has received information from the previous devices or it has been confirmed that it is the first device in a ring.

[00274] In an embodiment, if the slave device 54 enters a hardware error condition and is reset, its slave address is set to the default value of zero. If the slave device 54 loses synchronization with the master device 52, it disables its output and tries to regain synchronization with the master device

52. The slave device 54 should keep its current device address and start searching using the last obtained command separation value (which is described later in this document). After regaining synchronization, the slave device 54 may signal a bus error by setting its device status to “10”. The master device 52 will then ask the slave device 54 for the error type and it may respond with SLAVE_SYNC_ERROR or “OxFF” at device address zero, register address zero. If the slave device 54 receives an IO request other than a READ operation from address zero, before it has completed the read sequence, it should back off and terminate the process. In an embodiment, if the slave device 54 loses synchronization during operation and cannot resynchronize, then the master device 52 will know of this event within two frames by use of the PING operation and then change the value inside the STATUS register inside the master device 52 and set the ATTACHMENT bit.

[00275] To summarize, the slave device 54 deactivates the outputting of a slave address under the following circumstances: after power-on reset, when the slave device 54 is not locked onto the bus 64, when the slave device 54 has lost synchronization with the master device 52, when another

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-82 slave device has won arbitration and when the slave device 54 has completed outputting its own name ID.

[00276] The slave device 54 resets its own registers and prepares for a reading of its ID when the master device 52 starts the FUNCTION

REQUESTJD and the device address written by the master device 52 is equal to the slave device 54. If another slave device locks onto the bus 64 after this event happens, it should not start arbitrating even if its device address matches the master device address since it has not received the REQUESTJD command. Thus, after power-on reset or immediately after the slave device has attached itself to the bus 64, it should not be allowed to participate in arbitration, unless it has received this command from the master device 52.

[00277] The execution of the HARD RESET function (X3:X0 = 0001) may be used to reset an entire slave device, which is similar to a power-on reset operation.

[00278] The execution of the SOFT RESET function (X3:X0 = 0010) may be used to reset all functionality except the previous programmed device address and synchronization engine. In general, the internal registers and functionality for a slave device will be the same as after a power-on reset event except the slave device is already locked onto the bus 64 and has already been assigned an address. This means that the slave device will behave as it would after a power-on reset event with the exception that the slave device is already attached to the bus 64 and has already been assigned an address that is different from zero. This can be used to correct for internal or external errors faster than when resetting all registers inside the slave device, having the slave device to lock on to the bus 64, and then assigning an address before the slave device can be programmed again.

[00279] The execution of the REQUEST CAPABILITY INFORMATION function (X3.X0 = 0101) may be used to get information about the capability of the master device 52 or the slave device 54. This can be used for automatically setting up ports. This function works by reading values from

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-83register zero and register one, just like the REQUEST ID function. The information that is returned corresponds to the port that is being addressed. When all information from channels connected to a port has been read, zeros can be returned instead, indicating an end of the information. In this example embodiment, the ports are defined consecutively.

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-86the absolute and relative calibration data functions may be combined into a single command and the addressed slave device will either be requested to respond with either of these values or it may itself tell the master device what type of calibration information is available (i.e. relative or absolute calibration data).

[00288] The execution of a READ AND INCREMENT ADDRESS function (X3:X0 = 1000) may be used to read 16 bit data as specified by the register ADDRESS inside the slave device 54 and transfer the contents of this register to a Y word. Afterwards, the value of the ADDRESS register inside the slave device 54 is incremented by one.

[00289] The execution of a WRITE AND INCREMENT ADDRESS function (X3:X0 = 1001) may be used to take the 16 bit data in the Y word and write this data to the address specified by the register ADDRESS inside the slave device 54. Afterwards, the value of the ADDRESS register inside the slave device 54 is incremented by one.

[00290] The execution of an EXECUTE FUNCTION AT ADDRESS function (X3.X0 = 1010) may be used if the slave device 54 comprises a processor, in which case this processor will perform a jump operation to a subroutine with the 16 bit address defined by the Y word at the start of the next frame.

[00291] The execution of an EXECUTE FUNCTION AT ADDRESS INDIRECT function (X3:X0 = 1011) may be used if the slave device 54 comprises a processor, in which case the processor will perform a jump to a subroutine with the address that is contained inside the memory cell defined by the Y word at the start of next frame.

[00292] The execution of a PERFORM DEVICE SELF TEST function (X3:X0 = 0100) may be used to perform a device self-test, which may be done for debugging and production testing, for example. The result of the self-test will result in error codes or no error codes. For error codes, see the description of the READ LAST ERROR function. A low level interrupt will be

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[00301] The ACTIVATE field (reg. 0x03, B7) may be used to define the function of a data stream and how it is controlled. If an input stream is deactivated, the output will be zeros. If an output stream is deactivated, nothing will be written to the bus 64.

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-90[00302] The PREPARE bit (reg. 0x03, B6) may be used to define the circuits associated with the current selected port that will be turned on. When reading from this bit, the current status of the port will be returned (a logic one means the port is ready to begin data transfers). This can be used to ensure all circuits are ready and no glitches occur when data transfers begin.

[00303] In an alternative embodiment (e.g. Figure 16b), a POWER LEVEL field (reg. 0x02, B6:B4) may be used to set the power consumption and mode of operation of individual devices, ports and channels in order to optimize the power consumption for a system. System components can operate in several modes that can be used to minimize the power consumption. For example, individual channels can be selected using the CHANNEL SELECTION field. Channels that are not selected may be set in a low power mode of operation, in order to save power. For instance, in one usage of the unified bus communication protocol, until the PREPARE bit has been activated, all channels may be in a low power mode of operation. After the PREPARE bit has been activated, the channels that have been selected in the CHANNEL SELECTION field may be put into normal operation mode. By reading the status of the PREPARE bit, it is possible to know when the channels that have been selected are ready to receive or transmit data and can be activated by using the ACTIVATE bit (i.e. the PREPARE bit will be at a logic one level when all selected channels are ready), such as, but not limited to, after some device dependent initial power on delay, for example.

[00304] In at least one embodiment, when no power is applied to a device, the bus 64 may still be able to continue operation, i.e. ESD structures should not stall the bus 64 when no power is applied to the slave device 54 or the master device 52.

[00305] Referring now to Figure 17, shown therein is an example of various power consumption levels in an example embodiment. In this example, the power consumption scaling is defined by function and is not absolute. In other words, the exact power levels indicated in Figure 17 may vary for different slave devices. Furthermore, for the power consumption

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-91 levels defined by B6:B4 = 011 to 111, the port or device may or may not be fully functional. If the power consumption of an entire device is to be set, the port for broadcast (15) may be used. A port or device may support only a few power levels. In an example embodiment, if the master device 52 writes a value for the POWER LEVEL that is not supported by the slave device 54, it can be mapped to the closet value that is supported. The default value for the POWER LEVEL field is 010 (i.e. SLEEP mode).

[00306] Referring again to Figure 16a, the IRQ23 MASK field (reg. 0x03, B5) is used to enable or disable interrupts from a slave device communicated over the bus 64 as slave status levels ‘10’ and ‘11’ that would normally activate the SO bit. When the IRQ23 MASK field is equal to one, the slave device 54 will issue a high level interrupt when the internal logic indicates that the slave status level is a level two or a level three (i.e. the slave device 54 is requesting an interrupt and is allowed to admit this interrupt to the bus 64).

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-94address 15 will affect all ports connected to a specific slave device. Furthermore, the slave address 15 is also reserved for broadcasting, i.e. a WRITE operation to this address will affect all slave devices. Therefore, a write to the slave address 15 and to port 15 will affect all devices and all ports in the system (e.g. for shutdown or simultaneous activation of data at the same time). Port 124 is a custom port (meaning that it comprises a nonstandard interface such as l2C or l2S for a parallel connection using a direct wire for every data bit) that is connected to two channels of the ADC 128. In an alternative embodiment, there can be more than two channels and the port

124 may be connected to more than two channels. The ADC 128 is connected to one or more devices which generate data, such as a microphone, a current sensor, a voltage sensor, a pressure sensor, a temperature sensor and the like. There can be embodiments in which two of the same type of device are connected to the ADC 128 such as two microphones positioned at different locations. Port 126 is connected to two channels of the DAC 128. In an alternative embodiment, there can be more than two channels and the port 126 may be connected to more than two channels. The DAC 126 is connected to one or more devices which receive data, such as, but not limited to, an output speaker, a digital FM receiver, a digital FM transmitter, a Bluetooth interface, a vibrator, a temperature sensor, a sensor monitoring the status charging of a battery, an accelerometer, a gyroscope, a GPS receiver or a digital compass, for example.

[00314] The slave device 54b comprises a mux and sync engine 140, ports 142 to 152, ADC 154, DAC 156, and I/O 158 and 160. The I/O 158 and

160 can be a stereo ADC (represented as two channels) and a four channel

DAC (represented as four channels) respectively for example. Ports 142 to 148, ADC 154 and DAC 156 are similar to ports 122 to 126, ADC 128 and DAC 130 except that more channels are used for port 146 and ADC 154 compared to port 124 and ADC 128. Port 150 is configured to send or receive data according to the l2S protocol to I/O 158 which is in turn connected to an l2S interface. Port 152 is configured to send or receive data according to the l2C protocol to I/O 160 which is in turn connected to an l2C interface. The port

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CURRENT BANK bit is used by the master device 52 to select the active register bank.

[00321] It should be noted that conventionally, switching between these different data modes is done by decreasing volume, changing the settings for the register, and then increasing the volume. Advantageously, an aspect of the unified bus communication protocol is the ability to immediately switch between data because the registers can be switched and the active register is shown in the PING operation; e.g. it is possible to change the audio scenario with no clicks in the audio output.

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- 100[00329] Configurations 3 and 4 are used for fractional synchronization, e.g. for data sampled at 44.1 kHz in a 48 kHz channel. In this case, the transmitting device may extend the transmission of data from a single port into several frames. In this case, the DS0 and DS1 bits are valid every third frame and are used to reset the internal fractional phase adder (fractional counter) that is used to determine if the samples are valid or not when these bits are not active. The start of this transmission is signaled by setting the DS0 or DS1 bit to a logic one. The transmitter either located in the master device 52 or the slave device 54 can control the flow of data by activating the DS0 and

DS1 bits.

[00330] Referring once again to Figure 16a, the SUBGROUP field (reg. 0x05, B5:B3) may be used to group channels from a given port up into several subgroups in order to lower latency for the sources that provide data for the channels in the subgroup. When the number of channels that are transmitted is equal to the value of the SUBGROUP field, the transmission of data from these channels will stop for a number of time slots equal to the number of nibbles specified in the SKIP field and then be repeated. If the SUBGROUP field is equal to “111” then the SUBGROUP field will be ignored and data from the channels in the port will be transmitted in one group (e.g. there will be no subgroups). The default value is “111”.

[00331] Figure 23 shows an example of a frame setup (i.e. frame format) when using multiple channels with divisions between the channels from the same port for achieving lower latency in word mode and the SUBGROUP field is used to split data from the channels of the port into several subgroups. The

SUBGROUP field is composed of two multipliers specified by B3 and B4:B5, respectively. The number of channels transmitted before a SKIP occurs is equal to the product defined by the fields B3 and B4:B5. As can be seen from the example in Figure 23, the SUBGROUP field specifies how many channels are grouped together in subgroups and this may be done for all active channels for a port. Therefore, in one example, if the port of Figure 23 has four channels that provide Audio 0, Audio 1, Audio 2 and Audio 3, then the

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- 112bitstream mode field (reg. 0x05, B5:B3). The previous definition of the SUBGROUP parameter is then not possible, and all ports will transfer all data from all selected channels without any interruptions in between these data channels. The TDM WORDS TRANSFERRED in bitstream mode field indicates which bitstream frame channels in a bitstream frame format are used to transfer word data. In an embodiment, bitstream frame channels 0-7 can be used to transfer Time Division Multiplexed (TDM) data.

[00360] TDM data are digital words that can be supported in bitstream mode as will be explained. The bitstream frame channel 0 is used as the control channel and is mapped to no data output since it is only used to send bits from an S word, X word or Y word in this example embodiment. In the bitstream mode, the DS0 bit can be used to indicate the start of data transmission in order to support numerous data channels within a single bitstream frame channel or to support data lengths that are not compatible with the bitstream frame length, which is 48 bits in this example embodiment due to sending an S word, X word and Y word in each frame with no gaps in the control channel and in which these words are 16 bits each. For example, when four data channels each having 16 bits, which equals 64 bits in total, have to be sent in one frame channel in bitstream mode, this can be done using data synchronization across several frames. In other embodiments, there can be spacing between the control words, even in bitstream mode, to allow for better synchronization of TDM words that are placed in bitstream channels.

[00361] Referring now to Figure 29a, shown there is an example of a definition of registers that are can be used for the master device 52. An alternative embodiment is shown in Figure 29b but the following description will focus mainly on the embodiments related to Figure 29a. The registers are generally separated into three groups that provide the following functions: address port, command port and setup port. The registers provide values for a plurality of fields that will now be described. It should be noted that in alternative embodiments, other registers can be defined and these fields can

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- 113be implemented using one or more bits of a register. In alternative embodiments, different implementations can be used for these fields, the fields may be ordered differently, or there may be other fields that are used or other registers that are used.

[00362] A COMMAND SEPARATION field (reg. 0x08; B7:B0) is 8 bits long and represents an unsigned integer in an embodiment. The function of the command separation register will depend on the value of the frame format type as shown in Figure 25a. Figure 25c shows an example of an alternative embodiment of the definition of the COMMAND SEPARATION field depending on the frame type that is used in the embodiment of the unified bus communication protocol. Figure 25c is used in conjunction with Figure 29b.

[00363] If the frame type is set to word mode, a word frame format is used and the command separation distance is specified in units of nibbles (i.e. four bits) and gives the distance between two command words, not including the command word itself. The separation value may be zero in which case only the command information is transferred to the bus 64 (this is shown in Figure 40). The default value can be set to be equivalent to a default frame length of 48 bits which enables an increase in bandwidth for programming registers thereby allowing the bus 64 to be quickly setup and the attached slave devices to quickly obtain synchronization with the master device 54.

[00364] If the frame type is set to bitstream mode, a bitstream frame format is used and the control bits will be interlaced between data bitstreams. In this mode, the command separation register will give the number of data bits between the command bits. For example, a value of three in the

COMMAND SEPARATION field means that a command bit will be encountered every four bits (i.e. the command bits will be separated by 3 bits which may be data bits or empty time slots). In bitstream mode, the S, X and Y words are spaced between the bitstream data, resulting in low latency for the bitstreams. If bitstream mode is used, in at least one embodiment, an address may first be assigned to all slave devices before the master device 52 begins data communication and send out zeros in all data slots until all

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- 114slave devices have obtained synchronization with the master device 52 in order to reduce the time-to-lock for all of the slave devices. If the slave device 54 gets out of lock with the master device 52, the slave device 54 may try to regain synchronization with the previous value of the COMMAND

- 117are already defined. By setting the FRACTIONAL field, the fractional oversampling ratio Y/X is defined as the ratio between the FRACTIONAL HIGH (i.e. Y) field and the FRACTIONAL LOW (i.e. X) field. For the master device 52, this function is used to control fractional data flows and is optional.

The default value is all zeros. The FRACTIONAL HIGH (X) field and FRACTIONAL LOW (Y) field may also be used to define the oversampling ratio used by decimators and interpolators. In other embodiments, the encoding of this field may be different, but is still used to indicate the ratio between two binary encoded words.

[00373] An ADDRESS field (registers OxOC and OxOD) may be used to select which register the master device 52, and optionally the slave device 54, performs a READ, WRITE or FUNCTION operation on. It can also be used by slave devices when executing internal functions.

[00374] A FUNCTION field (reg. OxOE) may be used to define what operation is initiated when starting a FUNCTION operation using the FRAME CONTROL register.

[00375] A frame control register field (reg. OxOF) may be used which has the following fields: FRAME CONTROL, CURRENT BANK and SLAVE DEVICE ADDRESS. These fields can be implemented using one or more bits of a register. In alternative embodiments, different implementations can be used for these fields, the fields may be ordered differently, or there may be other fields that are used or other registers that are used. For example in an alternative embodiment, the frame control register field may comprise DATA SIZE and POWER fields.

[00376] The FRAME CONTROL field (reg. OxOF, B7:B5) may be used to initiate READ/WRITE/FUNCTION operations and to monitor the progress of WRITE operations. An example of an interpretation of writing to this field is shown in Figure 29i. When reading from this field, the value returned will be equal to the current frame operation. After writing to this field, the desired operation can be executed once. After this, the operation can be a PING operation in this example embodiment. The FRAME CONTROL register

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- 118selects the mode of operation for the next frame. Therefore, in order to initiate a READ operation, the correct three bit code constant for a READ operation (either 8 or 16 bits read data) is written to the FRAME CONTROL register inside the master device 52, after which a device register READ operation will start in the next frame.

[00377] The CURRENT BANK field (reg. 0x0F, B4) may be used to select the current register bank the slave device 54 should use to specify parameters for data transfer. This field has a different meaning during PING and other operations. The default value is zero. During a PING operation, this field can be used to select which memory bank is used to control the slave device 54. Therefore, in order to change the frame format or audio mode, a PING command is first issued that changes the CURRENT BANK bit so that the devices attached to the bus 64 may use a different memory bank. During other operations, such as READ, WRITE and FUNCTION operations, for example, this field can be used to select which memory bank the current operation (i.e. READ, WRITE or FUNCTION) is applied to. This can be used to select between two alternate register sets to seamlessly switch between two data different modes without any glitches in the output such as switching between two different audio modes without any glitches in audio output. The slave device 54 should internally update its own registers so that the new setting is used at the start of next frame. One way to do this it to bit copy the CURRENT BANK bit onto the BANK field (X12). All values in slave registers 0x02 to 0x07 are selected by the X12 time slot (i.e. in the X word). In an example embodiment, every slave device can have two modes of operation for streaming of data to and from ports. The actual change between data modes will happen after two frame boundaries after the transmission of the X command word (i.e. the slave device can first change its internal bank when two equal readings of the X12 bit has been obtained, for example). This means that when the BANK bit is changing from one value, e.g. zero, to another value, e.g. one, the slave device will use an auxiliary register bank (e.g. an alternative set of registers 0x02-0x07) with different values than those that were used previously. This change happens in all slave devices after the

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- 119second frame where the BANK bit has changed in a PING frame. The two register banks are selected during READ, WRITE and FUNCTION operations by the same BANK bit. The CURRENT BANK bit is used by the master device 52 to determine the value of the X12 (BANK) bit for the next frame.

[00378] The SLAVE DEVICE ADDRESS field (reg. OxOF, B3:B0) has B3 as the most significant bit and may be used to specify the selected slave device address. The default value after reset is “0000”. When the slave device address “1111 is used, the command will be broadcast to all devices. However, one should be careful about use of the broadcast command since it can result in ambiguity if reading from multiple devices at the same time. There can also be embodiments in which specific groups of devices selected by the master device 52 can be defined so that several devices can be selected at the same time as will be described in more detail below.

[00379] An INTERFACE CONTROL register (reg. 0x010) may be used to control the basic operation of the bus 64 such as setting the operating frequency, the clock source and selection of multi-master device operation. In an example embodiment, the INTERFACE CONTROL register comprises the following sub-fields: MCLKD, CLOCK SOURCE, ENABLE MULTI MASTER, ENABLE MASTER IRQ, and REQUEST MULTI MASTER which are also shown in Figure 32a (an alternative embodiment corresponding to Figure 29b is shown in Figure 32b). These fields can be implemented using one or more bits of a register. In alternative embodiments, different implementations can be used for these fields, the fields may be ordered differently, or there may be other fields that are used or other registers that are used. The default value of the INTERFACE CONTROL FIELD after a reset event is set to “00010000”.

[00380] The MCLKD clock division field (reg. 0x10, B7:B4) may be used to set the frequency of the clock signal used for the bus 64 (i.e. clock bus signal). In an embodiment, the frequency of the bus clock signal may be derived from an external clock source signal (EXTCLK) by using frequency division. The frequency division is determined by the MCLKD field of the INTERFACE CONTROL field. In an example embodiment, the external bus

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[00398] The IO ERROR field (reg. 0x12, B6) may be used to indicate an error during a READ/WRITE/FUNCTION operation or a parity error during a

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- 130operation is complete, this bit will be reset again immediately after a valid ACK in S14. If the slave device does not acknowledge the READ operation, the ERROR IO field will be set, and the RDC field will not go low. In this case it will first be reset after reading this register. In an alternative embodiment, this bit may be used to indicate the change of any bit (e.g. COMMAND ERROR) within the X and Y words that is done by a device other than the main master device. This bit is active high. In some embodiments, the field COMMAND ERROR will become active if any bits within the command words (S, X, Y) have been changed to a value that is not compatible with what is allowed by the master device 52. As an example, if a bit within the S word or the command type (B15:B13) in the X word are changed, this is an indication of electric noise or of another device trying to take over the bus 64. If however, another device has made a request to be able to control the bus 64 (via the REQUEST BUS command) and the master device has allowed this (via the RELEASE BUS command), then changes in the X word should be allowed and not result in the activation of COMMAND ERROR.

[00403] The FRAME DONE field (reg. 0x12, B0) may be used to indicate that a frame has been completed. The FRAME DONE field is set active high at the last bit of a frame. Accordingly, the FRAME DONE field may be used to synchronize operations with a basic timing of the bus 64. In an embodiment, the FRAME DONE field is still valid when a device is being charged, no data communication is active and the frame counter is usually running internally. The FRAME DONE field will continue to be set until the status register has been read. The FRAME DONE field can be used to tell if a PING operation has been completed or for basic timing, e.g. to count a certain number of frames before starting communication to ensure that all devices have been charged. When the corresponding IRQ MASK bit is enabled, an interrupt will be generated at the end of every frame.

[00404] The SLAVE STATUS registers (regs. 0x13 to 0x15) may be implemented using registers that reside inside the master device 52 and will indicate the status of the slave devices that are attached to the bus 64 with a

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- 131 slave address 0-11. These registers contain 12 values, each being two bits, corresponding to the status of slave devices 0-11 for a total of three bytes. In some embodiments, it is not possible to directly monitor slave devices 12-14 (device 15 is reserved for broadcast), but they can still issue an interrupt through activating the SO bit. In some alternative embodiments, the addresses 12-14 are used to address groups of devices as will be described in more detail below. In either case, the status values are read during a PING operation. The highest status value read from any slave device is compared to the corresponding two bit unsigned status bits. If this slave status value is larger than the value in these bits, these bits are updated to this new value. When the SLAVE STATUS register is read, its value is not cleared but will be overwritten during the next PING operation, i.e. if a maximum value of “11” has been read from the SLAVE STATUS register from one slave device and the maximum value during the next PING operation is “10”, the SLAVE

STATUS registers value for this device will be updated to “10” at the completion of the next PING operation. The initial value of all three SLAVE STATUS registers is “00000000” after a reset operation. If no slave devices are present on the bus 64, nothing will be activated and a constant high level will be read on the bus 64, which is equal to a logic zero since a negative logic signaling scheme is used for this example embodiment of the bus 64.

[00405] With respect to the alternative example embodiment of Figure 29b, there are different register definitions in comparison to those shown and described for Figure 29a. In particular, the definition in Figure 29b includes a FRAME RATE field, an OVERSAMPLE (X) field, an OVERSAMPLE (Y) field, a MULTI MASTER field, a POWER CONTROL field, and a CLOCK DIV field. Other fields are similar to those shown in Figure 29a but may be located at different registers and/or have a different number of bits assigned to the fields and will generally not be discussed with respect to Figure 29b. The OVERSAMPLE (X) OVERSAMPLE (Y) fields correspond to the FRACTIONAL (LOW) and FRACTIONAL (HIGH) fields of Figure 29a and will not be discussed. The MULTI MASTER field of Figure 29b has a different meaning compared to the ENABLE MULTI MASTER field of Figure 29a as will be

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- 132discussed. The CLOCK DIV field is similar to the MCLKD field of Figure 29a and will not be discussed.

- 143Therefore, in this example, two virtual frame channels are used to carry data from four word data channels. For example, frame channel 6 has bitstream data that corresponds to word data channel C and word data channel A. Frame channel 6 is used to either receive or send data to a device that uses word data channel C and either receive or send data to a device that uses word data channel A. The time slots are used for word data channel C first and then word data channel A. In addition, frame channel 7 has bitstream data that corresponds to word data channel D and word data channel B where the time slots are first used for word data channel D and then word data channel B. In this case, the data in the virtual frame channels are a bitstream version of digital word data as it is sent on the bus 64. The data synchronization bit (DSO) may be used to synchronize bitstream data that corresponds to word data across several frames to avoid ambiguity on when data for a data channel starts and stops (e.g. A or C). In order to save space, the DSO and DS1 bits are transferred in the middle of a PING frame, i.e. not just before a frame starts. These bits are used to reset a fractional counter to a known value (e.g. zero) which is then incremented by a given phase during every subframe thereafter. The overflow bit is then used to select if it is data from source (i.e. data channel) A or source C. The frame starts at the first bit after the S word at which time the corresponding one or more slave devices have been updated about register bank selection and data synchronization. At the various devices that use word data channels, the digital word data is multiplexed with bitstream data for transmission on the bus 64 or demultiplexed from the unified bitstream version into word data where it is used by the device. As an example, a system could contain two digital amplifiers that receive bitstream data and a connection to a Bluetooth or digital FM receiver or transmitter. The first slave devices (i.e. the amplifiers) would use bitstream data or multiplexed TDM data while the other devices would use multiplexed TDM data.

[00439] In this example, the frame channels start at bits 0 and 8 of each row and are sent one bit at a time from each frame channel. Accordingly, the command separation value is equal to 7 bits (i.e. there is a command bit from

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Integrated Circuit (ASIC) or some other processing circuit as is known by those skilled in the art. In this example, the bus 232 has a two-wire implementation in which one wire is used to transmit a clock signal and another wire is used to transmit data, synchronization and command data. In this example, the processing unit 222 acts as the master device and the slave devices are the ADC 224, the ADC 226, the DAC 228 and the display 230.

[00467] Referring now to Figure 51b, shown therein is an example embodiment of a mobile phone system 250 that uses the unified bus communication protocol. The mobile phone system 250 can be a cellular phone or a smart phone, for example. The mobile phone system 250 comprises a baseband processor 252, a CODEC 254, a Class-D amplifier 256, a capacitive sensor 258, an IR sensor 260, a class-D amplifier 262, an

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-156FM radio 264, a Bluetooth module 266, four microphones 268 to 274 and two buses 276 and 278. The bus 276 is used to couple elements 252 to 266 and the bus 278 is used to couple elements 252, 254 and 268 to 274. In this example, the buses 276 and 278 are implemented using a two-wire bus embodiment as described previously. Furthermore, in this example, the baseband processor 252 acts as a master device and the other elements 254 to 274 act as slave devices. There can be applications in which more than one bus is used to make the system more energy efficient since when many devices are coupled to the same bus, there will be an increase in capacitive losses and less energy efficiency. In addition, the different buses can have different clock speeds with a lower clock speed being more energy efficient. Another aspect of the unified bus communication protocol is that it may be used on buses that connect low cost digital accessories to the mobile phone system 250.

[00468] Referring now to Figure 52a, shown therein is an example embodiment of a house safety system 300 that uses the unified bus communication protocol. The house safety system 300 comprises a controller 302, a radio modem 304, a telephone line 306, a gas sensor 308, a Carbon Dioxide (CO2) sensor 310, switches 312 to 318 and a bus 320. The switches

312 to 318 are each connected to a slave device to give a logic zero output or a logic one output, which depends on the status of the switch (e.g. the window or door is open or closed). Even though there would be a small additional cost of including a slave device with each of the sensors, this would be offset by the lower installations costs, which may greatly exceed the added cost of a slave device. The controller 302 can be implemented by any processing unit described herein. The bus 320 can be implemented as a single wire embodiment in which the clock, data, command and synchronization information are sent on the same bus line. The bus 320 couples the controller 302 to elements 308 to 318. The controller 302 acts as a master device and the elements 308 to 318 act as slave devices. The radio modem 304 and the telephone line 306 may be used to communicate with a supervising central station or a home owner that could directly check the status of the line and

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- 157report to an appropriate authority when a warning arrives (e.g. telephone the owner, fire department, police, etc. when certain conditions occur). The radio modem 304 can serve as backup in case the telephone line 306 is down or broken.

[00469] Referring now to Figure 52b, shown therein is an example embodiment of a home entertainment system 350 that uses the unified bus communication protocol. The home entertainment system 350 comprises a DVD player 352, an amplifier 354, speakers 356 to 362 and a bus 364. The bus 364 couples the DVD player 352 to the amplifier 354. The bus 364 can be implemented as a single wire, for example, in a standard digital cable. In this example, the DVD player 352 acts as a master device and the amplifier 354, along with the four audio channels for the four speakers 356 to 362, acts as a slave device.

[00470] Referring now to Figure 52c, shown therein is another example embodiment of a home entertainment system 400 that uses the unified bus communication protocol. The home entertainment system 400 comprises a DVD player 402, an HD TV set 404, speakers 406 to 412 and a bus 414. The bus 414 couples the DVD player 402 to the HD TV 404. The bus 414 can be implemented as a single wire, for example, in a standard digital cable. In this example, the DVD player 402 acts as a master device and the HD TV 404, along with four audio channels for the speakers 406 to 412, acts as a slave device.

[00471] Referring now to Figure 52d, shown therein is an example embodiment of an instrumentation system 450 that uses the unified bus communication protocol. The instrumentation system 450 comprises a multimeter 452, a sensor 454 and a bus 456 coupling these two elements. The bus 456 can be implemented as a single wire, for example, in a standard digital cable. In this example, the multimeter 452 acts as a master device and the sensor 454 acts as a slave device.

[00472] Referring now to Figure 52e, shown therein is an example embodiment of an electronic key 500 that can communicate using the unified

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[00482] At 804, the mode of operation is configured. This mode of operation includes selecting various parameters for the frame format that is used for communication over the bus. For example, at this time, the master device 52 can choose between using word mode or bitstream mode.

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- 161 [00483] At 806, the master device 52 can then configure the frame format that is used for the selected mode from one of the word frame format, the bitstream frame format or the unified bitstream frame format. At this time, in at least some embodiments, the master device 52 can also save different data modes of communication in various bank registers so that the master device 52 may seamlessly switch between the different data modes of communication during operation without causing glitches in the data transmission. The different data modes can specify various parameters for the selected frame format such as, but not limited to, a combination of one or more of the following: different sampling rates, different channel selections, different port selections, different allocations of frame channels for the various selected channels of a given port, different subgroups of port channels in the allocation of frame channels, different repetitions of port channels in the allocation of frame channels, and multiplexing of data from different channels into a common frame channel. In some embodiments, the master device 52 may enable a fast start up after a low power mode is completed by enabling a fast settling oscillator to better support UART devices.

[00484] At 808, slave devices that want to communicate over the bus 64 synchronize with the master device 52. This is done by a slave device by monitoring the activity on the bus 64 for the transmission of S word data. In word mode, the bits of the S words are transmitted consecutively on the bus 64. In bitstream mode, the bits of the S word are not transmitted consecutively, but rather are time multiplexed with bits from other frame channels. However, in both cases, in at least one embodiment, the slave device 54 recognizes the S words as well as determines the frame length and frame structure during the synchronization process. While the frame structure is recognized by the slave device 54 as part of the synchronization process, if there are times when the slave device 54 changes immediately from one frame format to another frame format without losing synchronization (i.e. lock) and thereby allowing immediate change of the frame format, a register inside the slave device 54 can be included to indicate what the next frame format will be. This information may be contained in the COMMAND SEPARATION

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[00493] In at least one embodiment, the master device 52 then instructs the slave device where data is to be placed (i.e. which time slots are used) for the programmed ports based on the frame format that has been selected for use with the unified bus communication protocol. In at least one embodiment, a port is defined as to whether it will carry either bitstream or TDM data and different ports are used for different data format purposes.

[00494] In the case of word mode, the smallest distance between two command words can be specified, as well as the time slots in which data is first placed after a command word. In at least one embodiment, this can be specified by the START field. The data width of each data channel is also specified which can be done by using the LENGTH field in at least one embodiment.

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- 166[00495] In word mode, in at least one embodiment, it is possible to finetune the transfer of data, which is beneficial and efficient when multiple sample rates are used simultaneously for the different data channels for one or more ports of one or more slave devices. For example, in at least one embodiment, there can be gaps between the data for data channels in a subframe (see Figures 21 and 23 and the associated description for examples). In at least one embodiment, there can be various groupings of different data channels in a subframe (see Figures 21, 23 and 24 and the associated description for examples). In at least one embodiment, there can be a repetition of groupings of different data channels in a subframe (see Figures 21, 23 and 24 and the associated descriptions for examples). In at least one embodiment, only a single data channel may be repeated in a subframe. In at least one embodiment, these different configurations of data channels in a subframe can be achieved by using the REPEAT, SUBGROUP and SKIP fields. There can also be embodiments in which there can be various combinations of these features including at least two of these features are all of these features.

[00496] In word mode, it is also possible to support asynchronous data transfer efficiently. In at least one embodiment, this can be accomplished by adding two bits preceding data from a data channel in the first frame used for this data transmission. One of the bits may be used to indicate if a transmitting device has new data to transmit that is valid and one of the bits may be used to indicate if a receiving device has received the transmitted new data.

[00497] In word mode, in at least one embodiment, it may also be possible to support data flows that are of a fractional nature, such as when data sampled at 44.1 kHz are transferred over a 48 kHz path, for example. In at least one embodiment, fractional data flows can be supported by using a phase adder in the master device 52 and a bit located in the X command word to indicate data transfer over several frames.

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- 174requires extra silicon area and power consumption and results in reduced audio quality for audio applications.

[00520] There are some conventional bus communication protocols that use a variable frame length for the frame format, such as l2S, McBSP,

- 179match of the constant sync portion that represents the start of a frame, or if neither of these matches represents the start of a frame. In order to reduce this ambiguity, a random component may be used during the initial synchronization process to randomly try different start positions to help reduce the chance that a situation occurs where the synchronization method continuously switches between a false sync pattern and a true sync pattern and has trouble achieving synchronization (i.e. lock). This may occur, for example, if there are one or more channels that have data traffic that matches the constant sync portion all the time.

[00532] In at least one embodiment of the universal synchronization methods described herein, to further reduce the chance of synchronizing to a false synchronization pattern, once synchronization has been achieved or late in the synchronization process (i.e. after several true synchronization patterns have been found), the determined frame length can be used to search for other synchronization patterns. Since the distance between consecutive synchronization patterns is the determined frame length minus the length of the synchronization pattern, synchronization patterns found at less than this distance can be considered to be false synchronization patterns and eliminated.

[00533] In at least one embodiment of the universal synchronization methods described herein, a random component may be used in the search for synchronization patterns in order to improve the chances of synchronization under conditions of static data bus traffic that matches the constant synchronization symbols that are used. The use of a random component is beneficial if synchronization errors occur due to random bus traffic that closely matches the synchronization pattern that is being searched for.

[00534] In at least one embodiment of the synchronization methods described herein, the random component of the universal synchronization method may include reading the parity of the bus traffic for a certain period of time and using the parity information to aid in determining whether the

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- 180currently located synchronization pattern is a valid/true synchronization pattern or a false synchronization pattern. The parity information can be random as long as there is a physical sensor, such as a microphone, a temperature sensor, a pressure sensor, and the like, that is connected to and providing data to the bus 64. In other embodiments, a CRC generator utilizing input from the bus traffic and past history of operation of the CRC generator may be used to generate a random component. For example, in at least one embodiment, an adder with a finite word size that utilizes overflow wrapping (e.g. a simple binary counter) can be used to add the number of ones or zeros from the bus traffic, thereby generating a random component from the bus traffic. In other embodiments, a general function generator, based on the past history of the bus traffic, contents inside the function generator and the use of one or more mathematical operators may be used to generate a random component. The random component obtained from each of these various methods may be used to avoid getting stuck in a situation, where the synchronization method continuously switches between valid and invalid sync positions (i.e. sync patterns) because it is not initially known where the beginning of a frame is at the beginning of the synchronization process. In other embodiments, the bus may be started in a known state, where false sync patterns are not present, but this embodiment will not allow another device to obtain synchronization after the bus has started. Therefore, with this scheme, the bus will need to restart if a new device attempts to connect to the bus. Accordingly, if this solution is chosen, hot plug-in without any audio disturbances is not possible.

[00535] In addition to checking that there is a match for the dynamic sync portions in addition to a match of two constant sync portions, in at least some embodiments it is also possible to check if the distance between two constant sync patterns remains constant. This is true for a valid frame format. Therefore, it is possible to check that the distance between two synchronization patterns with valid dynamic sync portions also have a constant distance (in number of bits between, for example, the start or end of the two synchronization patterns). In order to perform such a check, at least

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- 181 three valid constant sync portions are located in order to be able to calculate two distances that can then be compared.

[00536] In an least one embodiment of the synchronization methods described herein, the random component can be used when the constant sync portion has been located but there are one or more errors, such as the current frame length determined based on the synchronization pattern that was just found is not the same as the previous frame length that was determined based on a previously located synchronization pattern. This extra information can be used to discard invalid sync positions.

[00537] In at least one embodiment of the universal synchronization methods described herein, the portions of the universal synchronization method that search for synchronization patterns in bitstream mode can utilize clock gating in order to skip data from channels in which the bits of the synchronization pattern are assumed not to exist (e.g. ignore every second bit if lock has already been achieved using information from only every second bit). One benefit of using clock gating is that it will allow for a reduction in power consumption thereby making the synchronization method more energy efficient since some frame channels are not processed since they are assumed not to have the bits of the synchronization pattern. Another benefit of using clock gating is that a common search structure can be used to search for the synchronization pattern under both word and bitstream modes of operation because clock gating in essence allows bitstream frame data to be processed in a similar fashion as word data, as will be explained in further detail below.

[00538] In general, the various universal synchronization methods described herein will employ an upper limit in order to reduce the time to synchronization. For example, when assuming the bus 64 is operating in word mode and searching for the synchronization pattern, an upper limit can be placed on the frame length. Accordingly, if the number of bits that are searched to locate the synchronization pattern is larger than the maximum defined frame length and the synchronization pattern has not been found then

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- 182the search may switch to bitstream mode, where the synchronization engine assumes that the sync symbol patterns have been multiplexed with other information and will search for the correct channel position, the position within a channel and the number of channels in order to achieve synchronization.

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- 186deterministic method such that the dynamic sync portions of two consecutive synchronization patterns are different but determinable. In at least one embodiment, the deterministic method may employ a CRC generator or one of the variations described previously.

[00552] In at least one embodiment, there can be several synchronization patterns that are used and act 904 can comprise searching for one of these synchronization patterns by comparing the transmitted data with each of these synchronization patterns.

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- 195then if the two frame lengths are different there is an error. Alternatively, if the two frame lengths are the same then this may be used as verification in some cases. Once the frame length has been found, the spacing between the command words can be found by dividing the frame length by three, e.g. by binary division or by incrementing a counter by three until this counter is equal to the frame length value (the number of increments is then equal to the subframe length).

[00568] In at least one embodiment, the verification comprises using the dynamic portion of the synchronization pattern. For example, the searching acts 904 and 906 and the obtaining act 910 may comprise reading a current dynamic sync portion associated with a constant sync portion for a currently located synchronization pattern and the synchronization rule comprises calculating an expected dynamic sync portion based on a deterministic method and the current dynamic sync portion, locating a next constant sync portion and comparing a dynamic sync portion associated with the next constant sync portion with the expected dynamic sync portion to reduce the chance of false synchronization.

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- 198occurrence of the sync constant portion during every frame after synchronization has been established.

[00574] In at least one embodiment, the synchronization rule may comprise adding a random component in the locating acts 904 and 906 and the obtaining act 910 in order to improve the chances of synchronization under noisy conditions on bus traffic and when bus traffic closely resembles the synchronization patterns.

[00575] For example, in at least one embodiment, the random component comprises reading the parity of the bus traffic for a certain period of time and using the parity information to make a random choice as to whether the currently located synchronization pattern is a true pattern or a false pattern. This way, the synchronization method will not get stuck in cycles, e.g. where every second located constant synchronization pattern is valid and every other second one is invalid, thereby making all CRC checks invalid. In at least one embodiment, the period of time can be one frame of transmitted data.

[00576] As another example, in at least one embodiment, the random component may be used when the synchronization pattern has been located in the wrong position (i.e. not at the start of a frame) thereby resulting in one or more errors during the synchronization process. For example, these errors may be due to the fact that there is a situation which results in transmitted data on the bus 64 that may look like the synchronization pattern that is being searched for but is actually a false synchronization pattern. If the false synchronization patterns are the result of truly random data traffic, they will normally only disturb the synchronization process for a short time and when they disappear, the method 900 will find true synchronization patterns and the slave device 54 will become synchronized to the bus 64. However, when searching for the constant sync portion, there could be a situation which results in constant activity, such as constant temperature data provided by a temperature sensor for example, that matches the constant sync portion. This may occur even though the constant sync portion can be many bits long. In

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- 199this case, these false synchronization patterns can appear in the transmitted data on the bus 64 for a long time which will disturb the synchronization process.

[00577] Referring now to Figures 55a and 55b, shown therein, 5 respectively, are diagrams of a first scenario in which a true synchronization pattern is sent in the transmitted data and a second scenario in which true and false synchronization patterns are sent in the transmitted data. In this example, the transmitted data (other than the control data) are audio data.

However, this example can also be true for other types of data such as instrumentation data (i.e. sensor data). In Figure 55a, the control data comprises an S word, an X word and a Y word which are separated by data portions comprising audio data. The S word comprises the true synchronization pattern. In Figure 55b, the control data comprises the same general components as was shown in Figure 55a. However, there are now three false synchronization patterns (i.e. three false S words) that are sent in the data portions. In alternative cases, the false synchronization patterns can exist closer to the beginning or the end of the data portions, can only be in some of the subframes and/or possibly can be in different locations within the consecutive data portions. The false S words contain data bits that correspond to the true synchronization pattern. However, they are not in the correct location (i.e. correct sync position) at the start of a frame and are therefore false. Accordingly, these false S words may be determined based on their location once the true location is known. Alternatively, these false S words can be determined by checking the dynamic sync portion of these false

S words to determine whether they match the expected dynamic sync portion as described earlier.

[00578] The situation of false synchronization patterns can be dealt with using a random component in the universal synchronization method 900. The random component is obtained by using a random variable. In at least one example embodiment, the random variable can be the parity of the transmitted data over a certain time period. For example, the parity can be

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-200set to 1 if the number of ones since the last synchronization pattern was even, otherwise it is set to 0 or vice-versa. The parity is the total number of bits modulus two, but other similar random quantities can be defined, e.g. total number of bits modulus four (i.e. last two bits when adding). In at least one embodiment an additional CRC generator may be used that is based on all bus traffic since the last frame synchronization pattern. The CRC generator could take as input the output from the CRC generator itself and XOR it with the input from the bus 64 (a special provision should be made to map the register value zero to some other value). Counting the number of Ts or 0’s in the bus traffic is a random process since the quantization process itself is a random process due to thermal noise which is present in any physical measurement (e.g. quantum-electrical electrical noise or quantum-mechanical noise). A random decision is then made based on this computation. In at least one embodiment, the decision may be to either keep the previous synchronization pattern as a true pattern and to keep searching for the next true synchronization pattern or to keep the current synchronization pattern as a true pattern and to keep searching for the next true synchronization pattern. This decision can be made by checking if the calculated parity is equal to 0. Alternatively, this decision can be made by checking if the calculated parity is equal to 1. In each case the probability of a change in the sync position is 1/2. In the general case, the probability of staying in the current position based on a random variable will be p and the chance of changing to the new position will be (1-p). Regardless of whether the previous synchronization pattern or the current synchronization pattern is retained as a true synchronization pattern, with this methodology sooner or later the correct true synchronization pattern will be selected. In at least one embodiment, instead of just retaining the current synchronization pattern as a true synchronization pattern, a random but finite number of synchronization patterns starting from the current synchronization pattern can be discarded before the method 900 considers the next located synchronization pattern to be a true synchronization pattern.

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-201 [00579] The selection of the previously located synchronization pattern as the true synchronization pattern can be denoted as having a probability of p and the selection of the currently located synchronization pattern as the true synchronization pattern can be denoted as having a probability of 1-p based on the selected random variable (i.e. the parity as discussed in one embodiment). The method 900 then continues to search for the next constant sync portion and compare the associated dynamic sync portion with the expected dynamic sync portion. In some cases, where there is a lot of bus traffic that looks like the constant sync symbol, the likelihood that the method remains in the correct sync position between two frame start positions is pN, where N is the number of false sync positions. However, once the correct sync position has been found, the search method will discard the false positions and only look at the correct positions.

[00580] In at least one embodiment, and in an attempt to make the search process fully deterministic, it may be possible to speed up this synchronization search by making a list of the last CRC values associated with a valid sync constant thereby quickly eliminating later sync constant matches that do not have a dynamic sync portion that matches to any position from this list (this may involve a list that is long enough to handle all possible disturbances on the bus 64).

[00581] In at least one embodiment, it may be possible to eliminate many false synchronization patterns, by observing how many time slots (i.e. the sync separation value) that are between the two located constant sync portions. The lower end of the spacing for the next located constant sync portion should be at least the sync separation value (in word mode). If the search method has already encountered a distance between two sync symbols of L, if the distance is shorter than L between two later found sync symbols, at least one of these sync symbols is false (it should be noted that the term sync symbol is similar to the term sync pattern or sync portion).

[00582] In at least one alternative embodiment, once a true synchronization pattern has been found, the method comprises continuing to

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-202search forward until the maximum frame length has been reached or the dynamic sync portion of a located synchronization pattern matches the expected dynamic sync portion. If this latter condition is valid, then the method continues to search for future synchronization patterns using the spacing between this current synchronization pattern and the previous synchronization pattern. This is different from the previous method in that it will continue to maintain a given first sync position until it has been proven that it is a false sync position or that is a good candidate for a valid sync position (since both the constant sync portion and the dynamic sync portion passes a check). This is in contrast to the technique of randomly choosing between two sync positions when in doubt. If it is proven that the given position cannot be a valid sync position, the synchronization method will move on to the next sync position that gives a possible valid sync symbol or it may exceed the maximum frame length. If this synchronization method fails to find the number of synchronization patterns that are used for verification, then the method can begin using the last located synchronization pattern as a true synchronization pattern, but this may involve some memory in order to perform. If the latter condition is true, and the maximum frame length is reached, the synchronization method begins anew and starts searching for the next true synchronization pattern. While this method may seem to offer a faster synchronization, there is the risk that synchronization may not be achieved, because the method may continue to skip over the true sync position due to the structure of the random data (although it might help to skip a prime number of positions forward, e.g. 11 positions). Therefore, in order for this method to work, it may be necessary to either store all sync positions and work with this information or to add some randomness to the method, e.g. skip a random number of sync symbols before starting again to search for a matching constant sync symbol and a matching dynamic sync symbol. This method seems to be most suited for parallel hardware implementation. If this is available, it is possible to implement a number of search engines, thereby making the entire algorithm work very fast and reliably. The first sync engine may look for a matching dynamic sync symbol to the first found sync constant,

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-203the second sync engine may look for a matching dynamic sync symbol from the second sync position, and so on until all N sync engines have been activated. This method will allow up to N-1 false sync positions between two frame start positions without encountering any problems.

[00583] In at least one alternative embodiment, a table can be made of the dynamic sync portions corresponding to all valid constant sync portions that have been found within a maximum length of data. The positions of these located dynamic sync portions are also recorded in the table. Next the positions of the dynamic sync portions in the table which match the expected dynamic sync portions can be recorded in a list of positions. If there is repetition in the separation of consecutive positions in the list of positions, then the distance between these positions will be the actual frame length, and these positions can be used to obtain synchronization. The main problem with this method is the hardware overhead, otherwise it offers robust synchronization.

[00584] In either of the above-noted variations, if synchronization is achieved, then the method 900 performs act 912. If synchronization is not achieved, and the mode of operation is still assumed to be correct, then the method 900 performs the searching acts 904 and 906 again and may reset one or more parameters.

[00585] It should be noted that there can be embodiments which use at least two of the synchronization rules that have been described herein. It should also be noted that there can also be embodiments which use various combinations of the synchronization rules that have been described herein.

Furthermore, it should be noted that there can be embodiments which use at least one of the synchronization rules that have been described herein.

[00586] At 912, synchronization has been achieved by the slave device 54. Depending on the particular implementation of the unified bus communication protocol, the slave device 54 may be allowed to transmit some information back to the master device 52 to signal that it has achieved lock (i.e. synchronization). At that point, the master device 52 may perform

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-204various actions such as, for example, sending various parameter data to the slave device 54 in order to configure the slave device 54 so that it can communicate according to the unified bus communication protocol and have one or more input channels, one or more output channels or one or more input and output channels of at least one port that are enabled. In at least one embodiment, the slave device 54 will not have any port attached to the bus 64 and the bus 64 will merely be used for control purposes such as register READ/WRITE operations or the activation of FUNCTIONS within the slave device 54. In an alternative embodiment, the setup can also be done by the slave device 54 or by a combination of events, for example, involving the master device 52 and the slave device 54. In at least one embodiment, another master device can be involved in setting up all or some of the slave device settings.

[00587] It should be noted that there can be embodiments in which once synchronization has been achieved, the method 900 is continued to be performed to maintain the synchronization. In cases where there is an error and synchronization is lost just for one instance of a synchronization pattern, then the method 900 can involve assuming that the mode of operation and frame format parameters are the same so that the method 900 does not have to undergo the full synchronization process with all of its parameters being reset. For example, since the frame length and frame format has been determined once synchronization has been achieved then when maintaining synchronization other positions in the transmitted data are not examined unless they are in the vicinity of a determined frame length’s distance from the last synchronization pattern. This allows the method 900 to ignore any false synchronization patterns that occur in the data blocks transmitted between the synchronization patterns. Alternatively, if synchronization is lost for an extended period of time, then the method 900 may be restarted with its parameters being fully reset to begin the synchronization process from the very beginning. As an example, if the slave device 54 has received no synchronization patterns for longer than the maximum possible frame length,

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[00594] At 1006, the method 1000 synchronizes with the clock. In other words, the remaining actions of the method 1000 start at a new clock cycle for the bus 64. For example, act 1006 can be configured such that if the clock signal is rising from a low logic value to a high logic value (i.e. a rising clock signal), then the remaining acts of the method 1000 are performed. Alternatively, the method 1000 can be synchronized to a falling clock signal. In yet another embodiment, the device can synchronize to both the rising and falling edges.

[00595] At 1007 the current position within the frame is incremented.

[00596] At 1008, the method 1000 determines whether a portion of the transmitted data on the bus 64 matches the constant sync portion as was described for methods 900 and 950. If there is not a match, then the method 1000 proceeds to 1011. If there is a match, then then the method 1000 proceeds to 1010.

[00597] At 1010, the method 1000 determines whether the counter state is equal to 0. The state is used to count how far the method 1000 is along the synchronization process. For example, if the state value is equal to the maximum state value, then synchronization has been achieved. If the state is currently equal to 0, then this corresponds to a first location of a constant sync portion and the method 1000 proceeds to 1012. If the state is currently not equal to 0, then this corresponds to a subsequent location of a constant sync portion and the method 1000 proceeds to 1014.

[00598] At 1011, the method 1000 determines whether at least two matching sync symbols (i.e. synchronization patterns) have been obtained

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-208and if the current search position is framestart (i.e. a start of a frame). If this is the case, then the method 1000 would expect to find a synchronization pattern at this position and there is an error in which case the method 1000 will go to 1050 to check if there is a missing synchronization pattern;

otherwise the method 1000 will go to 1070 and check for frame overrun before returning to 1006.

[00599] At 1012, the method 1000 sets the state to 1 and calculates the sync dynamic portion that is expected for the next constant sync portion by using a deterministic method and the current sync dynamic portion. One example of the deterministic method involving a CRC counter was described previously. The method 1000 then proceeds to 1070 to check for frame overrun and then back to 1006 to search for the next constant sync portion.

[00600] At 1014, the method 1000 then checks if the constant sync portion has already been found once before or if the current search position is at an expected frame start position. If this condition is true, the method 1000 proceeds to 1016 where the current position is set to the start of a frame. If the comparison at 1014 is false, the current located constant sync portion is ignored and the method 1000 proceeds to 1070 to check for frame overrun and then back to 1006.

[00601] At 1018, the method 1000 then checks whether the calculated dynamic sync portion matches the dynamic sync portion associated with the currently located constant sync portion (in this case the term associated means that the dynamic sync portion that is associated with a constant sync portion is part of the same synchronization pattern or S word). If the comparison at 1018 is true then the method 1000 proceeds to 1020. If the comparison at 1018 is false then the method 1000 proceeds to 1028.

[00602] At 1020, since there is a match between the calculated dynamic sync portion and the located dynamic sync portion, the method 1000 considers the currently located constant sync portion to be valid, updates the frame length and calculates the next dynamic sync portion. The frame length is updated by calculating the distance between the start of the synchronization

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[00615] At 1082, the method 1070 exits and returns to the method that called it.

[00616] Referring now to Figure 59, shown therein is a diagram of an example embodiment of a bitstream mode synchronization method 1100 that can be used with a universal synchronization method to locate and verify synchronization patterns when the unified bus communication protocol is operating under bitstream mode.

[00617] At 1102, an instantiation of the method 1100 is initialized.

Function calls to the method 1100 create an instantiation of the method 1100. At 1104, the parameters, states and counters that are used to search for, locate and verify the synchronization patterns are initialized. For example, the initialization includes defining a maximum number of bitstream frame channels and a maximum frame length. At 1106, the method 1100 synchronizes with the clock as described previously in order for the remaining actions of the method 1100 to start at a new clock cycle for the bus 64.

[00618] At 1108, the method 1100 determines whether a portion of the transmitted data on the bus 64 matches the constant sync portion as was described for the bitstream portion of the methods 900 and 950. This is done

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-213by searching through the currently assumed number of bitstream frame channels, one channel at a time. Alternatively, in a parallel implementation all of these channels can be searched at the same time.

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-218[00637] At 1164, the parameter sweet_spot is set to 0 and the current position L is incremented by 1. The method 1150 then proceeds to 1166.

[00638] At 1166, the method 1150 determines whether there is a match for the constant sync portion in the current transmitted data that is being searched. This act was described for method 900 and 950. If this condition is true, the method 1150 proceeds to 1168. If this condition is false, the method 1150 proceeds to 1169 to check if there is a missing sync symbol.

[00639] At 1168, since a constant sync portion has been located, the method 1150 determines whether the state counter is equal to 0. If this condition is true, then this is the first time a constant sync portion has been located and the method 1150 proceeds to 1170. If this condition is not true, then the method 1150 proceeds to 1172 to check if the located constant sync portion is valid.

[00640] At 1169, the method 1150 determines whether the state is at least 2 and that the current position matches the length of a frame (the length of a frame will have been obtained if the method has found at least two constant sync portions which means having a state value of 2). In this case the method 1150 expects to find a synchronization symbol, but none has been found for the current frame. Therefore, the method 1150 proceeds to 1174, where it calls the missing sync method 1200 (see Figure 61a). If the comparison at 1169 is not true, the method 1150 is not at a position where a synchronization pattern is expected. Therefore, it is not an error and there is no synchronization pattern. The method 1150 therefore goes back to the main entry point 1152 to continue searching for the next constant sync portion.

[00641] At 1170, the method 1150 sets the state counter to 1 (which means that the sync symbol has been located for the first time), resets the current position L to 0 (this indicates the start of a frame) and calculates the next dynamic sync symbol (i.e. the next expected dynamic sync symbol) that should be associated with the next constant sync symbol that is located. The next dynamic sync symbol is calculated based on a read CRC value from the

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-219bus 64 following the sync constant and incremented to the next value using the deterministic method. The method 1150 then proceeds back to 1152 to search for the next synchronization pattern. Accordingly, the reset parameter is not set to true and the method 1150 proceeds to 1157.

[00642] It should be noted that the terms constant sync portion and constant sync symbol are analogous to one another. It should also be noted that the terms dynamic sync portion and dynamic sync symbol are analogous to one another.

[00643] At 1172, the method 1150 determines if it has located only a single sync symbol or if the current position matches the expected frame length. If this condition is not true, the current located constant sync symbol will be ignored and the method 1150 will proceed back to the main loop 1152. If the condition checked at 1172 is true, the method 1150 proceeds to 1173.

[00644] At 1173, the method 1150 sets the current search position (L) to zero. The method 1150 then proceeds to 1176.

[00645] At 1176, the method 1150 determines whether the dynamic sync portion associated with the currently located constant sync portion is equal to the expected dynamic sync portion that was calculated. If the condition is true, the method 1150 proceeds to 1178. If the condition is false, then there has been at least one error and at least one of the previous constant sync portion or the current constant sync portion is invalid. The method 1150 then proceeds to 1186 to use randomness in order to select between the position where the previous constant sync symbol was found and ignore the current constant sync symbol or use the new position where the current constant sync symbol has been found and ignore the previous position (since they don’t match).

[00646] At 1178, the method 1150 sets the value of the current framelength L_old to the current position L and calculates the next dynamic sync symbol based on the value of the current dynamic sync symbol and the deterministic method. The method 1150 then proceeds to 1180.

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[00654] The method 1200 basically determines that if there is an error and synchronization has not been achieved, then the synchronization process has to be restarted from the beginning. Otherwise, if synchronization was achieved before the error occurred, then the method 1200 decreases the state counter by one and will search for the next sync symbol as if nothing happened rather than restart the entire synchronization process from the beginning.

[00655] Since the method 1200 expected a sync symbol, but there was none found, the current position is reset to zero at 1204, i.e. the method 1200 assumes that the frame starts at the current position even though the last located constant sync portion is in error, e.g. due to noise on the bus 64, for example. This will work for any data errors on the bus 64 but not for glitches on the clock signal.

[00656] At 1206, the method 1150 determines whether or not the slave device 54 is in lock with the master device 52. If it is in lock (state = max

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-223state), a single error will be allowed and the state value will be decreased at 1208. In this case the next dynamic sync portion is calculated based on the previous CRC value on the bus 64 and not the current CRC value on the bus 64, which seems to be wrong. Thus, the previous CRC value is updated. If this value does not match the current CRC value on the bus 64, then this updated CRC is updated once more to be compared to the next read CRC value. This scheme allows for a single CRC error while still maintaining synchronization (it is assumed that only the constant sync portion is in error). The method 1150 then proceeds to 1211 and returns to 1152 of the main search method 1150.

[00657] At 1210, there has been more than one error or the slave device 54 is not yet in synchronization with the master device 52. Therefore, the search method is restarted again by resetting certain parameters, since those conditions will not happen for a valid synchronization position. The method

1150 then proceeds to 1211 and returns to 1152 of the main search method

1150.

[00658] Referring now to Figure 62, shown therein is a diagram of an example embodiment of a bitstream mode synchronization method 1250 that can be used with the method 1150.

[00659] At 1252, an instantiation of the method 1250 is initialized.

Function calls to the method 1250 create an instantiation of the method 1250.

[00660] At 1254, the method 1250 determines whether the parameter reset has been set to true (i.e. to 1). If this condition is true, then this means that all of the parameters, counters and variables used to search for a synchronization pattern under the assumption of bitstream mode are reset to their initial values so the method 1250 proceeds to 1256. Otherwise if the condition at 1254 is false, the method 1250 proceeds to 1258.

[00661] At 1256, the parameters, states and counters that are used to search for, locate and verify the synchronization patterns under the assumption of bitstream mode are initialized. For example, the initialization

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-224includes defining the current assumed number of bitstream frame channels (A), a channel counter or index (B) indicating the channel that is currently being searched through, a counter (C) going through all the channels to activate clock gating for the channel that is being searched through and a the current position within a bitstream channel (DL), which is similar to the current position within a frame (L). The maximum allowed number of channels is defined by Amax and may be equal to 16 in one implementation. The method 1250 then proceeds to 1258.

[00662] The A, B and C variables are referenced from a value of 0 so setting the current number of bitstream frame channels to 8 means that A = 7. This is done to save register space. To understand how these variables are used, assume that there are 3 maximum number of bitstream frame channels so Amax = 2. The counters are then set to A=0, B = 0, C = 0 and DL = 1. This means that there is currently assumed to be 1 bitstream frame channel (A=0), the current bitstream frame channel being searched for a synchronization pattern is the first bitstream frame channel (B=0), the counter looking through all channels starts in a first position (C=0) and the starting position in the transmitted data is 0 (DL = 1).

[00663] The method 1250 works by systematically going through all possible structures of the bitstream frame format and trying to obtain synchronization in any of the allowed channels for each assumed frame format. The method 1250 will continuously increment the channel index counter C, which indicates which bitstream channel is currently being transmitted on the bus 64. When C is equal to the number of channels (A) defined for a frame format, it is reset and the general search method 1150 will capture a single bit, i.e. take out a single bit from the multiplexed signals on the bus 64 and assume this belongs to the frame channel containing the synchronization. At the same time, the current bit position (DL) within a channel will be advanced by one. If synchronization is not obtained in this channel, the current channel (B) that is searched for the synchronization pattern is incremented by one. If B is equal to A, the current number of

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-225channels, the search is complete for the current assumed number of channels for the current assumed frame format and A is incremented by one. If A is equal to Amax, the method 1250 has searched through all formats and all channels, otherwise C, DL, B and A will be incremented, in that particular order, to search through another channel for the synchronization pattern.

[00664] At 1258, the method 1250 synchronizes with the clock as described previously in order for the remaining actions of the method 1250 to start at a new clock cycle for the bus 64. The synchronization can either be done at the rising, falling or both clock edges as earlier described.

[00665] At 1260, the parameter re_sync is set to false (i.e. a logic value of 0). This signifies that the search by the main search method 1150 proceeds uninterrupted. When this parameter is set to true, the current search position L and the current frame length L_old are both reset to zero. This happens if no synchronization symbol has been found in the current bitstream channel that is being searched through. The method 1250 then proceeds to 1262.

[00666] At 1262, the method 1250 determines whether the parameter bitstream_mode is set to true (i.e. a logic value of 1). If this condition is true, then the method 1250 proceeds to 1266. If this condition is false, nothing happens and the method 1250 proceeds back to the bitstream entry point 1252. This is done so that all variables are in a well-defined state and this also lowers current consumption. It could be omitted in some embodiments. The check performed at 1262 may also be done earlier in the method 1250 in an alternative embodiment.

[00667] At 1266, the method 1250 determines whether the parameter sync_begin is set to true (i.e. 1). If this condition is true, then this means that the search for the synchronization pattern is starting at the very beginning under bitstream mode. The method 1250 proceeds to 1268 where the counters and parameters are reset to their initial values to assume that there is only one bitstream frame channel in which case the search for the synchronization pattern begins at the first bit in the first bitstream frame

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-226channel. If the condition at 1266 is false, then the search process for the synchronization pattern is not starting at the very beginning and the method 1250 proceeds to 1270.

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-229method 1250. In word mode, the method 1250 still runs, but with lower power consumption, since bitstream mode is false (see the decision at 1262). The bitstream method 1250 and the clock gated word mode method 1150 can be run (i.e. carried out or executed) in parallel.

[00677] Referring now to Figure 64, shown therein is a diagram of an example embodiment of a quick resynchronization method 1350. The quick resynchronization method 1350 can be used when synchronization has already been achieved and a synchronization method is still being used in order to maintain synchronization. For example, the method 1350 can be run or executed in parallel with the methods 1150 and 1250.

[00678] At 1352, an instantiation of the method 1350 is initialized. Function calls to the method 1350 create an instantiation of the method 1350.

[00679] At 1354, the method 1350 determines whether the reset parameter has been set to true. If this condition is true, the method 1350 proceeds to 1356 at which point the parameter allow_changes is set to 1 (i.e. true). The method 1350 then proceeds to 1358. However, if the condition at 1354 is not true then the method 1350 proceeds to 1358.

[00680] At 1358, the method 1350 synchronizes with the clock as described previously in order for the remaining actions of the method 1350 to start at a new clock cycle for the bus 64.

[00681] At 1360, the method 1350 determines whether the value of the state counter is equal to the max state value or the max state value -1 (which can be set to 6 & 7 for example) and whether the search for the synchronization patterns is operating under bitstream mode. This compares the current state value against two different state values to allow for a single error in synchronization. If this is true, then the method 1350 proceeds to 1362 where the value of the parameter allow_changes is set to 0 (i.e. false) which means that synchronization has been achieved and the current state should be maintained even if some errors occur. This means that even if an error occurs in bitstream mode, the synchronization method will not

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-230immediately go out of lock. This condition is covered by the allow_changes parameter and act accordingly (in other words, the synchronization method is not allowed to immediately change back from assuming it is bitstream mode and back to assuming it is word mode based on a single error). The method

1350 then proceeds to 1352 to continue to monitor for any changes in the state value. However, if the condition at 1360 is false then the method 1350 proceeds to 1364.

[00682] At 1364, the method 1350 determines whether the search has exceeded the current frame length or whether the search for the synchronization patterns is operating under word mode. Therefore, the condition at 1364 can be used to find situations in which more than one error has occurred or the synchronization search method is operating under word mode. If the condition at 1364 is false, then the method 1350 proceeds to 1352. If the condition at 1364 is true, then the method 1350 proceeds to 1366 at which point the allow_changes parameter is set to 1 so the current value of B and A may be changed (after act 1304 of method 1300) if no synchronization symbol is found.

[00683] Referring now to Figure 65, shown therein is a diagram of an example embodiment of a clock gating method 1400 that can be used in parallel with the methods 1150, 1250 and 1350 described herein. The clock gating or clock enable is used to control the main method 1150, so that it captures bus activity all the time in word mode and so that it only captures bus activity during the times when the current frame channel that is being monitored is active in bitstream mode, as explained previously.

[00684] At 1402, an instantiation of the method 1400 is initialized.

Function calls to the method 1400 create an instantiation of the method 1400.

[00685] At 1404, the method 1400 determines whether the reset parameter has been set to true. The reset parameter is either set by a poweron reset signal or by an external event such as a controlled reset event initiated by a bus controller. If this condition is true, then the method 1400 proceeds to 1406 at which point the clock_gate parameter is set to 1 which

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-231 means that the default condition is that the clock should be enabled in the search method that is using the method 1400. The method 1400 then proceeds to 1408. If the condition at 1404 is false, then the method 1400 proceeds directly to 1408.

[00686] At 1408, the method 1400 synchronizes with the clock as described previously in order for the remaining actions of the method 1400 to start at a new clock cycle for the bus 64.

[00687] At 1410, the method 1400 determines whether the current position within a multiplexed bitstream channel (C) is equal to the current channel that is being monitored or if the method is operating in word mode. In both cases, the clock should be enabled for the method 1150. If the condition at 1410 is false, the method 1400 proceeds to 1414 at which point the parameter clock_gate is set to 0, which means that the clock is disabled and the method 1150 is idle during the following clock period and ignores current data on the bus. At the completion of acts 1412 or 1414, the method 1400 proceeds back to 1402 to check if the mode of operation (i.e. bitstream mode or word mode) or the values of C and B have changed. This is done in every clock cycle since C and B can change value in every clock cycle.

[00688] It is also possible to use at least one embodiment of the unified bus communication protocol described herein over a wireless link. In this case, the wireless link or wireless interface can be considered to be the bus. It is especially suited for configurations where the delay is low (e.g. for high speed short distance links such as RF-ID like links or wireless docking stations) or where the communication speed is not too high and is limited by a longer propagation distance. For example, at least one embodiment of the unified bus communication protocol can be used in a low power magnetic link system, where a master device transmits a modulated carrier signal and utilizes the same time slot system as described for a single wire bus embodiment. The slave device will rectify the RF signal and use the envelope of this rectified signal as the “bus signal” in order to derive the clock and data signals, as shown in Figure 66. In order for the slave device to communicate

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-232back to the master device, it may use a separate transmitter for long distance links, but for a simple magnetic link it may simply load the transmitted carrier signal. Similar to the single wire bus case, the loading of the transmitted carrier signal can be used as a mechanism for communicating back to the master device with the same advantages, namely the receiver can retrieve the clock and data directly from the transmitted carrier signal. Furthermore, the protocol and hardware are relatively simple to implement. The transmitting and loading of the carrier signal can be accomplished by the use of two small coils, e.g. implemented as a number of circular turns on a part of a PCB in the master device and the slave device. The spacing and number of turns of these PCB coils may be improved to utilize the inherent parasitic capacitance between the windings for tuning of these coils to a specific frequency of operation. In an alternative embodiment, two coupled transmission lines may be used for high frequency of operation and high speed data transfers. The transmitted carrier signal will typically have a frequency that is much higher than the bandwidth of the data, e.g. a 433 MHz, or 2.4 GHz carrier signal could be used as carrier and a frequency of 3.072 MHz or 19.20 MHz could be used as the transfer rate of high quality stereo audio. In some embodiments, a much higher carrier frequency, such as 24 or 60 GHz may be used, especially if broad band data such as high definition video, for example, may be transferred. These signals could be transmitted through closely coupled transmission lines. Furthermore, if the power requirements of the receiver is low, it is possible to power this device by the power from the transmitted carrier signal (that was sent from the master device) enabling similar functions as compared to an RF-ID device, but with the possibility of a higher bandwidth and more functionality. This enables the transfer of identity information or the transfer of larger amounts of information, e.g. files, audio, pictures or movies. In some embodiments, more than one data bit may be transferred after a given clock transition and before the next clock transition for enabling a higher bandwidth of the data. By encrypting the data, a secure handling of data can be obtained.

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-233[00689] It should also be noted that at least some of the elements used to perform at least one of the methods of the unified bus communication protocol described herein that are implemented via software may be written in a high-level procedural language such as object oriented programming.

Accordingly, the program code may be written in C, C++ or any other suitable programming language and may comprise modules or classes, as is known to those skilled in object oriented programming. Alternatively, or in addition thereto, at least some of these elements implemented via software may be written in assembly language, machine language or firmware as needed. In either case, the program code can be stored on a storage media or on a computer readable medium that is readable by a general or special purpose programmable computing device having a processor, an operating system and the associated hardware and software that is necessary to implement the functionality of at least one of the methods of the unified bus communication protocol described herein. The program code, when read by a processor, configures the processor to operate in a new, specific and predefined manner in order to perform at least one of the methods described herein for the unified bus communication protocol.

[00690] The next section of the description discusses other example embodiments of the unified bus communication protocol in which modifications have been made to achieve one or more benefits.

[00691] Referring now to Figure 67, shown therein is a diagram of another example embodiment of the fields and bit allocations that can be used for a synchronization word otherwise known as an S word. For this S word, the IRQS bit (S15) is the first bit (or first time slot), the parity bit (S14) is now the 2nd bit (or second time slot) and the ACK bit (SO) is now the last bit (or last time slot in which the S word is transmitted on the bus 64). The remainder of this S word format is similar to the one shown in Figure 7 and will not be discussed.

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-234[00692] In an example embodiment, the default value of the S word at power-up of the bus 64 can be “0010.1100.0111.1110” = 0x2C7E. This is equivalent to starting the pseudo random sequence with a value of “1111”.

[00693] It should be noted that with this different configuration for the S 5 word, many of the example frame formats described herein will change such as those shown in Figures 40 to 44 due to the different ordering of bits in the

S word of Figure 67.

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-246[00735] Another method that may be able to achieve low power consumption, which can be used in at least one embodiment of the unified bus communication protocols described herein, is to operate the system in two modes. In a first mode, all of the features of the system are available and in a second mode only a few of the features are available and it is no longer possible to program devices. The clock frequency does not necessarily have to be changed between these different modes. The second mode has a lower power consumption compared to the first mode.

[00736] As an example, currently some bandwidth is allocated to control 10 and synchronization and this is allocated in any scenario. It costs power to clock out this information to the bus 64. However, lower power consumption may be obtained by setting the bus 64 in a specific mode, where this bandwidth is no longer used. However, this means that control is no longer possible and the slave devices and the master device may use sequences in order to regain control. It is possible to change from a scenario that includes control data to a scenario where there is no control data. The problem lies in assuring synchronization after control data has been removed and to assure a slave device or the master device can initiate a control sequence, if needed. If control is removed, devices could get out of sync. For example, if an error occurs due to a glitch on the clock line, these devices may not be able to get back in sync since the synchronization information has been removed. The simplest solution to this problem is to limit the number of devices on the bus 64 to two devices and let one device drive the bus 64 when the clock signal is high, and let the other device drive the bus 64 when the clock signal is low.

This fully solves the problem of synchronization even in the event of errors on the bus 64.

[00737] Still continuing with the example of not sending control data, a transmitting slave device (e.g. a microphone) may wake up the master device by sending out a certain sequence to the master device 52, that is predetermined as part of the unified communication protocol. This sequence is masked out from audio data by having the master device 52 filter this

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[00762] Referring now to Figure 77b, shown therein is a table showing an example embodiment of timing parameter values that may be used for devices that utilize overclocked data slots. Overclocking by a factor of 4x may be done using 4 data slots per half clock period (instead of 2), and

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-257overclocking by a factor of 6x may be done by transmitting 6 data bits for every half clock period. It should be noted (see * in Figure 77b) that if it is only possible to have a time to disable output (TDz) that is greater than 5ns and a time to enable output (TZD) that is less than 9ns, then the output current should be less than 1 mA during the violation period. Any overlap of data will lead to increased power consumption which is not desirable. Also, the VCO range of the PLL may be higher by an integer factor if required by internal device timing events (see + in Figure 77b).

[00763] The actual timing of some overclocking examples will now be 10 discussed. For 2X overclocking using an 8.2 MHz clock, the setup time is given by equation 1.

Tsetup - Tclkmin/2 - Tzd-Tclkskew(write)-Tclkskew(read)- Tpcb-Tsljitter -Tmsjitter-Tdly (1) = (70/2-16-2-2-2-4-1-4) ns = 4ns, margin 2ns The hold time is given by equation 2.

Thold = Tzd-Tclkskew+Tpcb-Tsljitter-Tmsjitter+Tdly (2) = (9-2-4-1+2) ns = 4ns, margin 3ns

The bus conflict time is given by equation 3.

TbUS CONFLICT = TZD + TsLJITTER(MIN)- TdZ(MAX)- TsLJITTER(MAX) (3) = (9-2-5-2) ns = 0ns ( > 0)

[00764] For 4X overclocking using an 8.2 MHz clock, the setup time is given by equation 4.

Tsetup = Tqlkmin/4 - TZd—Tclkskew(write)-Tclkskew<read)- Tpcb-Tsljitter -Tmsjitter-Tdly (4) = (140/4-16-2-2-2-4-1-4) ns = 4ns, margin 2ns The hold time is given by equation 5.

Thold = TZd-Tclkskew+Tpcb-Tsljitter-Tmsjitter+Tdly (5) = (9-2-4-1+2) ns = 4ns, margin 3ns

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-258[00765] For 6X overclocking using an 8.2 MHz clock, the setup time is given by equation 6.

Tsetup = Tclkmin/6 - Tzd-Tclkskew(write)-Tclkskew(read)- Tpcb-Tsljitter -Tmsjitter-Tdly (θ) = (204/6-16-2-2-2-4-1-4) ns = 4ns, margin 2ns.

PCT/CA2013/000198

-261 device 52 has already set the ENABLE MODE CHANGES field to one, the BANK field will change during the next PING operation. In this embodiment, this will continue as long as the REQUEST BANK CHANGE field (during a PING operation) and the ENABLE MODE CHANGES field are both set to one.

The master device 52 may allow for more bandwidth by configuring the second bank so that it allows more bandwidth than the original bank selection. In other embodiments, a device may request for less bandwidth in order to save power consumption.

[00777] Another mode of operation is the DEVICE ACTIVATED WAKE

UP FROM BUS SLEEP mode in which any device can wake up the bus 64 by initiating an interrupt by changing the level of the DATA line after the master device 52 has turned off or disabled the clock to the bus 64. In this case, when the bus 64 is disabled, it may be kept in a tri-state mode but driven by a bus holder with a weak drive so that at least one of the slave devices can initiate the bus wake-up. When the slave device 54 initiates the device wakeup, the interrupt will be sent to the master device 52 which will then begin to activate the clock for the bus 64 again. In this case, the bus 64 acts as an input to the master device 52. In addition, in this case, all of the devices attached to the bus 64 will wake up unless they have been programmed to be in low power mode by other means. Since it is unknown, whether the clock of the master device 52 has been powered down or merely disabled, it may not be possible to achieve a low latency for this particular operation. In particular, if the master device 52 has been powered down, it may take several thousands of clock periods before the main oscillator of the master device 52 is running at normal level again, depending on the Q-factor of the crystal that is used in the oscillator.

[00778] Another mode of operation is the MASTER INITIATED DEVICE

WAKE UP FROM SLEEP mode. For very low power consumption, most if not all of the devices may have their ports disabled and the bus 64 may be stopped. However, it is usually convenient to be able to selectively reduce the power consumption for a number of devices attached to the bus 64 to a bare

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-262minimum while still being able to communicate with the rest of the devices that are attached to the bus 64. To achieve this, SLEEP mode, which is initiated by the FUNCTION SET POWER (‘0001’ and Ό010’, partial shutdown), may be used to set a slave device in a special state where it will only monitor a frame once in a while and discard all of the other traffic on the bus 64 (see Figure 79). The number of frames that will be ignored may be either 15 or 255 frames after which one frame will be monitored. These numbers has been chosen because it is easy to detect 16 or 256 clock cycles that have happened and because they are both divisible by 15. Thus, the waiting period may be any number of M=N*L frames, where N is a positive integer and L is selected based on the different number of synchronization codes that are used, where L is 15 in this example embodiment. In this technique, the pseudorandom counter inside the device that is sleeping will still match the next frame, even though a large number of frames have been skipped. For example, see Figure 79 which shows a slave device that ignores 15*N frames in order to reduce power consumption while still staying in sync with the master device. Correctly implemented, this mode may result in an internal power consumption of less than 1 uA at a bus clock speed of 1 MHz, while the external power consumption (due to capacitive loading) may be an order of magnitude larger. To further lower the power consumption, the bus clock frequency may be set to be less than or equal to 100 kHz. In this mode of operation, the master device 52 may actively use the PING operation as a way to communicate back to the device that is sleeping. By writing to the DEVICE STATUS field (the default value may be zero), the master device 52 can set the most significant bit equal to a one (i.e. the high logic value). If the most significant bit is equal to one, the device should wake up again, while if it is zero, the device should maintain the lower power mode in this example embodiment. Since the device is asleep and only checking the data on the bus 64 every N*15 frames, then the master device 52 may have to send the device wake up command repeatedly for N*15 frames until the device actually wakes up.

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-263[00779] Another mode of operation is the DEVICE INITIATED WAKEUP FROM SLEEP mode. This mode may be used for devices that require a low latency for data transfers after power down. An example of a typical scenario is a UART device that has been waiting for data and suddenly its internal buffer is quickly being filled up by data. Therefore, the UART device may have a lot of data to send but the master device 52 may have set the bus 64 to be inactive to reduce power consumption. Since crystal oscillators have a very long startup time approximately proportional to Q/fo, where Q is the quality factor of the crystal and f0 is the operating frequency (for example about 1 ms for a 10 MHz XTAL crystal and 1,000 ms for a 32.768 kHz crystal), it is may not always be possible to achieve low latency by utilizing a crystal oscillator. Therefore, a device that requires a low latency may instead use an internal relaxation (RC) oscillator with a low and known startup time (see Figure 80b). The master device 52 may program the device for UART mode by setting the FUNCTION SET POWER. This allows a UART to dynamically control the bus 64 depending on the bandwidth that is used and to send data to the master device 52. The master device 52 may then take over when its crystal oscillator has stabilized. In alternative embodiments, an LC oscillator or a ring oscillator may be used instead of an RC oscillator.

These different oscillators can restart in one or a few clock periods, which is advantageous, but they may result in more jitter than the clock signal of the master device 52.

- 268 5*0.5+1=3.5. There are a total of 5 bits that are transmitted. Therefore, the total power consumption per bit is 0.7 transitions per bit (i.e. 3.5/5). Accordingly, this new method of data bit inversion to convey clock and data information results in a greater bandwidth and lower power consumption as compared to the examples of Figures 81a and 81b. In addition, with this technique, it should be noted that all data slots can still be driven individually.

[00792] The schemes in Figures 81b and 81c are suited for bus systems that use high bandwidth and have low power consumption and also use a single wire or medium to transmit information. In other embodiments, the transmission medium could be optical or wireless. It should be noted that a PLL will typically be used in the receiver of a device in order to extract the clock information from the stream of data. Furthermore, a PLL that utilizes a single clock edge (e.g. low-to-high or high-to-low) transition, such as type 111 or type IV phase detectors, may utilize a small delay line together with an XOR gate in order to find the transition for every group of data. In this application, the delay could conveniently be approximately equal to one data slot and the direct and the delayed signal may be feed to an XOR gate and the output from the XOR gate may be provided to the phase detector.

Contents803

41 members in 9 offices

This recordMember, by publication datePriority claim

Priority claims7

Priority claims
Document	Office	Kind	Date
61654386	United States of America	–	2012-06-01
201261654386	United States of America	P	2012-06-01
61714156	United States of America	–	2012-10-15
201261714156	United States of America	P	2012-10-15
13784457	United States of America	–	2013-03-04
201313784457	United States of America	A	2013-03-04
2013000198	Canada	W	2013-03-05

Members41

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Document	Office	Kind
CA2874891A1	Canada	A1	2013-12-05
CA2874899A1	Canada	A1	2013-12-05
US2013322461A1	United States of America	A1	2013-12-05
US2013322462A1	United States of America	A1	2013-12-05
WO2013177664A1	World Intellectual Property Organization (WIPO)	A1	2013-12-05
WO2013177665A1	World Intellectual Property Organization (WIPO)	A1	2013-12-05
US2014247834A1	United States of America	A1	2014-09-04
EP2775654A1	European Patent Office (EPO)	A1	2014-09-10
WO2013177665A8	World Intellectual Property Organization (WIPO)	A8	2014-11-27
AU2013270396A1	Australia	A1	2014-12-18
AU2013270397A1	Australia	A1	2014-12-18
KR20150016618A	Republic of Korea	A	2015-02-12
KR20150023558A	Republic of Korea	A	2015-03-05
CN104509022A	China	A	2015-04-08
EP2856689A1	European Patent Office (EPO)	A1	2015-04-08
EP2856690A1	European Patent Office (EPO)	A1	2015-04-08
CN104541473A	China	A	2015-04-22
JP2015523005A	Japan	A	2015-08-06
JP2015525507A	Japan	A	2015-09-03
HK1203712A1	Hong Kong, China	A1	2015-10-30
AU2013270397B2	Australia	B2	2015-11-12
HK1206135A1	Hong Kong, China	A1	2015-12-31
AU2013270396B2	Australia	B2	2016-01-28
US9252900B2	United States of America	B2	2016-02-02
EP2856690A4	European Patent Office (EPO)	A4	2016-02-17
EP2856689A4	European Patent Office (EPO)	A4	2016-03-09
US2016147686A1	United States of America	A1	2016-05-26
US9461812B2	United States of America	B2	2016-10-04
JP6013596B2	Japan	B2	2016-10-25
US9479275B2	United States of America	B2	2016-10-25
KR101702203B1	Republic of Korea	B1	2017-02-03
CA2874891CThis record	Canada	C	2017-03-28
EP2775654B1	European Patent Office (EPO)	B1	2017-05-03
KR101733273B1	Republic of Korea	B1	2017-05-24
US9672177B2	United States of America	B2	2017-06-06
CA2874899C	Canada	C	2017-07-11
CN104541473B	China	B	2017-09-12
CN104509022B	China	B	2017-12-08
JP6362277B2	Japan	B2	2018-07-25
EP2856689B1	European Patent Office (EPO)	B1	2019-02-06
EP2856690B1	European Patent Office (EPO)	B1	2020-12-02

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