Apparatus, system, and method for creating one or more slow speed communications channels utilizing a real-time communication channel

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PPH

APPARATUS, SYSTEM, AND METHOD FOR CREATING ONE OR MORE SLOW SPEED COMMUNICATIONS CHANNELS UTILIZING A REAL-TIME COMMUNICATION CHANNEL

FIELD OF THE INVENTION

[001] The present invention relates generally to apparatus, systems, and methods for maximizing the use of communications resources within a power protection device, and more particularly to the creation of one or more virtual communications channels from a small amount of data within a real time data stream.

DESCRIPTION OF THE PRIOR ART

[002] In U.S. Pat. No. 5,793,750, a communication system between two microprocessor-based protective relays for an electric power system is disclosed. Each of the two relays in that system has both transmit and receive modules, for directly transmitting indication status bits indicative of the result of selected protective functions of one relay from that one relay to the other, and vice versa.

[003] The output status indication bits are sometimes used to identify the existence and location of a fault on the power line portion served by the two relays. One or both of the relays might initiate a circuit breaker trip action on the basis of the exchange of such information. The output status indication bits may be the result of processing functions in one of the relays involving the voltages and/or currents on the power line monitored by that relay. The output status indication bits may be used for various control, status, indication and protection functions. Examples of protection functions include permissive overreaching transfer trip (POTT) actions, permissive under-reaching transfer trip (PUTT) actions, directional comparison unblocking (DCUB) and direct transfer trip (DTT) actions. Other relay-to-relay operations are possible using particular output status indication bits.

[004] The advantage of the communication system described in the '750 patent is that it is fast and secure. Protective relays typically accomplish their monitoring functions several times each power system cycle. The communication system described in the ‘750 patent provides the results of these monitoring functions of one relay, to the other relay. The information is transmitted directly over a communications link from an originating relay which may or may not trip its associated circuit breaker based on its operational results, to another relay. The

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WO 2013/119315 PCT/US2012/068958 receiving relay then uses the transmitted information, in the form of digital bits, to perform its own on-going calculations, producing various protection actions such as tripping and closing a circuit breaker when appropriate. The communication between the two relays may be bidirectional, allowing the two relays to exchange information concerning the results of their own calculations both quickly and securely,.

[005] Communication systems in power protection devices often rely on lowbandwidth connections, such as 56 kbps or 64 kbps serial connections. However, these connections are often used to communicate real time data, such as, for io example, direct transfer tripping, i.e., tripping a local circuit breaker after receiving a command from a remote protection device, permission-to-trip communications a permissive direction comparison protection scheme, and blocking of tripping in a blocking directional comparison scheme. As these communications are time-critical, such schemes generally demand the entire bandwidth of a low-bandwidth is connection so that the data can be communicated as needed, and with a sufficient guarantee of integrity.

[006] Another communication application utilized by power protection devices is known as “Line Current Differential,” or 87L function. An 87L function communicates local currents as samples or phasors, restraining terms derived from local currents,

0 on/off bits associated with various functions such as, for example, indication of time synchronization to an external device, detection of external faults, test in progress, charging current compensation in progress, and other quantities. In addition, user configurable bits and timing information, such as, for example, time stamps, sequence numbers, and message hold up time, may be communicated as well to

5 facilitate synchronization of data between two devices utilizing the communications channel. As an 87L application is time critical, it also often utilizes the entire communications bandwidth.

[007] While the above functions are critical to the operation of power protection devices, it would be beneficial to also support and utilize other communications between the said devices without the installation of a separate physical communications channel.

SUMMARY OF THE INVENTION

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[008] The disclosed invention achieves its objectives through the use of an intelligent electronic device providing a real-time communications system as well as one or more virtual communications channels.

[009] In one embodiment of the invention, an intelligent electronic device includes a 5 processor and a transmit module coupled to a slow-speed serial communications link. The processor causes the transmit module to transmit a real-time data channel consuming nearly all of the bandwidth available on the communications link. However, the processor further causes the transmit module to inject a background session into one or more unused bits of the real-time data channel, thereby creating io one or more virtual communications channels.

[0010] Further refinements of the disclosed invention describe different uses of the communications channel. For example, a multi-ended fault location service can be realized by sharing voltage data and/or calculated system impedances. Further, fault records can be transmitted between the devices without interrupting normal is operation of the intelligent electronic device. Similarly, device diagnostics data can be transmitted as well.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Although the characteristic features of this invention will be particularly pointed out in the claims, the invention itself, and the manner in which it can be

0 made and used, can be better understood by referring to the following description taken in connection with the accompanying drawings forming a part hereof, wherein like reference numerals refer to like parts throughout the several views and in which:

[0012] FIG. 1 is a simplified single line schematic diagram of a typical wide area power system.

5 [0013] FIG. 2 is a simplified block diagram of a relay-to-relay direct communication system within the power system of FIG. 1 constructed in accordance with an embodiment of the invention.

[0014] FIG. 3 is an exemplary-received frame of the relay-to-relay direct communication system of FIG. 2.

30[0015] FIG. 4 is a simplified functional block diagram of a system constructed in accordance with an embodiment of the invention wherein a primary power protection device controls the functioning of a backup power protection device.

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[0016] FIG. 5 is a simplified block diagram of a relay-to-relay direct communication system for use in the power system of FIG. 1, constructed in accordance with an embodiment of the invention.

[0017] FIG. 6 is an exemplary-received frame of the relay-to-relay direct 5 communication system of FIG. 4.

[0018] FIG. 7 is a simplified block diagram of a relay-to-relay direct communication system within the power system of FIG. 1 constructed in accordance with an alternate embodiment of the invention.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS io[0019] As indicated above, the present invention is based on and is an improvement of the communication system of U.S. Pat. No. 5,793,750, which includes a direct communication link between two protective relays serving an electric power apparatus, the system supporting a communication arrangement or protocol involving eight data channels for exchange of output status indication bits between the two relays both quickly and securely. The channel data bits TMB1-TMB8 identify eight transmit bits, on eight data channels.

[0020] Those bits, when received by the other relay, are identified as received channel data bits RMB1-RMB8, wherein RMB1-RMB8 are the mirror or replica of the transmit channel data bits. The eight data channels can accommodate at least

0 eight output status indication bits. As indicated above, however, in many two-relay arrangements, only two or perhaps three channels are necessary to communicate the output status indication bits. Utilizing the present invention, the otherwise vacant channel space can now be used by selected additional data (discussed below) and an associated synchronization channel to synchronize the additional data.

25[0021] The additional data can be digitized analog quantities, such as metering data, or can be virtual terminal data. In a virtual terminal implementation, a human user or another application utilizes the direct communication link to communicate with the other relay. For example, the human user could utilize the direct communications link to control or query the other relay. An application such as, for example, an integration protocol like as DNP3, could also utilize the communications link in the virtual terminal implementation.

[0022] FIG. 1 is a simplified single line schematic diagram of a typical wide area power system 10. As illustrated in FIG. 1, the power system 10 includes, among other things, two generators 12 each configured to generate three-phase sinusoidal

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WO 2013/119315 PCT/US2012/068958 waveforms, for example, three-phase 12 kV sinusoidal waveforms, two step-up power transformers 14 configured to increase the 12 kV sinusoidal waveforms to a higher voltage, such as 138 kV, and a number of circuit breakers 18. The step-up power transformers 14 provide the higher voltage sinusoidal waveforms to a number of long distance transmission lines such as the transmission lines 20. In one embodiment, a first substation 16 may be defined to include the generators 12, the step-up transformers 14 and the circuit breakers 18, all interconnected via a first bus 19. At the end of the long distance transmission lines 20, a second substation 22 may include step-down power transformers 24 to transform the higher voltage io sinusoidal waveforms to lower voltage sinusoidal waveforms (e.g., 15 kV) suitable for distribution via a distribution line to various end users 26 and loads 30.

[0023] As previously mentioned, the power system 10 includes protective devices and procedures to protect the power system elements from faults or other abnormal conditions The protective devices and procedures utilize a variety of protective logic schemes to determine whether a fault or other problem exists in the power system. For example, some types of protective relays utilize a current differential comparison to determine whether a fault exists in the protection zone. Other types of protective relays compare the magnitudes of calculated phasors, representative of the power system sinusoidal waveforms, to determine whether a fault exists in the protection

0 zone. Frequency sensing techniques and harmonic content detection is also incorporated in protective relays to detect fault conditions. Similarly, thermal model schemes are utilized by protective relays to determine whether a thermal problem exists in the protection zone.

[0024] Referring again to FIG. 1, also included are a first and a second protective

5 relay 100 and 102 adapted to provide for example, overcurrent protection for the transmission line 21. As described below, the first and second protective relays 100, 102 are also adapted to communicate via a communication link 34 that can be configured using one of a number of suitable media. Additional protective relays such as a protective relay 104, adapted to communicate with the first protective relay

100 and/or the second protective relay 102, may also be included in the power system 10.

[0025] FIG. 2 is a simplified block diagram of a relay-to-relay direct communication system 40 incorporated in the power system 10. Although illustrated using the first and second protective relays 100, 102, it should be understood that the

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WO 2013/119315 PCT/US2012/068958 communication system 40 can include additional protective relays operatively coupled to the first and/or second relay 100, 102 and adapted to operate as described below. Further, although illustrated using the first and second protective relays 100, 102, it should be understood that the apparatus and method described herein is applicable to communication between any intelligent electronic device (IED) of the power system 10.

[0026] For ease of discussion, the first protective relay 100 is shown as the transmitting relay and includes, inter alia, a transmit module 41, having a microcontroller 42 operatively coupled to a receive and transmit interface means; in io this example, a universal asynchronous receiver/transmitter (UART) 43. The (transmitting) UART 43 is configured to convert bytes of channel data bits (corresponding to the channel data) resulting from operation of the first protective relay 100 into a single serial message stream for outbound transmission via the communication link 34 to the second protective relay 102, and to convert an inbound serial message stream (from the second protective relay 102) into bytes of channel data suitable for use by the first protective relay 100.

[0027] Similarly, the second protective relay 102 is shown as the receiving relay and includes, inter alia, a receive module 44 having a second microcontroller 45 operatively coupled to another UART 46, operational and configured as described

0 above. Although not separately illustrated, each of the first and second protective relays 100, 102 include both transmit and receive capability to enable communication. While illustrated as transmit and receive modules 41, 44, in a simplified functional block diagram format, the relay-to-relay direct communication system and method described herein may be implemented by means of a

5 microprocessor or field programmable gate array (FPGA) executing a computer program, protection algorithm or relay logic scheme. Further, although illustrated as a UART 43 operatively coupled to the first microcontroller 42, and a UART 46 operatively coupled to the second microcontroller 45, one of any suitable transmit and receive interface means may be utilized to convert bytes of channel data bits into a serial message stream for transmission via the communication link 34.

[0028] The transmit module 41 and the receive module 44 are operatively connected via the communication link 34. As noted above, the communication link 34 may be implemented as an RF link, a microwave link, an audio link, a fiber optic link, or another other type of suitable media adapted to carry serial data. As illustrated, in

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WO 2013/119315 PCT/US2012/068958 addition to output status indication bits, each of the transmit and receive modules 41, 44 is capable of transmitting/receiving other types of channel data in the form of serial messages. For example, the channel data may include digitized analog values, derived from analog quantities, that require more than a single bit such as metering information, breaker failure system security enhancement information, reclose enable information, instrument transformer checking and multi-terminal fault location information, to name a few.

[0029] Referring to the transmit module 41, an eight data channel arrangement is configured such that two data channels, a data channel 47 and a data channel 48, io correspond to the conventional output status indication bits 57 transmitted as channel data bit TMB1 and TMB2, respectively, from the transmit module 41 of the first protective relay 100 to the receive module 44 of the second protective relay 102. Three data channels, a data channel 49, a data channel 50 and a data channel 51, are dedicated to digitized analog values 59, 60 and 61 transmitted as channel data bits TMB3, TMB4 and TMB5, respectively, from the transmit module 41 of the first protective relay 100 to the receive module 44 of the second protective relay 102. Each of the digitized analog values 59, 60, 61 are formed by, for example, converting a 32-bit floating point number representing an analog quantity (e.g., system impedances, currents, voltages) into an 18-bit floating point number. The 18-bit

0 floating point number is then serialized such that one bit from each of the digitized analog values 59, 60, 61 is included as channel data bits TMB3, TMB4 and TMB5, respectively, in sequential transmitted messages until all of the bits associated with the digitized analog values 59, 60, 61 are transmitted. For example, if each of the digitized analog values 59, 60, 61 is expressed in 18 bits, eighteen sequential serial

5 messages are transmitted where the first serial message includes the first bit of the digitized analog value 59 transmitted as channel data bit TMB3, the first bit of the digitized analog value 60 transmitted as channel data bit TMB4, and the first bit of the digitized analog value 61 transmitted as channel data bit TMB5. Similarly, the second serial message includes the second bit of the digitized analog value 59 transmitted as channel data bit TMB3, the second bit of the digitized analog value 60 transmitted as channel data bit TMB4, and the second bit of the digitized analog value 61 transmitted as channel data bit TMB5, and so on.

[0030] It should be noted that while compromising some precision, the conversion scheme that converts a 32-bit floating point number (representing the analog

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WO 2013/119315 PCT/US2012/068958 quantity) into a corresponding 18-bit floating point number, enables quicker transmission to the second protective relay 102. It should also be noted that other conversion schemes may be utilized depending on the analog quantity measured, the precision required, and the speed of transmission desired.

[0031] Two additional data channels, a data channel 52 and a data channel 53 facilitate virtual terminal data transmitted as channel data bits TMB6 and TMB7, respectively, from the transmit module 41 of the first protective relay 100 to the receive module 44 of the second protective relay 102. As noted above, virtual terminal data refers to data provided by a user located at a local relay (e.g., the first io relay 100), to a remote relay (e.g., the second relay 102) via the communication link 34. In such a configuration, the local relay operates as a virtual terminal to allow the user to query and/or control the remote relay with the familiar serial port user interface passing data on otherwise unused channels. The virtual terminal scheme also adds fast meter/operate capability. Like the digitized analog values described above, the virtual terminal data is serialized bit-by-bit such that, for example, 18-bit virtual terminal data is transmitted bit-by-bit in 18 sequential serial messages where the first two bits are payload flags and the last sixteen bits are two 8-bit data bytes. For example, the 18-bit virtual terminal data may be expressed as: PiP2di6di5di4di3di2dndiodgd8d7d6d5d4d3di where pi=1 indicates that drds is a

0 payload byte, and p₂=1 indicates that dg-di6 is a payload byte (see, FIG. 3).

[0032] The eighth data channel 54 is dedicated to synchronization information transmitted as channel data bit TMB8 from the transmit module 41 of the first protective relay 100 to the receive module 44 of the second protective relay 102. The synchronization information enables synchronization of the data channels associated with the analog values 59, 60, 61 and the virtual terminal data 62. Thus, when any of the data channels 47-53 are used for anything other than the output status indication bits, a dedicated synchronous channel is allocated for synchronization information transmitted as channel data bit TMB8.

[0033] Although illustrated utilizing an eight data channel arrangement, it should be understood that a different number or arrangement and/or assignment of data channels can be used by the first and second protective relays 100, 102 of the communication system 40. Accordingly, the two data channels of output status indication bits in combination with the three data channels of analog values and the two data channels of virtual terminal data illustrated in FIG. 2 is arbitrary. The output

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WO 2013/119315 PCT/US2012/068958 status indication bits could occupy more or less or no data channels, the analog values could occupy more or less or no data channels, and the virtual terminal data could occupy more or less or no data channels. In addition, one analog value can occupy more than one data channel for speedier transmission. Similarly, virtual terminal data can occupy more than one data channel for speedier transmission. [0034] Further, in one embodiment of the invention, the arrangement and/or assignment of the data channels may be fixed, while in another embodiment, the arrangement and/or assignment of the data channels may be dynamically changed during relay operation, depending on the desired configuration of the protective io relay(s) 100, 102. As a result, speed of receipt of the channel data by the receive module 44 is adjustable based on the assignment of the channel data to the number of data channels.

[0035] For example, if 18-bit virtual terminal data is dynamically assigned to one data channel during a high activity period of relay operation, it is transmitted bit-by-bit in is 18 sequential serial messages, and then reassembled for use by the receiving relay. If one message is transmitted every 1 millisecond via the communication link 34, 18 milliseconds are required for receipt of the entire 18-bit virtual terminal data. In contrast, if the same 18-bit virtual terminal data is dynamically assigned to three data channels during a lower activity period of relay operation, it is transmitted in groups

0 of 3 bits in 6 sequential serial messages, requiring six milliseconds.

[0036] Prior to transmission, each of the eight channel data bits TMB1-TMB8 is encoded by an encoder 65 to form an encoded message 66 using one of any number of suitable techniques. The encoded message 66 may therefore have one of any number of suitable formats, depending on the encoding scheme selected. For

5 example, in one encoding scheme, the encoded message 66 may include 36 or 40 bits, divided into four 9-bit (for 36 bit length) or 10-bit (for 40 bit length) characters plus a number of idle bits. The number of idle bits may vary depending upon the selected transmission speed.

[0037] Continuing with the example, the bits may be assembled such that the first 930 10 bit character includes a single start bit followed by the six channel data bits

TMB1-TMB6, followed by an odd parity bit and one or two stop bits, as selected by the user. The second character may include a second single start bit, followed by the six channel data bits TMB5, TMB6, TMB7, TMB8, TMB1 and TMB2, followed by an odd parity bit and one or two stop bits. The third character may include a start bit

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WO 2013/119315 PCT/US2012/068958 followed by the six channel data bits TMB7, TMB8, TMB1, TMB2, TMB3 and TMB4, followed by an odd parity bit and one or two stop bits. The fourth and final character in the message may include a single start bit followed by the six channel data bits TMB3-TMB8, followed by an odd parity bit and one or two stop bits. The remaining bits, if any, are a variable number of idle bits, depending upon transmission speed of the data.

[0038] Using such an encoding scheme, each of the channel data bits TMB1-TMB8 are repeated three times in the four character portions of one encoded message 66 with single stop and parity bits and one or two stop bits inserted between each io character portion of the encoded message 66. This encoding scheme allows the receiving, or second protective relay 102, to check for errors that may have occurred during transmission.

[0039] In addition to assembling the bits into messages, each of the first and second protective relays 100, 102 may be adapted to further encode and decode using an identifier pattern selected during system configuration. For example, if preprogrammed to include one particular identifier pattern, the transmit encoder 65 logically inverts one of the four characters in each of the messages as a means of encoding the identifier pattern into the message. As described below, the receiving, or second, relay 102 then ensures that the received message has been encoded

0 with the correct identifier pattern. Although described as assembling messages where one character is logically inverted, it should be understood that other suitable formats and encoding schemes may be utilized by the encoder 65 to generate the encoded message 66.

[0040] The encoded message 66 is then applied to the UART 43, adapted to satisfy several operating parameters for the system. In general, the UART 43 converts the encoded message 66 into a serial message 67 for transmission as part of a serial message stream via the communication link 34. Accordingly, the receiving UART 46 must also be capable of checking the received serial message 67 for proper framing (the presence of one stop bit per byte) and proper parity, and detecting overrun errors.

[0041] The UART 43 can be programmed for various baud rates. For example, it can be programmed for baud rates ranging from 300 through 115,000. The UART 43 is additionally adapted to synchronize both transmit and receive serial messages using transmit and receive clocks externally supplied. As will be appreciated by one skilled io

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WO 2013/119315 PCT/US2012/068958 in the art, the method of bit synchronization, using start and stop bits or using synchronizing clocks, is one of any number of suitable methods for synchronization.

[0042] Subsequent to being prepared for transmission by the UART 43, the serial message 67 is transmitted over the communication link 34 to the receive-module 44.

The sampling and transmission rates can be varied depending on the desired operation of the transmitting relay.

[0043] Referring now to the receive module 44, the receiving UART 46 provides the counterpart functions of the transmitting UART 43. When the serial message 67 is received by the receive module 44, the UART 46 performs several data checks on io each character of the serial message 67. It also checks each character of the serial messages 67 for proper framing, parity and overrun errors.

[0044] From UART 46, the characters of the serial message 67 are passed to a decoder 68. In general, the decoder 68 reassembles groups of four characters in order to reconstruct the four character message. Next, the decoder 68 checks each is message for errors, and also examines the results of the UART checks described above. If any of the checks fail, the decoder 68 discards the message and de-asserts a DOK (data OK) flag 94 for that message in a register 95 (see, FIG. 3).

[0045] More specifically, in the illustrated example, the decoder 68 ensures that there are the three copies of the eight channel data bits TMB1-TMB8 included in the

0 transmitted four-character encoded message 66. If an identifier pattern was used to encoder the encoded message 66, the decoder 68 also checks to ensure that the encoded message 66 includes the identifier pattern. It should be noted that the encoding/decoding scheme described above is one of any number of suitable encoding/decoding schemes to enable error detection that may be utilized in the

5 method and apparatus of the invention.

[0046] As a result of operation of the decoder 68, the DOK flag 94 and the channel data bits RMB1-RMB8 are provided. The received channel data bits RMB1-RMB8 are the mirror or replica of transmitted channel data bits TMB1-TMB8. The data OK (DOK) flag 94 provides an indication of whether errors were detected in the received message.

[0047] Like the transmit module 41 of the first relay 102, the receive module 44 of the second relay 102 includes an eight data channel arrangement where two data channels are dedicated to the output status indication bits, three data channels are dedicated to three digitized analog values, two data channels are dedicated to virtual

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WO 2013/119315 PCT/US2012/068958 terminal data and one data channel is dedicated to synchronization information. Accordingly, the output status indication bits 57 are received as channel data bits RMB1 and RMB2 via data channels 70 and 71, respectively, and are applied to one or more security counters 69. The security counters 69 operate to ensure that the state of the received channel data bits RMB1 and RMB2 remain constant for a preselected number of received serial messages 67 before the output status indication bits are utilized by downstream processes. Ensuring that the state of the output status indication bits remain constant increases the reliability and security associated with the output status indication bits 57.

io[0048] Because the two channel data bits RMB1 and RMB2 are transmitted bit by bit, no synchronization of those bits is required. The channel data bits RMB1 and RMB2 are used by the second relay 102 to make determinations concerning operation of the power system 10 (as detected by the first protective relay 100) including possible circuit breaker trip action when appropriate. In the illustrated example, the digitized analog values 59, 60 and 61 are received as channel data bits RMB3, RMB4, and RMB5 via a data channel 72, a channel 73 and a channel 74, respectively. Each of the three digitized analog values 59, 60, 61 are received serially one bit per message per data channel, and are then parallelized in a parallelize element 78. The parallelize element 78 re-assembles each of the three digitized analog values from

0 received successive decoded messages 58. As noted above, in the illustrated example, each of the digitized analog values 59, 60, 61 includes eighteen bits. In an embodiment, sixteen bits are used for information while the remaining two bits are unused. Therefore, for every 18 messages, a complete original analog value is received on each corresponding data channel.

25[0049] Similarly, the virtual terminal data 62 is received as channel data bits RMB6 and RMB7 via data channels 75 and 76, respectively. Like the analog values 59, 60, 61, the virtual terminal data 62 is received serially one bit per message per data channel, and is also parallelized in the parallelize element 78. In the illustrated embodiment, the virtual terminal data 62 includes eighteen bits. Sixteen bits of the eighteen bits are utilized for virtual terminal data, where the sixteen bits are divided into two eight-bit bytes. The two remaining bits are used to indicate which of the two eight-bit byte fields actually contain virtual terminal data, and which, if any, are idle, (e.g., waiting for user input). Thus, for every 18 decoded messages 58, two virtual terminal bytes are received on each corresponding data channel 75, 76. After

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WO 2013/119315 PCT/US2012/068958 parallelization via the parallelize element 78, the analog values and the virtual terminal data are provided to the second protective relay 102.

[0050] Again, the particular arrangement of the eight data channel bits TMB1-TMB8 is established in accordance with the user's communication requirements. Different numbers of output status indication bits, analog values and virtual terminal data can be utilized to form seven bits of the eight channel data bits TMB1-TMB8.

[0051] A data channel 77, or synchronization channel, is dedicated to the remaining channel data bit, RMB8. The channel data bits RMB8 of the synchronization channel enable the receiving decoder 68 and parallelize element 78 to find the start and stop io boundaries serial messages that include the digitized analog values and virtual terminal data. The synchronization channel is necessary when any of the other channel data bits include the digitized analog values or the virtual terminal data. If all of the channel data bits are used for output status indication bits only, no synchronization is necessary and the data channel 77 may be used for output status indication bits.

[0052] In order to determine that a complete (four character) bit message has been received, the second relay 102 identifies the first byte of each of the bit messages via message synchronization. In one embodiment, message synchronization is maintained by counting modulo 4 from the first received byte after byte

0 synchronization is achieved. Accordingly, each time the counter rolls over, the first byte is received.

[0053] FIG. 3 illustrates an exemplary received frame 80 of the relay-to-relay direct communication system 40, according to an embodiment of the invention. As illustrated, the received frame 80 includes 18 messages where a series of the

5 bottom channel data bit (TMB8) provides the 18-bit synchronization information after encoding, transmission and decoding. In addition, the analog values and virtual terminal data are received as channel data bits RMB3-RMB7 via data channels 7276.

[0054] Referring to the data channel 77, or the synchronization channel, a special frame synchronization pattern, for example 000001, is utilized to indicate that all other data channels (e.g., data channels 70-76) are at the beginning of a frame. In the illustrated example, when the last six bits received on the synchronization channel are 000001 (the 1 being most recent), then the other data channels are determined to be at a frame boundary. For example, the synchronization channel

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WO 2013/119315 PCT/US2012/068958 may be expressed as ded7d6d5vd4d3d2di1pt000001 where, d_x=virtual terminal data, 1=binary one, O=binary zero, p=1 indicates that the virtual terminal data is valid, v is a virtual terminal flag byte; it is normally 1, but is set to 0 to indicate a special flag byte is in the virtual terminal data, and t=time sync bit.

[0055] A comparator 91 in FIG. 3 is adapted to enable detection of the special frame synchronization pattern in the six most recently received channel data bits (from the six most recently received messages). Upon detecting the special frame synchronization pattern via operation of the comparator 91, a modulo 18 counter 92 is interrogated. If the modulo 18 counter 92 is not zero, it is reset to zero and the io data on the synchronization, virtual terminal data and analog value channels (i.e., channels 72-77) since the last valid frame sync (FS) signal 97 is discarded. Therefore, if the modulo 18 counter 92 is at zero, if all of the 18 most recent data OK (DOK) flags in register 95 are valid (e.g., a binary 1 value) and if the comparator 91 is asserted indicating detection of the special frame synchronization pattern, then an

AND-gate 96 asserts the FS signal 97, resulting in the analog values and virtual terminal data being utilized by the receiving, or second relay 102.

[0056] The synchronization channel, dedicated to the channel data bit RMB8, includes an additional virtual terminal character separated into two four-bit segments 80 and 82. Further, a bit 84 has a binary 1 value if the additional virtual terminal

0 character contains valid data, and has binary 0 value if the additional virtual terminal character is idle (such as might be the case if the virtual terminal session is waiting for input from the user). A bit 85 of the synchronization channel 77 has a binary 1 value, and a bit 86 typically has a binary 1 value, except under special conditions described below. When both of the bits 84 and 85 have a binary 1 value, five

5 consecutive zeros in the synchronization channel are not possible. This ensures that the frame synchronization pattern 000001 detected by comparator 91 can only occur at frame boundaries.

[0057] The additional terminal character contained in half-bytes 80 and 82 can also include control characters, intended to indicate from one relay (transmitting) to the other (receiving) when virtual terminal communication should be established, terminated, paused, etc. When one of these control characters is included in the additional virtual terminal character, bit 86 is forced to a binary 0 value. The special control characters are chosen carefully by the system designer such that, even with

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WO 2013/119315 PCT/US2012/068958 bit 86 at the binary 0 value, the frame synchronization pattern 000001 can only occur at a frame boundary.

[0058] In addition, a bit T 98 in the synchronization channel comprises a separate serial data stream, transmitted at the rate of one bit per 18 messages (frame). This separate serial data stream contains date and time information. Each time the FS signal 97 asserts, a time synchronization device 88 accepts the bit T 98. An additional frame synchronization system, similar to the frame synchronization system described above, allows the time synchronization device 88 to recognize the boundaries between successive time synchronization messages. Namely, a specific io frame synchronization pattern is placed in the serial data stream formed by the bit t 98 (i.e., a bit t serial data stream). A comparator detects the specific frame synchronization pattern, and signals that the time-of-day and calendar day information, contained in the bit T serial data stream may be used. The data included in the bit T serial data stream is formatted such that the frame synchronization pattern can only occur at frame boundaries. The time synchronization device 88 then updates the time-of-day clock and the calendar day with the time-of-day and calendar day information contained in the bit T serial data stream.

[0059] Unlike typical (analog) control inputs of protective relays, the relay-to-relay direct communication system disclosed herein includes communication link

0 monitoring capability via detection of corrupted serial messages when they occur. That is, when a corrupted serial message is received by the receive module 44, it may be concluded by the receive module that the corrupted serial message is the result of faulty operation or degradation of the communication link 34 and/or associated transmission equipment. Suitable alarming may be utilized to notify the

5 user of the condition where the communication link 34 and/or associated equipment remains faulty for a predetermined duration.

[0060] The relay-to-relay direct communication system disclosed herein also includes communication link monitoring via detection of missing serial messages. Because, the serial messages 67 are transmitted via the communication link 34 at pre30 determined periodic intervals, or at a predictable rate, it can be concluded by the receive module that the missing serial message(s) 67 is/(are) the result of faulty operation or degradation of the communication link 34 and/or associated transmission equipment. For example, if the transmit module 41 is transmitting 250 serial messages every second (a rate of one message every 4 milliseconds), and the

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WO 2013/119315 PCT/US2012/068958 receive module 44 does not receive a serial message in an 8 millisecond period (4ms normal rate plus a 4ms margin), a problem with the communication link and/or associated equipment may be concluded. In both-instances, the DOK flag 94 indicates the problem with the communication link 34 and/or associated equipment, and the received analog values and/or virtual terminal data is not utilized by the receiving relay (see, FIG. 3).

[0061] The relay-to-relay direct communication system disclosed herein further includes an ability to determine communication link availability, or channel availability, defined as that portion of time the communication link 34 and/or io associated equipment is capable of properly delivering uncorrupted serial messages 67. Communication link availability may be calculated by dividing the aggregate number of all of the received uncorrupted serial messages by the total expected serial messages in a recording period. For example, for a recording period of 24 hours, at 250 serial messages per second the transmitting module 41 transmits

21,600,000 messages and the receive module 44 receives 21,590,000 serial messages 67 because 9000 of the serial messages were corrupted and 1000 of the serial messages were missing. The channel availability would therefore be 21,590,000/21,600,000=99.9537%. Suitable alarming may be utilized to notify the user when the channel availability falls below a predetermined threshold.

0 [0062] As will be appreciated by one skilled in the art, variations of availability calculations are possible such as, for example, counting received frames 80 to determine availability of the digitized analog values and/or virtual terminal data. For example, because 18 received frames are needed to reconstruct an 18-bit digitized analog value, receipt of only 17 of the 18 frames would indicate an analog value

5 availability of 94.44%.

[0063] Accordingly, the relay-to-relay direct-communication system disclosed herein is adapted to (1) directly communicate output status indication bits which represent the result of protection functions by one of the relays, (2) directly communicate selected analog values representing one or more functions of the relay, (3) directly communicate virtual terminal data provided by a user to one of the relays via the other relay, (4) monitor the communication link between the two relays, (5) determine communication link availability and (6) provide time synchronization. The analog values and the virtual terminal data are processed in serial fashion in successive messages on channels not used by the output status indication bits. The time

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WO 2013/119315 PCT/US2012/068958 synchronization data is processed in serial fashion in successive frames (18 messages) of data.

[0064] As noted above, the number of and assignment of data channels for the output status indication bits and the additional data (analog values and virtual terminal data) can be pre-selected by an operator or can be dynamically selected during relay operation. The additional data may include analog values only, virtual terminal data only or a combination of analog values and virtual terminal data. The synchronization channel is dedicated for purposes of synchronizing the additional data, to transmit/receive additional virtual terminal data, time information and io calendar (date) information. This results in the channel capability of the basic transmission arrangement disclosed in the '750 patent being used to its maximum extent, while providing the benefits of the existing fast and highly secure transmission of output status indication bits.

[0065] FIG. 4 illustrates a power protection system 400 utilizing a primary 410 and a backup 420 protection device to oversee the operation of a circuit breaker 430. As illustrated, both the primary device 410 and the backup device 420 are identical. The circuit breaker provides a breaker status signal 434,436 to both the primary 410 and backup 420 devices. The breaker status signal 434,436 indicates whether the breaker is open or closed, and is used by both the primary device 410 and the

0 backup device 420 to determine whether or not to open the circuit breaker on detection of a fault.

[0066] The primary device 410 and the backup device 420 also provide overcurrent indications 444,446 to an alarm grid 440. Further, the breaker provides a breaker gas pressure alarm signal 438 to the backup device 420. As explained later, the

5 backup device transmits this alarm condition over a link 415 to the primary device 410. The primary device 410 processes the transmission and outputs a breaker gas pressure alarm 448 to the alarm grid 440.

[0067] The primary device 410 is also connected to a communications network 450. An operator may use a computer 460 connected to the same network 450 to send commands to the primary device 410. The operator may also direct commands to the backup device 420 through the primary device 410, which is coupled to the backup device by link 415.

[0068] FIG. 5 is a block diagram of a device-to-device direct communication system 500 within the power system 400, constructed according to an embodiment of the

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PPH invention. FIG. 5 is largely analogous to FIG. 2, discussed earlier. However, FIG. 5 utilizes sixteen data channels, and their specific use is described below. The first eight data channels 531-538 are used as “virtual output bits” for the primary device. The virtual output bits 511-518 denoted VOB1-VOB8 are transferred into the first eight data channels 531-538. The primary protective device 504 transmits the status of the virtual output channels to the backup protective device 556 which operates output contacts in accordance with the virtual output channels, as explained later.

[069] The next six data channels 519-524, denoted IB1-IB6 (input bit) are virtual input channels. The primary protective device 504 collects the status of its input contacts 508 and places the collected status into the input bits 519-524. Those bits are then transmitted to the backup protective device 556, which maintains corresponding virtual input bits, and may use the virtual input bits in its internal calculations.

[070] The final two data channels 525-526, denoted CMD1-CMD2 are command channels. Using these channels, the primary protective device 504 may issue commands to the backup device 556. The commands may be relayed through the primary protective device 504 from an operator as illustrated in FIG. 4. The commands may also be sourced from the operation of the primary device 504. For example, an external operator could alter the cold load pickup setting both the primary protective device 504 and backup protective device 556 using the CMD data channels 525-526.

[071] When a frame is ready to transmit, the processor encodes at 550 the data using any one of a number of suitable techniques. The data is then passed to a UART 552, where it is transmitted by a link 555 to the backup protection device 556. The backup protection device 556 then retrieves the data from a UART 579 and decodes at 580 the data into sixteen parallel received bits 561-576. The received bits 561-576 are separated into _Obi-s (output bits 18) 581-588, VIB1-6 (virtual input bits 1-6) 589-594, and CMD1-2 (command bits 1-2) 595-596. The backup protection device adjusts its output contacts (not shown) to conform to the received output bits. It also updates its internal operations with the virtual input bits, and executes any commands required by the command bits.

[072] FIG. 6 is an exemplary received frame 600 of the device-to-device direct communication system 500, according to an embodiment of the invention. As illustrated, the received frame includes sixteen bits 601-616. Of these, eight are output bits 620. The processor

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PPH

660 reconfigures the output contacts 651-658 to match the state of the output bits 620. The received frame also includes six virtual input bits 630, which correspond to inputs of the primary protection device 504. The processor 660 adjusts its internal memory and operating state based on the virtual input bits 630. Finally, the received frame includes two command channels 640. These channels may encompass messages that are many bits long, and will need to be assembled frame by frame before they can be executed. Once the command messages are assembled, they are executed by the command processor 640, which adjusts the internal state of processor 660 and output contacts 650.

[073] The virtual input bits 630 can be used to convey the status of an input contact from one device to the other device. For instance, one device may monitor signals, such as a circuit breaker-in service signal, a circuit breaker test mode signal, or a circuit breaker manual close indication signal. The monitored signals may then be transformed into digital bits and transferred to the other device, where they are used internally in the second devices calculations. Other signals which may be monitored using virtual input bits are cold load pickup on/off, or the status of a second circuit breaker.

[074] Each virtual output bit may be based on a single setting within the primary protection device, or a combination of settings within the primary protection device. The table below illustrates some common power protection settings:

<td> Setting</td><td> Description</td>

<td> 50PH</td><td> Phase Instantaneous Definite-Time Overcurrent Elements</td>

<td> 50N</td><td> Residual Ground Instantaneous Definite-Time Overcurrent Elements</td>

<td> E50Q</td><td> Negative-Sequence Instantaneous Definite-Time Overcurrent Elements</td>

<td> E51S</td><td> Selectable Operating Quantity Inverse Time Overcurrent Element</td>

<td> EV/D1</td><td> Manual Close Command for Circuit Breaker D1</td>

<td> EV/D2</td><td> Manual Close Command for Circuit</td>

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<td></td><td> Breaker D2</td>

<td> 43OP</td><td> Reclosing Control Activation Parameter</td>

<td> 43PR</td><td> 51 PR Detector Activation Parameter</td>

[0075] Virtual output bits may also be used so that one device; i.e.; the primary device; may control output contacts on another device; i.e.; the backup device. Some virtual output bit functions can be ground overcurrent on/off indication, remote on/off indication, and auto-reclosing of the second circuit breaker.

[0076] So, for instance, using the disclosed invention, a virtual output bit could be set in the primary based on a negative-sequence instantaneous definite-time overcurrent element (E50Q), or it could be based on a negative sequence instantaneous definitetime overcurrent element and a phase instantaneous definite-time overcurrent io element (50PH).

[0077] Figure 7 depicts a further refinement of the disclosed communications system. As with the previously discussed communications system, this communications system makes use of unused bits within the payload of a real-time communications stream. However, instead of communicating virtual terminal data, the refined communications system creates one or more general purpose virtual communications channels. These virtual communications channels can be transmitted along with real-time bandwidth intensive data over the same communications lines used by the real-time data. This aspect of the disclosed communications system is especially useful where a real-time quantity is

0 communicated over a relatively slow speed connection, such as, for example, a 56 kbps or 64 kbps serial connection. In such circumstances, a single real-time signal may require the entire bandwidth of the communications medium, and any additional quantities that were desired to be communicated would require additional physical communications lines. However, by using the disclosed communications system, a number of slow-speed virtual channels can be created using spare bits from the primary real-time communications session.

[0078] As an example, a “Line Current Differential” or “87L” function transmits local currents as samples or phasors, as well as restraining terms derived from local currents, and various one bit quantities related to the core 87L function, such as, for example, an indication of synchronization of the device to an external time source, an indication of the detection of an external fault, a test-in-progress indication, and a

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WO 2013/119315 PCT/US2012/068958 charging current compensation in progress indication. As the 87L function is timecritical, using a relatively slow speed connection, an 87L function may transmit a packet approximately every 1-8 ms. Accordingly, assuming 1 unused bit within an 87L packet is used to create a single virtual channel, a communications rate of 250 bps can be achieved, assuming that an 87L packet is sent every 4 ms.

[0079] There are numerous functions that the low bandwidth virtual communications channels disclosed herein can utilize. Such functions include, for example, multiended fault location, i.e., the sharing of voltages, calculated system impedances, or other special quantities to facilitate better fault location as compared with a single10 ended fault location method that uses just local data, executing commands on a remote relay, such as putting it in test mode, extracting fault records and/or metering and event logs from a remote device, extracting device diagnostics data from a remote device, changing settings on a remote device, crude synchronizing of clocks and calendars in devices that are not independently synchronized to another external time source, the creation of a virtual terminal by which commands can be entered without interrupting the functioning of the device, and periodically sending metering data to facilitate automatic control and/or protection applications. Other applications where a human operator needs to interface with a device located remotely from the operator, or automatic functions that utilize low bandwidth / slow

0 data can also be accommodated using the virtual channels disclosed herein.

[0080] Generally, a serial communications channel requires a data line, a clock, framing, and a data integrity verification method. The disclosed virtual communications channels provide data bits using one or a few bits of an underlying real-time session, such as an 87L session. As packets of real-time quantities are

5 usually sent at regular intervals, the packet itself can serve as a clock. Similarly, sequence numbers within the packets of the underlying session can serve as a framing mechanism. Similarly, the underlying packets will contain integrity checks, such as CRC or BCH checks, and accordingly, errors introduced by noise in the communications channel can be assumed to be detected and eliminated through a retry mechanism. Alternatively, an additional integrity check can be appended onto the packets transmitted via the virtual channel, decreasing available bandwidth, but adding an additional guarantee of data integrity.

[0081] Figure 7 is similar to Figure 2, except that certain elements have been modified and/or re-labeled. Transmit module 741 includes several re-labeled

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WO 2013/119315 PCT/US2012/068958 elements such as element 57, labeled “output bits” has been replaced with element 757, labeled “Real-time protection data,” elements 59-62 have been removed and replaced with element 762 labeled “background session data,” elements 47-54 have been removed and replaced with element 747 labeled “data frame,” and element 743 labeled serial communications channel has been substituted for element 43 labeled “UART.” The function of element 757 is similar to that of removed element 57, except that element 757 may contain additional real-time protection data, such as, for example, “Line Current Differential Protection Data.” Elements 59-62 have been replaced with a general purpose communications session over which analog values, io virtual terminal data, multi-ended fault location data, meter data, and time synchronization data may be transmitted. The eight bit data channel represented by elements 47-54 of Figure 2 have been replaced with element 747 depicting a communications channel of any size, such as, for example, 256 bits, of which a few bits are dedicated to a background session. The bits used for the background session may be background session bits. Element 43 of Figure 2 has been replaced with a synchronous serial communications channel interface 743 that may be configured to be compatible with a number of standard communications links, such as, for example, ITU-T G.703, EIA-422, and IEEE C37.94 Element 743 may also be configured to support one or more direct fiber links.

0 [0082] The changes to the receiver track the changes to the transmitter. That is, the receive module 744 includes a serial communications channel interface 746 that may be compatible with a number of standard communications links. Data frame 777 replaces the elements 70-77 and may be a communications channel of any size, such as, for example 256 bits, of which a few bits are dedicated to a background session. Real-time protection data module 787 may contain additional real-time protection data received from the transmit module 741. Further, background session data module 792 receives the parallelized background session data.

[0083] The description herein may be applied to various types of communication between lEDs. As mentioned above, the slow-speed communications channels may be used to communicate data between lEDs within a real-time data stream. The slow-speed communications may include various communications that may affect calculations and operations performed by the lEDs.

[0084] In one example, the lEDs may communicate fault location information using the slow-speed communication. Fault location information may be shared, for

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WO 2013/119315 PCT/US2012/068958 example, between lEDs protecting a predetermined section of an electric power delivery system. The lEDs may be configured to use impedance-based fault location to determine a location of a fault. For example, the lEDs may determine a location of a fault as a ratio of the distance to the fault to the length of an electric power line (such as a transmission line) calculated using impedance to fault and the impedance of the electric power line. The ratio of the impedance to the fault over the impedance of the electric power line may provide an estimation of the fault location on the electric power line. To this end, the lEDs may communicate information such as voltage phasor, current phasor, and other information related to impedance based io fault location. Such information may be used to calculate line constants such as the impedance of the electric power line. Such information may be used to calculate fault information such as impedance to the fault. An IED could then use the line constant and the fault information to calculate a possible fault location.

[0085] In another example, lEDs may be configured to use traveling wave based fault location to determine a location of a fault. Traveling waves may emanate from a fault location outwardly to the ends of the electric power line. lEDs along the electric power line may collect such traveling wave fault signals, process them and share such information using the slow-speed communication described herein such that one or more of the lEDs may calculate the fault location using the traveling wave information. Traveling wave information may include waveform arrival time, or the like.

[0086] In another example, lEDs may be configured to share device information stored on the lEDs using the slow-speed communications described herein. Such device information may include device configuration information. Such device

5 information may include a settings file. Such device information may include one or more settings. Such device information may include device hardware revision information. Such device information may include firmware revision information.

[0087] In yet another example, lEDs may be configured to exchange time and date information. In some configurations, lEDs may receive a common time signal 30 common to the lEDs - such as a communications network common time, GPS time provided using a I RIG signal, WWVB, WWV, or the like. If such common time signal is not available, the lEDs may exchange time and/or date information. Further, in some configurations lEDs do not receive a common time. lEDs may use the slowspeed communications described herein to exchange time and/or date information.

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Exchange of such time and/or date information allows lEDs without explicit time signal to follow time coherent with other lEDs, benefiting precision of their timestamped records and the overall user interaction with the device

[0088] Note that the invention described herein utilizes a digital processor. As the algorithms described do not require any particular processing characteristics, any type of processor will suffice. For instance, microprocessors, microcontrollers, digital signal processors, field programmable gate arrays, application specific integrated circuits (ASIC) and other devices capable of digital computations are acceptable where the term processor is used.

io[0089] In addition, the term intelligent electronic device is used. An intelligent electronic device is defined, for terms of this application, as a power protection device (i.e.; non-power protection devices such as general computers are not intended) including a processor for decision making. Examples of intelligent electronic devices are relays of various types and recloser controls.

[0090] The foregoing description of the invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or to limit the invention to the precise form disclosed. The description was selected to best explain the principles of the invention and practical application of these principles to enable others skilled in the art to best utilize the invention in various embodiments and

0 various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention not be limited by the specification, but be defined by the claims set forth below.