Variable sized information frame switch for on-board security networks

CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 VARIABLE SIZE INFORMATION FRAME SWITCH FOR ON-BOARD SECURITY NETWORKS The present invention relates to packet-switched transmission networks intended to convey critical information for the transmission. security with special requirements in terms of guarantee and delivery time.

Such secure transmission networks have many possible fields of application, including the interconnection of the onboard equipment of an aircraft for the exchange of instructions and critical information.

A packet-switched transmission network is generally referred to as an ATM or switched ethernet network, the acronym coming from the Anglo-Saxon "Asynchronous Transfer Mode". It consists of a set of interconnection nodes called “ATM or ethernet switches”, joined by transmission links, wired or not, constituting a mesh of the space where the entities having to communicate with each other are distributed.

To be transmitted over an ATM or Ethernet network, information must undergo two successive formatting.

It must first of all be digitized and put in the form of one or more binary message data packets completed, as a preamble, by binary service data containing various instructions useful for routing within the network 2o including identifiers of the packet destination entities, to constitute datagrams that can be handled by ATM or ethernet switches.

Then these datagrams must themselves be put in the form of an electrical or optical transmission signal adapted to the physical characteristics of the transmission links interconnecting the ATM or ethernet switches.

The main difference between ethernet and ATM transmissions is the use of variable size packets (64 to 1518 bytes) for ethernet networks, while ATM transmissions are characterized by a fixed size.

In what follows, it is considered that the size of the packets is arbitrary, which allows the application to ATM or Ethernet networks.

CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 2 The focus on the security aspect leads to adopting in a packet switching network measures tending to guarantee the best, the routing of information in a maximum delay, even in the event of an operation degraded by a failure.

° 5 Among these measures, some are intended to eliminate the risk of loss or delay in routing information as a result of network congestion, others are intended to ensure that the information having, despite the precautions taken, lost their integrity during routing are rejected so as not to congest the transmission links and unnecessarily take up processing time in the switches.

The measures to eliminate the risks of loss or delay in the routing of information consist mainly in requiring the network to be deterministic to facilitate the analysis, a priori, of its behavior in all circumstances and to the size to support the maximum possible traffic, which amounts to guaranteeing a minimum throughput for each information flow routed through the network, from a sending entity to the attention of one or more recipient entities, said flows being called more concisely, virtual channels 2o.

For a transmission network to be deterministic, it is necessary that the virtual paths resulting from the instantaneous positions of the switches adopted at the times of the passage of information be predefined, invariant and only a function of the sending and receiving entities.

25 These constraints of being deterministic and guaranteeing minimum speeds on the virtual channels of the network connecting sender and recipient entities affect the size of the network, that is to say on the number and arrangement of switches and transmission links. ensuring the mesh of the switches but also on the 3o performances required of the switches and the links of transmission.

They result, for each transmission link, by an imposed minimum rate corresponding to the maximum foreseeable rate taking into account the fact that they can be used by several virtual channels and, for each switch, by the requirement to be able to correctly direct the data traffic arriving on its input-output ports when the CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 3 transmission links connected to its ports of input-output are all at their maximum predictable flow rates.

The measures with a view to rejecting the information conveyed by the network as soon as they have lost their integrity consist in providing, in the datagrams, integrity control information whose concordance with the apparent content of the datagram is verified before any operation of the datagram. 'routing and retransmission within a switch.

A switch mainly performs detection and demodulation, at each of its input-output ports, of the transmission signals reaching it via the transmission links to which it is directly connected, making it possible to retrieve the datagrams, temporary storage of information traffic received by all of its input-output ports while awaiting the execution of the routing operations of the datagrams being received to one or more output ports of the switch ,.

an analysis of the service binary data placed at the head 2o of each datagram in order to deduce therefrom a broadcast profile determining the output port (s) to which the datagram in question must be routed, the execution, as soon as possible, of the consistent broadcast profile in a recovery, in the buffer memory, of the traffic carrying the datagram under consideration and its presentation on the desired output ports, and remodulating the datagrams at the output ports to give them the form of a transmission signal adapted to their routing on the transmission links 3o connected to the output ports.

For the temporary storage of the various data traffic arriving in reception at the input-output ports of a switch, circulating memories are needed in a number equal to that of the incoming data traffic, with a capacity adapted to the required delays. of CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 4 storage and with a speed adapted to the rates of these incoming data traffic.

These circulating memories, which handle the incoming traffic while they are in digital form, are produced from sets of banks of registers, each set having its banks of registers scanned cyclically in writing, according to an invariant addressing law, at a rate sufficient to absorb the flow of the traffic in question.

In reading, each output port is allocated at a rate sufficient to restore the traffic rate considered, the possibility of accessing all of the circulating memories.

The latter can be located at the level of the input-output ports or gathered within a central storage device called a central buffer memory.

The present invention relates more specifically to a packet switch with a central buffer memory.

l5 The requirement of a guaranteed routing through a switch, of all the traffic reaching it on all its input-output ports at their maximum authorized speeds is reflected on its central buffer memory, by the need to tolerate, at the input and at the output, a flow rate 2o equal to the sum of all these maximum flow rates, which can lead to a very high flow rate.

Thus, a switch having 15 I / O ports with maximum rates of 100 Mbit / s must have a buffer memory accepting a rate of 1.5 Gbit / s for writing and reading.

This very high throughput required for the central buffer memory poses problems in terms of the management of the latter, its energy consumption and radio interference generated by the switching operations inherent in its addressing and in the read and write operations. of data.

Moreover, it is interesting to use the transit times of the 3o datagrams in the buffer memory as an integrity criterion.

In addition, although datagrams that are too old in the buffer are naturally overwritten by newer datagrams arriving through the same ingress port, it is useful to know the datagram processing times to quickly detect the presence of problems. operating within a switch and be able to take the measures CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 necessary to isolate this switch as quickly as possible.

The usual solution, which consists in dating the datagrams in transit through a switch, as a function of the instants of their reception, has the drawback of increasing the quantity of data to be stored in the buffer memory.

5 The object of the present invention is a packet switch with a central buffer memory for the momentary storage of information traffic reaching it through its input ports, that is organized and managed in such a way as to maximize the sum of the acceptable bit rates at the level of the input and output ports of the switch and to minimize its energy consumption and the electromagnetic disturbances generated by the switches caused by its addressing and operations in writing and reading.

It also aims at a packet switch with a central buffer memory for the momentary storage of the traffic of information reaching it by its input ports, which is managed in such a way as to give an implicit measure of the latency time undergone by each datagram. contained in the traffic of information that it sees passing.

It relates to a packet switch with several input ports and several output ports providing access to the switch, 2o incoming and outgoing data traffic using physical transmission links outside the switch and carrying information containing datagrams made up of binary message data and binary service data containing routing instructions, each input port, respectively output port, controlling access to the switch of incoming data traffic, respectively of outgoing data traffic and each physical link having a maximum rate imposed on reception as well as on transmission, said switch comprising at each of its ports d 'input ~ a demodulator circuit ensuring the demodulation allowing the 3o passage of the transmission signals conveyed by the transmission links which are connected to them, to the datagrams they contain, and ~ a circuit for extracting the binary service data contained in the datagrams received, at each of its output ports CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 6 ~ a modulator circuit ensuring the modulation allowing the passage of the datagrams to the transmission signals conveyed by the transmission links which are connected to them, and ~ a transmission management circuit executing switching instructions concerning the datagrams in transit, received by the switch on input ports, and at a central level, ~ a buffer memory with a set of memory registers 1o addressable in write and read mode to temporarily store the data traffic entering through the input ports , awaiting routing of the datagrams they contain for forwarding to one or more output ports, and with addressing buses, data and control allowing the selection in writing or in reading of each of its banks of registers, the number of banks of registers being at least equal to that of the input ports and sufficient to store the data traffic received on each port input over a period compatible with a maximum time allocated to the 2nd switch to direct the datagrams, ~ a sequencer punctuated by a clock, managing the address buses, of data and read-write control of the buffer memory, and the accesses of the demodulation and transmission management circuits to the buffer memory, this management consisting in dividing the banks of registers of the buffer memory into as many distinct groups as of input ports, - scanning, in writing, the banks of registers of each group in a cyclical manner according to an invariant 3o scanning law,.

- grant each input pig exclusive write access to a single group of register banks assigned to it, according to a periodicity compatible with the maximum rate of data traffic entering the switch through the input port considered, CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 7 - and grant all output ports general read access to all groups of register banks with a scan of their register banks starting from a bank of selectable starting registers and respecting the order of the scanning in writing, according to a periodicity compatible with the maximum binary rate of the data traffic leaving by the considered input-output port, and ~ a routing machine analyzing the binary service data associated with the datagrams routed by the data traffic in transit in the switch, stored temporarily in the buffer memory, to extract routing instructions, a broadcast profile determining the output ports forwarding then forwarding instructions to be executed by the transmission management circuits of the output ports identified by the broadcast profile, and being characterized in that said sequencer manages the accesses of the input ports and of the output ports to the buffer memory - by dividing the time measured by the clock into a repetitive series of time slots in which are distributed, of invariantly, the write and read accesses of the input ports and of the output ports to the groups of banks of registers of the buffer memory, each input port having at least one write access and each output port one read access to a bank of registers of the buffer memory during the repetitive series of time slots, and 3o - using an addressing system banks of registers of the buffer memory taking again in a first part of the individual address of a bank of registers within the buffer memory, the address of the group to which it belongs, this address part also identifying the input port having the access CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 8 exclusive in writing in the register bank considered, and, in a second part of the individual address of a bank of registers its relative position with respect to the banks of registers of its group to which it belongs within a write scan of this group.

Due to the management by the sequencer of the access of the input ports and the output ports of the switch to its buffer memory, the addresses of the banks of registers of the buffer memory make it possible to determine both the input port therefore the incoming data traffic from which the data word stored by a bank of registers originates and the date of registration of this word since the write accesses of the input ports to the memory as well as the banks of registers addressed during these write accesses depend only on the time variable delivered by the clock.

~ 5 Reading a bank of registers in the buffer memory then gives an implicit measurement of the storage time of the data word concerned and therefore of its latency time within the switch, a latency time which is also that of the datagram to which it belongs.

2o Advantageously, the buffer memory is organized into several modules operating in parallel and each having their banks of registers distributed between the different groups assigned in writing to the different input ports.

25 Advantageously, the buffer memory is organized into several modules of the same capacity operating in parallel and having their banks of registers distributed among the different groups assigned in writing to the different input ports by following the same distribution law.

3o Advantageously, the buffer memory is organized in two modules of similar capacities operating in parallel, one in writing, the other in reading and periodically exchanging the roles of writing and reading.

CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 9 Advantageously, the buffer memory is organized into three modules of similar capacities operating in parallel in writing and in reading, the actions of writing and reading in each of the three modules being out of phase with one another by a third of their period.

Advantageously, the buffer memory is organized into four modules of similar capacities operating in parallel in writing and in reading, the write and read actions in each of the four modules being out of phase with one another by a quarter of their period.

Advantageously, the accesses of the same nature, write or read, to the buffer memory initiated by the sequencer are grouped together during the repetitive series of time slots so as to minimize the frequency of the read-write and write-read transitions which are accommodation time generators during which the buffer memory is not operational.

Advantageously, the write accesses corresponding to the time slots grouped together so as to minimize the frequency of the read-write and write-read transitions, are made at addresses that differ from each other only by their first part encoding the input port number, their second part linked to the registration date remaining common to all the time slots grouped together. This results in a minimization of the number of high frequency switchings on the address bus during the write phases and consequently a minimization of the consumption and of the noise generated.

Advantageously, when an input port is inactive, it uses the write access in the time slot which is associated with it to write a shortened data word with a specific value indicating an absence of valid data.

This shortened data word uses only a few elements of the addressed register bank while the others take the values ​​corresponding to the maintenance of the data previously on the data bus.

As a result, the number of high-frequency switchings on CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 the data buses during the write phases is minimized. This consequently results in a minimization of the consumption and of the noise generated.

Advantageously, when an output port is inactive, the read access thus unused in the time slot associated with it is carried out at an address corresponding to the last useful reading.

As a result, the number of high frequency switchings on the address and data buses during the read phases is minimized. This consequently results in a minimization of the consumption and of the noise generated.

These precautions are particularly effective 1o for packet switches operating in a deterministic network context for which the average load of each link (physical transmission link) is low.

Advantageously, registers are reserved in each bank of the buffer memory for at least one datagram presence or absence flag.

An input port then takes advantage of periodic write accesses to the group of register banks allocated to it by the sequencer to either register a datagram being received and activate in each register bank being registered, the 2o datagram presence flag, or, in the absence of datagram reception, to only deactivate the datagram presence flag in each bank of registers being registered.

The datagram presence flag makes it possible to secure the operation of the switch by ensuring that its transmission management circuits only handle banks of registers of the central buffer memory actually containing datagram data.

Advantageously, the routing automaton has write and read access in the central buffer memory to store, in 3o banks of registers unused by the input ports and for each datagram stored or in the process of being stored, a label encapsulation containing its diffusion profile.

Advantageously, the routing automaton benefits from write and read access in the central buffer memory to store, in CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 11 banks of registers unused by the ports input and for each datagram stored or in the process of being stored, an encapsulation label containing its broadcast profile and an indication of its length.

Advantageously, the datagrams routed in succession on the same physical link are separated by a minimum time interval and the periodicity for assigning write access to the input port where the physical link ends is less than the duration of this. minimum separation time interval, which guarantees the presence in the group of banks of registers of the central buffer memory assigned in writing to an input port, at least one bank of registers unused at the separation between the stored data of two successive datagrams.

~ 5 Advantageously, the datagrams routed one after the other on the same physical link are separated by a minimum time interval and the periodicity for assigning write access to the input port where the physical link ends is less than the duration of this minimum separation time interval, which guarantees the presence in the group of banks 2o of registers from the central buffer memory assigned in writing to an input port, at least one bank of registers unused at the separation between the data stored in two successive datagrams, which is used to store an encapsulation label containing the broadcast profile extracted by the routing machine, of the service information included in the 25 datagram, this encapsulation label making it possible to secure the operation of the switch by ensuring that the transmission management circuits of the output ports perform operations in accordance with the broadcast profile associated with the datagram.

3o Other characteristics and advantages of the invention will emerge from the following description of an embodiment given by way of example.

this description will be farte with regard to the drawing in which ~ a Figure 1 shows an example of packet transmission network topology, CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 12 ~ Figure 2 shows an architecture packet switch with centralized buffer memory, ~ a figure 3 details the main parts of a switch input / output port, ~ a figure 4 shows, in a more functional form the packet switch architecture shown in Figure 2, ~ Figures 5 to 8 illustrate various examples of sequencing for access to incoming 1o and outgoing data traffic in the centralized buffer memory of a packet switch, in the context of memories with one, two, three or four modules operating in parallel, ~ Figure 9 illustrates formats for the data words stored in the banks of registers of the central buffer memory depending on whether or not these words belong to datagrams constituting the useful messages conveyed by the network, and ~ Figure 10 illustrates a format for an encapsulation label added to a datagram during its passage 2o in a packet switch and used for the purpose of controlling its routing within this switch.

FIG. 1 shows various devices 10 to 18 which communicate with each other via a packet-switched transmission network 20.

The sets of equipment 10 to 18 are of unequal size and geographically dispersed over an area covered by the packet-switched transmission network 20 which is shown schematically by a mesh of interconnection nodes or packet switches represented by circles, and 3o transmission physical links represented by straight line segments joining the interconnection nodes between them.

Each item of equipment represented by a rectangle is connected to the packet-switched transmission network, at one or more interconnection nodes placed nearby, through a specialized terminal not shown and one or more physical transmission links.

CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 13 For their handling through a packet-switched transmission network, the messages exchanged by the devices undergo a double formatting: on the one hand, a digitization giving them the appearance of a series of binary data and a formatting in datagrams adapted to the routing processing that they are subjected to by combinatorial and / or sequential logic circuits within each packet switch crossed and, on the other hand, a shaping of the datagrams into electrical or optical transmission signals for their routing by the physical interconnection links.

Datagrams are made up of a series of binary message data preceded by a series of binary service data containing information useful for their routing within the packet switches crossed.They follow an organization format or particular protocol adapted to characteristics of the combinational logic circuits ~ 5 and / or sequential performing the routing within the packet switches.

The electrical or optical signals used to route the datagrams on the physical interconnection transmission links connecting the packet switches to each other and to the equipment, are adapted to the physical characteristics of the links used.

At the ends of the transmissian links, whether at the level of the terminals connecting the equipment to the network or at the level of the input-output ports of the interconnection nodes of the network constituted by the packet switches, there are modulation and demodulation circuits ensuring the transformation of a transmission signal received by a physical transmission link into its corresponding datagram and conversely the transformation of a datagram manipulated at the level of an equipment terminal or d A packet switch into a transmission signal suitable for routing through the physical transmission links of the network.

These modulation and demodulation circuits will not be detailed because they do not form part of the invention.

In the example described, they are assumed to be suitable for asynchronous transmission signals which propagate one after the other on the physical links connecting the packet switches and which are formed. each of a phase modulation of a temporary carrier preceded in the preamble by a CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 14 unmodulated carrier end intended to facilitate carrier recovery during demodulation.

A datagram received and demodulated at an input output port of a packet switch must be routed within this packet switch to one or more other input-output ports to be re-transmitted on one or more links physical transmission directly connected to this packet switch in order to get closer to its destination (s).

This so-called routing operation, which is the essential task of a packet switch, may require a certain delay depending on the congestion of the re-transmission input-output ports.

Indeed, several datagrams can be received simultaneously by different input-output ports and have to be routed, for their retransmissions, to the same input-output port, which causes a traffic jam requiring the management of a queue of data. 'waiting.

~5 .

The possibility of a routing delay within a packet switch implies the need to provide in each packet switch a storage of the incoming data traffic carrying the datagrams, over a period of time greater than the maximum foreseeable routing delay within the considered packet switch.

This 2o temporary storage of each data traffic entering an interconnection node is done using circulating memories assigned individually to each traffic.

A circulating memory is formed by a group of banks of registers which are cyclically scanned for writing and reading in the same order of succession, at a rate sufficient to support the maximum rate allowed for the traffic of data to be stored and which are in sufficient number to ensure that the incoming traffic considered is stored for the required time.

The different groups of banks of registers assigned to the storage of incoming data traffic in a packet switch can be either delocalized and distributed at level 3o of the input-output ports of the packet switch, or centralized and united within a packet switch. a central buffer memory.

The centralization of the groups of banks of registers ensuring the temporary storage of the incoming traffic has the advantage, in a secure network, of allowing centralization and therefore simplification of the checks on the correct operation of a packet switch.

CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 FIG. 2 illustrates a possible architecture for a switch 1 of a packet switched network.

The packet switch 1 communicates with other packet switches in the network or with equipment connected to the network by mono or bidirectional physical transmission links.

It is connected to a two-way physical transmission link or to two one-way physical transmission links used, one for reception and the other for transmission, via a dedicated I / O input / output port.

In figure 2 three I / O input-output ports 21, 22, 10 23 are shown but the number of input-output ports is not limited and corresponds to the number of connections provided, for the packet switch considered, an input-output port providing the interface between a physical two-way transmission link or two physical one-way transmission links used one for transmission and the other for reception.

In the example shown, the input-output port 21 provides the interface with a physical two-way transmission link and the input-output ports 22 and 23 interface with two physical one-way transmission links used one on reception and the other on transmission.

Providing the interface consists of performing the modulation and demodulation tasks and a task of managing the queue on transmission.

The modulation task consists in putting the datagrams to be transmitted in the form of a transmission signal with physical characteristics adapted to those of the link used for transmission leading to the input / output port concerned.

The demodulation task consists in extracting the datagrams contained in the transmission signals received from the physical transmission link used on reception ending at the input-output port considered.

The queue management task consists of putting in a queue, one behind the other the datagrams to be sent when the transmission orders of the latter arrive simultaneously at the input / output port or at a rate that is too fast in view of the bit rate of the physical transmission link used for transmission.

An input-output port is connected to the internal processing circuits of the switch that it equips, by a data reception channel, a data transmission channel and several control ports.

By means of CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 16 receiving vr data it delivers the incoming binary data traffic arriving at the switch via the physical transmission link that it controls.

The data transmission path ve allows it to receive the datagrams that it must send and which come from other internal circuits of the switch.

The control ports including a routing request port rr, a datagram allocation port at and a datagram request port to be sent are used to manage its waiting queue.

FIG. 3 details the constitution of an input-output port, for example the input-output port 22.

This comprises modulator-demodulator circuits 220, 221 associated with a MAC circuit 222 and with a transmission manager circuit 223 provided with a queue management stack 224.

The modulator-demodulator circuits 220, 221 associated with the MAC (Medium Access Control) circuit provide in both directions, the interface between the datagrams circulating inside the switch and the transmission signals which correspond to them on the physical transmission links connected. at the considered I / O port.

The modulator 220 and the demodulator 221 take care of the tasks of the ph ~ sic layer, that is to say of the inclusion, of the binary data manipulated in the 2o switch, in a transmission signal capable of being transmitted in outside the switch, on a physical transmission link and the extraction of binary data contained in the transmission signals received by a transmission link.

The MAC circuit 222 accumulates the binary data supplied by the demodulator 221 in binary words whose length corresponds to the processing capacity in one operation of the internal digital processing circuits of the switch. It detects the start of reception of a datagram by analyzing its header reserved for binary network service data and sends, on the control port rr, datagram routing requests accompanied by network service information 3o extracted from the datagram considered to determine the routing profile of the datagram. It can also carry out an integrity check of each datagram received when the latter contain an integrity check code, for example a CRC code (Cyclic Redundant Code).

The transmission manager circuit 223 receives, on the control port at, datagram allocations each consisting of a CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 17 identification of a datagram to be sent available at the within the switch.

It places these datagram allocations in a queue management stack 224, for example of the "First IN First Out" type, and transfers, as a transmission request to the control port re, the most important datagram allocation. old appearing in the queue management stack 224 so that the data corresponding to the targeted datagram is applied to the send channel ve of the input-output port.

In addition to its input-output ports 21, 22, 23, the packet switch 1 shown in Figure 2 comprises: a routing controller 30, 1o a buffer memory 40 used to store over a certain period of data traffic arriving by the physical transmission links which are connected to it and a sequencer 50 managing the buffer memory 30 and access to the latter via the various input-output ports 21, 22, 23 and the routing machine 50.

The routing machine 50 is a combinatorial and / or sequential circuit, for example with a microprocessor, which processes the routing requests sent by the various input-output ports 21, 22, 23 in order to extract therefrom the routing profiles associated with each datagram being received by the interconnection node and generate, from these routing profiles, datagram allocation instructions intended for the input-output ports which have to re-send them.

The routing requests, which can appear simultaneously from several different input-output ports, are processed successively by the routing machine 30 which either manages a queue or scans regularly, in a determined order, the control ports rr of the various input-output ports of the interconnection node.

The buffer memory 30 is a collection of circulating memories whose presence is imposed by the obligation to manage queues at the input-output ports for the re-transmission of datagrams and, to a lesser extent, by the times. for processing routing requests.

It is made up of a set of banks of registers of lengths equal to that of the binary words supplied by the input / output ports 21, 22, 23, a length which is chosen as a function of the processing capacity in one operation, of the circuits. digital used in the packet switch.

CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 18 As represented in FIG. 4, the set of banks of registers of the buffer memory 30 is divided into as many separate groups 30a, ..., 30b , ..., 30n that there are input-output ports 21, 22, 23, cyclically scanned in an invariant order.

Each group 30a, 30b, ..., 30n of banks of registers is reserved in writing for the binary data traffic received by a determined input-output port 21, respectively 22, 23 so that all the binary data traffic received by all the input / output ports have individually, a group of register banks assigned to them to be temporarily recorded there.

1o Each group 30a, 30b, 30n has its registers scanned cyclically for writing at a rate sufficient to support the bit rate of the data traffic to which it is assigned.

Thus, at any time, in the buffer memory 40, there are found the faithful records of the binary data traffic received by the packet switch over a period which corresponds to the scan cycle in writing of its groups of banks of registers and which can be easily adjusted by varying the number of register banks per group.

Each group of banks of registers of the buffer memory 40 is scanned for reading according to cycles following the same order as the write cycles 2o but which can be initiated from any one of its banks of registers by all the ports d 'input-output since these can be assigned for re-transmission any datagram being received.

An input-output port identifies, in its routing requests, the datagram concerned, by the registration address of its start word in the group of banks of registers of the buffer memory 40 which is assigned to the data traffic. through which it reaches the packet switch.

This address is taken up by the routing automaton 30 in its datagram allocation instructions intended for the other input-output ports, in order to allow the transmission manager circuits of the 3 input-output ports concerned to recover binary data of datagrams temporarily stored in the buffer memory.

The write and read scans of the different groups of banks of registers of the buffer memory 40, which are carried out for the same group with no phase relationship between them but in the same order, and the management of access to the banks of registers of the different group of CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 19 buffer memory 30 by the input-output ports 21, 22, 23 and the routing machine 50 are the responsibility of the sequencer 40 of which the operating mode will be detailed.

The sequencer 40 divides the time measured by a clock into a repetitive series of time slots in which the write and read accesses of the input / output ports 21, 22, 23 to the memory register banks are distributed invariantly. buffer 30.

In order to obtain an operation of your buffer memory 30 in a set of circulating partial memories 30a, 30b, 30n assigned individually to the binary data traffic received by the various input-output ports 21, 22, 23 the sequencer 40 follows. , to address the banks of registers of the buffer memory, a particular addressing procedure.

This addressing procedure is based on a distribution of the banks of registers into as many groups as there are input-output ports, each group being individually reserved, for write operations, for a particular input-output port of the device. so that there is a one-to-one relationship between groups and I / O ports with respect to write operations.

Such a distribution of the banks of registers of the buffer memory into separate groups can be done naturally, by using, in the 2o addresses of the banks of registers, a few digits.

The addressing procedure differs depending on the write or read mode.

During a series of accesses to the buffer memory assigned to the same input / output port for write operations, the sequencer 40 selects the group of register banks assigned for writing to the input / output port. considered, and cyclically scans the banks of registers of this group in an invariant order on which the input-output port has no influence.

During a series of accesses to the buffer memory assigned to the same input-output port for the same reading operation, the 3o sequencer 40 leaves the input-output port to choose the group of banks of registers. to explore, and, within this group, the choice of the register bank to start the exploration but imposes a scanning order identical to that used for the write operations.

To summarize, the sequencer 40 allocates to each. input port an invariant periodic frame for write access to a single CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 reserved group of banks of registers of the buffer memory and a periodic frame for access in reading to a group of register banks left to the choice of the input-output port, said periodic read access frame following the same scanning order as the periodic frame used in writing for the selected group but with a phase shift left to the choice of the input-output port.

The periodic read and write access frames allocated to the same input / output port can be entangled with each other and with those assigned to the other input / output ports.

Because of this mode of management of the accesses of the input / output ports 1o of the packet switch to its buffer memory, the addresses of the banks of registers of the buffer memory make it possible to determine both the input-output port, therefore incoming data traffic, where the data word stored by a bank of registers comes from and the date of writing of this word since the access in writing of the input-output ports to the memory as well as the banks of registers addressed during these registration access depend only on the time variable delivered by the clock.

Reading a bank of registers from the buffer memory then gives an implicit measurement of the storage time of the data word concerned and therefore of its latency time within the packet switch, a latency time which is also that of the datagram. to which it belongs.

FIG. 5 illustrates an example of sequencing in accordance with this addressing procedure, provided for a packet switch with seven input-output ports each managing incoming binary data traffic and outgoing binary data traffic, all traffic of binary data having the same maximum guaranteed rate, and for a central buffer memory consisting of a module of banks of registers addressable one by one in a random manner.

The addressing of the register banks reflects an organization of the memory into seven separate groups of register banks assigned, in writing, in a one-to-one manner, to the seven input / output ports. It takes place at two levels, a first level written in large numbers corresponding to the group to which it belongs, that is to say to the input-output port to which the bank of registers concerned is assigned in writing, and a second level written in a small number giving the position of the register bank concerned in its group to which it belongs, that is to say its position in the invariant relative order CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 21 adopted to scan the banks of registers of a group concerned, on writing as reading.

With this type of central buffer memory structured in a single module, each time slot cut out by the sequencer in its clock signal is assigned to a particular input-output port, for an operation of determined type, write or read in a Accurate bank of buffer registers.

The sequencing begins with a series of time slots 0 to 6 assigned to successive write accesses WO-1, ..., W6-1 dedicated to each of the seven input-output ports, in the first register bank of each of the seven groups assigned to them individually in writing.

The numbered time slot 7 is not assigned to the input-output ports but to the change of write-read modes.

It does not lead to any operation on the buffer memory but prevents the duration ~ 5 of inaccessibility of the memory during a change of write read modes from being charged to an I / O port access time.

The sequencing continues with a series of time slots 8 to 14 assigned to successive read accesses RO-XOXo, ..., R6-X6Xs dedicated to each of the seven input-output ports.

During one of these 20 time slots 8 to 14, the input-output port, which has read access, chooses a group Xi of banks of registers from which it wants to read, and, within this group Xi, a particular register bank xi.

The choice of the group to be read Xi appears in its transmission request since it corresponds to the input-output port from the datagram to be transmitted while the choice of bank 25 of registers xi to be read within the elected group Xi is a choice implicit deduced from the address of the register bank containing the start of the searched datagram and from the reading progress of the datagram during the successive read accesses allocated to the same input-output port.

The time slot 15 is not assigned to the input-output ports 3o but to the change of read-write modes.

It plays a role analogous to the time slot 7.

The following time slots 16 to 22 are again devoted to successive write accesses WO-2, ..., W6-2 dedicated to each of the seven input-output ports, in each of the seven groups which have their CA 02437540 2003 -08-05 WO 02/076002 PCT / FR02 / 00843 22 are reserved individually for writing, but this time in the second bank of registers of each group and not in the first.

The time slot 23 is not assigned to the input-output ports but to the change of write-read modes.

It plays a role analogous to the time slots 7 and 15.

The following time slots 24 to 30 are again assigned to successive read accesses RO-XO ~ xo + 1 ~, ..., R6-X6 ~ Xs + y> dedicated to each of the seven input-output ports.

During one of these time slots 24 to 30, the input-output port which has read access chooses a 1o group of banks of registers in which it wants to read, supposed to be the same as in its previous access in read mode, the sought datagram not yet being fully recovered, and, within this group, the bank of registers following that previously read xi + 1.

The time slot 31 is not assigned to the input-output ports ~ 5 but to the change of read-write modes.

It plays a role analogous to the time slots 7, 15 and 23.

During the following time slots, the write and read access groups dedicated to each of the input / output ports follow each other regularly, separated by time slots dedicated to the changes of read write modes.

At each successive write access to the same input / output port, the register bank concerned within the group of register banks reserved for writing at the input / output port considered progresses by one in the immutable order adopted. for the write scan of the group in question so that after a certain time there is looping back and overwriting of previously written data with new data, the delay being that which is considered to be the maximum delay tolerated for the routing processing of a datagram by the packet switch considered.

3o At each read access to the same input / output port, the register bank concerned within the group of register bank explored progresses by one unit in the order adopted for the write scan of the group concerned and this, until the I / O port carrying out the reading considers that it has retrieved the whole of the sought datagram, this estimate being based on a priori knowledge of the length of the datagram CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 23 appearing in service data included in the head of the datagram.

The grouping of several memory accesses, of the same type, write or read, makes it possible to minimize the frequency of changes of read write modes and vice versa, which consume time and energy, and which are the source of noise. electromagnetic.

The periodic write access frame allocated to the same input / output port 1o must make it possible to absorb the maximum rate guaranteed for the data traffic received by this input / output port.

If this rate is B and the length of a bank of registers in the buffer memory b, this implies that the lapse of time separating two successive writes on behalf of this same input-output port must be equal to b / B .

For example, if the received binary data traffic rate is 100 Mbits / s and the register bank width is 32 bits, write access should be provided every 320 ns.

In the same way, the periodic read access frame allocated to the same input-output port must allow it to pass, through the physical transmission link that it uses for transmission, outgoing traffic of 2o data at maximum guaranteed rate.

For example, if this maximum guaranteed transmission rate is 100 Mbits / s and the width of the register banks of the buffer memory is 32 bits, read access must be ensured every 320 ns.

As it was considered in the preceding sequencing example that all the data traffic entering and leaving the packet switch considered had the same guaranteed maximum throughput, the time lapse separating two write accesses and two read accesses allocated to the same input-output port have the same duration marked TS in FIG. 5.

The buffer memory must support in writing and reading the 3o rates imposed by all the periodic frames of write and read access allocated to the various input / output ports.

As this buffer memory works in time-sharing between the various input / output ports, it must support in writing and reading the sums of the maximum binary rates guaranteed on transmission and on reception for all the input ports. -sorüe of the packet switch.

These CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 24 sums quickly reach very high values.

For example, a packet switch with 15 I / O ports with guaranteed maximum rates of 100 Mbps must have a central buffer memory that supports write and read rates of 1.5 Gbps.

We therefore quickly come up against very high bit rates at the level of the central buffer memory.

To solve this problem of very high bit rates, banks are used in the central buffer memory, the registers of which are written and read simultaneously in parallel.

The flow rates required at the banks of 70 registers are thus divided by their number of registers.

With banks of 32 registers with parallel writings and reads, the bit rates of 1.5 Gbits / s at the global level of the memory are reduced to 47 Mbits / s at the level of the banks of registers.

A solution to absorb the very high flow rates required at the level. memory therefore consists in playing on the number of parallel read and write registers of the banks of registers making up the central buffer memory.

However, this solution cannot be taken very far because it has drawbacks.

A first drawback is the complexity of the auxiliary circuits of the banks of registers necessary so that their 2o registers can be read and written in parallel, which increases with the number of registers served in parallel in writing and in reading.

A second drawback is the decrease in the rate of occupation of the memory registers by payload data due to the fact that the datagrams to be temporarily stored generally have a variable number of bits and rarely occupy an integer number of banks of registers so that one very often finds oneself, at the end of memorization of a datagram, with a last bank of registers partially occupied whose percentage of vacancy increases with the size.

Finally, the length of a bank of registers cannot be greater than that corresponding to half of the 3o minimum silence time separating two datagrams if we want to preserve a bank of registers encoding an absence of data between two datagrams. successive.

To allow absorption by the central buffer memory of the very large binary data rate required, it is proposed, not to increase CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 the number of registers of its banks but to design it in several independent modules operating in parallel.

The sequencer then allocates each time slot that it cuts in its clock signal to as many simultaneous memory accesses as there are 5 modules, these simultaneous memory accesses being allocated to distinct data traffic, the same port d 'input-output being able to have at most only two simultaneous accesses to two banks of different registers, one in write mode and the other in read mode.

The banks of registers in the buffer memory remain organized in as many separate groups as there are input-output ports, each of them being assigned to a specific input-output port for recording its traffic. incoming data.

But they are distributed, within each group, between the different modules.

The possibility of simultaneous memory access during the same time slot makes it possible, for the same apparent throughput of the memory, to lengthen the duration of a time slot in the ratio of the number of these simultaneous accesses and therefore to reduce in the same report the flow rate required at the level of a module.

As previously, the sequencer assigns, to each input / output port 2o, during separate time slots, a series of write access to the banks of registers of the group reserved for it and a series of read access to the banks of registers of a group that he can choose, always respecting an immutable scanning order within the groups.

But the banks of registers selected from write access to the next or from read access to the next may belong to different modules.

The modules are preferably of the same capacities and the banks of registers belonging to the same group equally distributed between the different modules.

This allows the sequencer to adopt, for the 3o different modules, identical sequencing between them at the level of the access allocations to the input-output ports and 'of the write or read mode but out of phase with each other to respect the constraint of' allocation to an input / output port, of at most two simultaneous accesses to the buffer memory, one in reading, the other in writing.

Indeed, thanks to the phase shift, it is possible to display different read or write modes and / or different input-output ports CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 26 for simultaneous access during the same time slot.

The determination of the number Nm of modules necessary, that is to say of the reduction ratio to accommodate the maximum throughput made possible by the technology used for the banks of registers while satisfying the requirements of the resulting write and read throughputs maximum guaranteed rates for binary data traffic entering and leaving the considered packet switch is done by seeking to satisfy the inequality N ",> _ 2 ~ N ~, + 1 ~ s Nn, being the number of modules, N ~, being the number of input-output ports of the considered packet switch, number which corresponds to the number of pairs of data traffic entering and leaving by the considered packet switch, T ~ i being the duration of the write access cycles and in reading in a bank of registers of the buffer memory imposed by the technology used, and TS being the period separating two accesses of the same nature (write or read) on behalf of the same input-output port at the level of the banks of registers of the buffer memory making it possible to satisfy the 2o data rates guaranteed for the data traffic entering and leaving the considered packet switch.

The duration TS is deduced from the minimum throughput required for the central memory to accommodate the maximum throughputs guaranteed for the data traffic crossing the packet switch considered.

If the data traffic entering and leaving the packet switch considered all have the same maximum guaranteed rate dm, the duration Ts is deduced from this maximum rate dm and from the number of registers B of the banks of the central buffer memory by the relation Ts - dm Figure 6 illustrates an example of write and read sequencing for a central buffer memory with two modules A and B of the same capacity operating in parallel, still in the context of a switch CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 27 of packets with seven input-output ports 0 to 6 each managing an incoming binary data traffic and a traffic of Outgoing binary data, all binary data traffic having the same guaranteed maximum rate. Using two modules allows each module to operate at half the rate of the overall buffer.

The sequencer cuts out, in its clock signal, successive time slots of sufficient duration for a write or read operation in a bank of registers of the modules.

As before, the banks of registers of the buffer memory are divided into seven distinct groups 0 to 6, as many as input-output ports, each of the groups being reserved for writing at a particular input-output port 0, 1 , 2, 3, 4, 5, 6 but these groups have their register banks distributed equally between the two modules A and B.

For example, having, as shown in FIG. 6, their banks of registers of which the address part relating to their order of scanning in writing, at the level of a group, is odd placed in the module A and their banks of registers of which the address part relating to their order of scanning in writing, at the level of a group, is even placed in the module B.

The notation adopted in this figure 6 for the addressing of the banks of registers is taken from figure 5 with a double identification by a first large number giving the group of membership of the bank of registers considered, that is to say the input-output port to which it is assigned in writing, and by a second small number giving its position in the group with respect to the immutable relative order adopted to scan the banks of registers of a group on writing or on reading.

With this type of central buffer memory structured in two modules A and B, each time slot cut out by the sequencer in its clock signal is assigned to two simultaneous accesses to the central buffer memory, one for the module A and the other for module B, each assigned to a predetermined input-output port for an operation of also predetermined type, write or read in a specific bank of registers of the buffer memory.

To comply with the constraint on the assignments of simultaneous accesses to the buffer memory which must always be assigned to different data traffic, the proposed sequencing assigns CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 28 systematically, to the during the same time slot, simultaneous access to the two modules A and B, to the same input / output port but one in write mode and the other in read mode, the write and read modes being exchanged periodically between the two modules A and B.

The sequencing begins with a series of time slots 0 to 6 assigned ~ for the module A, to successive write accesses WO-1, ..., W6-1 dedicated to each of the seven input-output ports 0 ,. .., 6, in the first bank of registers of each of the seven groups which are assigned to them individually for writing, these first banks of registers of the seven groups being assumed to have an odd address 1 within their groups and therefore to belong to module A , and ~ for module B, to successive read access RO-XOxo, ..., 86 X6Xs of module B register banks dedicated to each of the seven input / output ports 0, ..., 6.

During one of these time slots 0 to 7, the input-output port which has write access chooses a group Xi of banks of registers in which it wants to read, and, within this group Xi , a particular register bank xi whose address is assumed to be even within its group.

If this is not the case, it waits for a subsequent read access from module A.

The time slot numbered 7 is not assigned to the I / O ports but to the change of read write modes in the two modules A and B.

It does not lead to any operation on the buffer memory but prevents the time of inaccessibility of the memory during a change of read write modes within modules A and B from being charged to an I / O port access time. .

The sequencing continues with a series of time slots 8 to 14 assigned ~ for module A, to successive read accesses RO-XO ~~ o + 1>, ..., R6-X6 ~ Xs + 1> dedicated to each of the seven input-output ports.

The input-output port, which has read access, chooses a group Xi of banks of registers in which it wants to read, supposed to be the same as during its previous read access on module B, the datagram sought being assumed not entirely CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 29 recovered, and, within this group Xi, the register bank xi + 1 of odd address, which follows that of address xi pair, read previously in module B, ~ for module B, to successive write accesses WO-2, ...., W6-z dedicated to each of the seven input-output ports, in the second bank of registers of each of the seven groups which are individually assigned to them in writing, this second bank with an even address and located in module B.

The time slot 15 is not assigned to the input-output ports but to the change of read-write modes.

It plays a role analogous to the time slot 7.

For module A, the time slots 16 to 22 correspond to successive write accesses WO-3, ..., W6-3 dedicated to each of the seven input-output ports, in each of the seven groups reserved for them. individually in writing but this time in the third bank of registers of each group which, like the first, has an odd addressing.

For module B, the time slots 16 to 22 correspond to successive read accesses granted to each of the seven input output ports 0, ..., 6.

The input-output port, which has read access, chooses a 2o group Xi of banks of registers in which it wants to read.

This group Xi is supposed to be the same as during its previous read access on the module A, the sought datagram being supposed not entirely recovered, and, within this group Xi, the bank of registers xi + 2 of even address , which follows that xi + 1 with an odd address, read previously in the module A The time slot 23 is not assigned to the input-output ports but to the change of write-read modes.

It plays a role analogous to the time slots 7 and 15.

The following time slots 24 to 30 are again assigned, for module A, to successive read accesses RO-XO ~~ o + s>, ...

, R6-X6 ~~ s + a ~ dedicated to each of the seven input-output ports.

During one of these time slots 24 to 30, the input-output port which has write access chooses a group Xi of banks of registers in which it wants to read, supposed to always be the same as in its access previous reading, the sought datagram being assumed not to be fully recovered, and, within CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 of this group Xi, the register bank xi + 3 with an odd address, following that xi + 2 of even address, previously read in module B.

For module B, the time slots 24 to 30 are again assigned to successive write accesses WO-4, ..., W6-4 5 The time slot 31 is not assigned to the input ports. output but the change of read / write modes.

It plays a role analogous to the time slots 7, 15 and 23.

During the following time slots, the pairs of simultaneous access to modules A and B, one for writing, the other for reading in reading 1o dedicated to the input / output ports, follow each other regularly separated by time slots dedicated to write-read mode exchanges between the two modules A and B.

On each successive write access to the same input / output port, the register bank concerned within the group of register banks 15 reserved for writing at the input / output port considered changes module from module A to module B or conversely and progresses by one in the immutable order adopted for the write scan of the group in question so that after a certain delay, there is looping and overwriting of data previously written by new data , 20 the delay being that which is considered to be the maximum delay tolerated for the routing processing of a datagram by the packet switch considered.

On each read access to the same input / output port, the register bank concerned within the group of register banks explored changes module from module A to module B or vice versa and progresses by one unit. in the immutable order adopted for the write scan of the group concerned and this, until the input / output port carrying out the reading considers that it has recovered all of the sought datagram, this estimate being based on a priori knowledge of the length of the datagram appearing in service data included in the head of the datagram.

The grouping of several accesses to a module A or B, of the same type, write or read, makes it possible to minimize the frequency of changes of read write modes and vice versa which are CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 31 consumers of time and energy, which are the source of electromagnetic noise.

FIGS. 7 and respectively 8 illustrate examples of write and read sequencing for central buffers with three and respectively four modules of the same capacities operating in parallel, in the context of packet switches with twenty three and respectively thirty-one ports input-output each managing an incoming binary data traffic and an outgoing binary data traffic, all the 1st binary data traffic having the same maximum guaranteed rate.

The use of three modules makes it possible to operate each module at a third of the throughput of the global memory and the use of four modules at a quarter of the throughput of the global memory.

In cases of parallel use of more than two modules, it is no longer possible to comply with the constraint of assigning to the same input / output port at most two simultaneous accesses to the buffer memory, the one in writing and the other in reading by playing only on the write or read modes, which corresponded to using sequencing for the two identical modules from the point of view of the input-output ports and of the 2o write read modes but out of phase 180 degrees. It is necessary that some of the simultaneous accesses do not have the same allocation ports.

This can still be achieved by using for all modules the same sequencing in terms of I / O ports and read / write modes, but then they must be out of phase by the correct amount, 120 degrees for three modules and 90 degrees. degrees for four modules.

For the purpose of simplification, the accesses appearing in the sequencing proposed for four and three modules are no longer identified in FIGS. 7 and 8 by the assigned input / output port and the imposed write or read mode. It goes without saying that, as in FIGS. 5 and 6, 3o each access specifies not only the input / output port to which it is assigned and the write or read mode authorized but also a group of banks of registers and, within this group, a particular register bank determined both according to the same rules as previously.

For write operations, the group of register banks specified is the one reserved specifically for the allocation input-output port and the CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 32 registers selected in this group, the next to be entered following the invariant order of scanning of the banks of registers of the group concerned.

For read operations, the register bank group is specified by the allocation I / O port and the selected register bank within the group, the next to be read in the invariant scan bank order. registers of the group concerned, the allocation input-output port also specifying the address in the group concerned of the bank of registers starting a read campaign.

1o With the sequencing which has just been proposed, the regrouping of the successive time slots around the same write or read mode not only make it possible to limit the frequency of changes in operating modes for the memory modules but also to reduce the high-frequency address bus switching since they are also done while keeping, in write mode, a fraction of the addressing unchanged, that corresponding to the address of the banks of registers within the different groups.

This address fraction, which corresponds in a one-to-one way to the registration date, is by far the most important because there are many more banks of registers in a group than input-output ports.

The set of words written in the banks of registers of the central buffer memory corresponding to the same datagram constitutes a linear sequence of information.

This linear sequence of information is located within the group of banks of registers assigned specifically to the input-output port ensuring its reception at the level of the packet switch and is accessible from knowledge of the address, within this group, from the bank of registers storing the start word of the datagram. It is therefore possible to secure, within a packet switch, the use of the data of a datagram stored in its central buffer memory, by associating with the words which group them together in this central buffer memory, that is to say say at the level of each bank of registers of this central buffer memory, one or more error detection bits relating to the information content of the bank of registers considered and / or the address within the memory of the bank of registers considered.

These CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 33 error detection bits, which are advantageously determined by the securing method described in French patent application No. 2 723 222 filed by the company Sextant Avionics, make it possible to stop the transmission, through the network, of corrupted datagrams due to either ~ a failure of the central buffer memory of the considered packet switch (erroneous data read in a bank of registers), ~ a failure of the generation of address sequences 1o of banks of registers of the central buffer memory called by an input / output port during a sequence of successive read accesses to the central buffer memory ( succession of erroneous addresses), ~ a failure of a datagram allocation instruction ~ 5 (initial datagram reading address incorrect).

The presence of local error detection bits added at the level of each bank of registers of the central buffer memory of a packet switch but not retransmitted outside a packet switch, makes it possible to dissociate the malfunctions within the 20 packet switch itself, physical layer malfunctions linked to the implementation of the transmission signals carrying the datagrams on the physical transmission links used by the network outside its packet switches, the physical layer malfunctions being the subject elsewhere. specific monitoring, by means of error correction bits of the CRC type (acronym taken from the Anglo-Saxon "Cyclic Redundancy Code) or parity added to each datagram as soon as it is sent and the following throughout its routing through the network.

These error detection bits can be determined by an input-output port 30 when it prepares a word to be written into a register bank of the central buffer memory and written with the word considered when the sequencer grants it access. in writing to the central buffer memory, provided that the banks of registers of the central buffer memory are dimensioned accordingly, that is to say that they have a number of CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 34 registers adapted to the size of the word extended by the error detection bits.

Generally, this is the case of switched networks of the ethernet type, the datagrams are separated, in their routing on the same physical link of the network, by minimum time intervals making it possible to insert, as a preamble, in the transmission signal of each datagram, a service signal used by the demodulator arranged on the reception side to recover the modulation carrier used and 1o ensure the demodulation.

During these separation time intervals, inbound data traffic received by an I / O port continues to be stored in the central buffer while it is not carrying any data.

We then find ourselves with, in the central buffer memory, banks of registers containing data words belonging to datagrams and banks of registers containing meaningless data words called "gap words", corresponding to the time intervals of separation of successive datagrams received by the same input-output port. It is advantageous, to improve the security of the operation of a packet switch, to add, at the level of 2o each bank of registers of the central buffer memory, in addition to a field of error detection bits, a field of datagram presence identification bits called "datagram presence flag", updated from a signal of reception of a datagram generated by the input-output ports.

FIG. 9 shows a possible composition of a word stored in a bank of registers of the central buffer memory, depending on whether it belongs to a “data” datagram or to a separation time interval between two “no data” datagrams.

In this figure 9, the banks of registers of the central buffer memory 3o are supposed to have thirty six one-bit registers, thirty two (bits 0 to 31) constituting a field 100 reserved for the storage of a word of datagrams and four ( bits 32 to 35) constituting two fields 101 and 102 reserved for service information, one 101 containing two error detection bits SO and S1, the other 102 containing a datagram presence flag made up of two bits.

CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 When a register bank contains a word belonging to a datagram, as is the case of the register bank called "data", it contains the word belonging to a datagram. the datagram in its field 100 of thirty two bits, two error detection bits SO and S1 in its field 101, bits 5 whose values ​​are a function of that of the word stored in field 100 and possibly of the address of the register bank as taught in French patent application 2 723 222, and two datagram presence bits in its 102 field set to logical value 1.

When a register bank does not contain a word belonging to a datagram, as is the case with the register bank called "no data", it contains, in its field 100, thirty two bits of values ​​indifferent to l 'except for bits 30 and 31 forced to zero for convenience, in its field 101, two error detection bits S1 and S2 set arbitrarily to 0, and, in its field 102, two presence bits of ~ 5 datagram set to the logical value 0 signifying the absence of a datagram.

The values ​​of bits 0 to 29 of field 100, which are indifferent, are preferably taken to be equal to those previously present on the data bus.

This makes it possible to minimize the number of high frequency switchings affecting the data bus, which is advantageous for consumption and the reduction of parasitic noise.

To improve the security of the operation of the packet switch, it is proposed to give the routing automaton the ability to access the register banks of the central buffer memory, in competition with the input-output ports for it. make it possible to store, in the banks of registers not containing datagram words, information on datagram routing instructions that can be verified, for example by the transmission managers of the input / output ports.

3o To do this, we insert, in the sequencing of the accesses of the input / output ports to the buffer memory organized by the sequencer, one or more accesses reserved for the routing automaton, always taking care that the sequencing does not depend on than the time variable measured by the clock.

One way of doing this is to configure the sequencing of the accesses 35 of the input-output ports taking into account one or two virtual input-output ports CA 02437540 2003-08-05 WO 02/076002 PCT / FR02 / 00843 36 and to assign the reserved accesses to these virtual input / output ports to the routing automaton, the latter then determining at its convenience the address of the register bank in which it performs a read or write operation.

Advantageously, the routing machine uses its accesses to the buffer memory to add to each datagram being stored, an encapsulation label the size of a bank of registers, containing the diffusion profile of the datagram, that is, that is to say the various input-output ports of the packet switch through which the datagram 1o considered must be retransmitted and possibly the length of the datagram considered.

The storage of the broadcast profile makes it possible, when reading the associated datagram with a view to its transmission on a particular input-output port, to verify that this transmission operation indeed matches the expected broadcast profile. It avoids having to relate to the coding mechanism of the datagram (CRC or parity) the detection of a malfunction of the packet switch by a device placed downstream in the network.

The storage of the length of a datagram makes it possible to make it self-extracting if the encapsulation label is placed in a bank of 2o registers preceding the first word of the datagram.

Advantageously, the broadcast profile appearing in the encapsulation label can be dynamic, that is to say include flags assigned to each input-output port to indicate whether the associated datagram must be retransmitted by the port of input-output considered or not, activated by the routing automaton and deactivated by the transmission management circuits of the input-output ports.

This avoids the transmission of a datagram more than once through the same I / O port.

FIG. 10 shows a possible composition of an encapsulation label the size of a bank of thirty six one-bit registers, of which a 3o field 200 of twenty five bits reserved for the broadcasting profile makes it possible to manage twenty five communication ports. input-output in transmission, and an eleven-bit field 201 for the length of the datagram.

Such a label is particularly suitable for the encapsulation of ethernet frames the length of which between 64 and 1518 bytes is coded over 11 bits without using. the codes for the presence or absence of a datagram (field 102 in FIG. 9).