Longest coincidence data detection using associative memory units having interleaved data

CA 02239367 2000-07-21

LONGEST COINCIDENCE DATA DETECTION USING ASSOCIATIVE MEMORY UNITS HAVING INTERLEAVED DATA

The present invention relates to a longest coincidence data detection, and more particularly to an apparatus and method for detecting a longest coincidence data between an external data externally supplied and an internal data internally stored.

A longest coincidence data detecting apparatus compares an internal data internally stored with an external data externally supplied to detect the longest coincidence data between the internal data and the external data. The longest coincidence data detecting apparatus is conventionally composed of a single associative memory unit or a plurality of associative memory units which are connected in series. The comparison is performed to detect the longest coincidence data while the mask bits for the associative memory units in the whole apparatus are shifted one bit by one bit.

In this manner, in the conventional longest coincidence data detecting apparatus as mentioned above, it is necessary to perform the comparison while the mask bits for the associative memory units in the whole apparatus are shifted over all the bits. Therefore, the shifting operation and the comparing operation must be performed a number of times which is equal to the number of mask bits. In this manner, there is a problem in that the operation speed becomes slow.

In Japanese Laid-Open Patent Disclosure (JP-A-Showa 61 -162898), an associative memory apparatus is described which includes a data memory, a counter for counting an address of the data memory, and a mechanism for comparing a search data and an output of the data memory and for stopping the counter when the comparing result indicates matching. In this reference, the associative memory apparatus is composed of a search data memory for storing a plurality of search data, a selecting means for selecting a specific one of the plurality of search data stored in the search data memory, the mechanism for comparing a portion of the selected search data in a specific comparison region and a portion of a data read out from the data memory corresponding to the comparison region for the selected search data, and for stopping the counter when the comparing result indicates coincidence, and

CA 02239367 2000-07-21 another mechanism for restarting the counter from an address next to the stopped address.

The present invention is accomplished in view of the above problems in the conventional technique. Therefore, an object of the present invention is to provide an apparatus and method for detecting a longest coincidence data, in which a longest coincidence data can be detected at high speed.

According to an aspect of the present invention, a longest coincidence data detecting apparatus includes N M-bit associative memory units, wherein each of N and M is an integer greater than one, and a control section for distributing an external data to the N associative memory units to satisfy a relation of X_y = Y_Nj+i where 0 < i < N, 0 < j < M, i and j are integers, Xy is a j-th bit of the i-th one of the N associative memory units, and Y_k is a k-th bit of the external data. Here, each of the N associative memory units compares a distributed portion of the external data and a corresponding portion of an internal data in a designated bit region from a most significant bit of the distributed portion, and outputs a matching signal when the distributed portion of the external data portion and the corresponding portion of the internal data are coincident with each other in the designated bit region. The longest coincidence data detecting apparatus further includes a coincidence determination unit for generating a matching signal indicative of coincidence between the external data and the internal data in the designated bit region when the matching signals are received from the N associative memory units.

When the designated bit region is designated based on a mask bit data, the control section supplies to the N associative memory units the mask bit data which indicates the designated bit region narrowed by one bit from a least significant bit of the distributed portion of the external data each time a shift signal is inputted. In this case, all bits of an initial data of the mask bit data is 1 , and each bit of the initial data of the mask bit data is changed to 0 from a least significant bit each time the shift signal is inputted, and the designated bit region is designated based on the bits of 1 of the mask bit data. Also, the longest coincidence data detecting apparatus may further include a bit count outputting section for outputting a data indicative of a number of bits for which the external data and the internal data are not coincident with each other from a least significant bit of the external data, from a number of times of

CA 02239367 2000-07-21 the input of the shift signal and the matching signals from the N associative memory units.

The longest coincidence data detecting apparatus may further include a bit count outputting section for outputting a data indicative of a number of bits for which the external data and the internal data are not coincident with each other from a least significant bit of the external data, from the designated bit region. In this case, when the N associative memory units comprises first and second associative memory units, the bit count outputting section includes a counter for counting a number of times of input of a shift signal to produce a count data, the shift signal being used to determine the designated bit region, a flip-flop for outputting an output state data indicative of whether the matching signal is already outputted from the first associative memory unit, and a subtracting unit for subtracting the output state data from a data derived from the count data to output a matching bit count data indicative of the number of bits for which the external data and the internal data are coincident with each other from the least significant bit.

In order to achieve another aspect of the present invention, a method of detecting a longest coincidence data, comprising the steps of:

distributing an external data to N M-bit associative memory units to satisfy a relation of X,j = Y_Nj+i where each of N and M is an integer greater than one, 0 < i < N, 0 j < M, i and j are integers, Xy is a j-th bit of the i-th one of the N associative memory units, and Y_k is a k-th bit of the external data;

comparing a distributed portion of the external data and a corresponding portion of an internal data in a designated bit region from a most significant bit of the distributed portion;

generating a matching signal from each of the N associative memory units when the distributed portion of the external data portion and the corresponding portion of the internal data are coincident with each other in the designated bit region; and a coincidence determination unit for generating a matching signal indicative of coincidence between the external data and the internal data in the designated bit region when the matching signals are received from the N associative memory units.

CA 02239367 2000-07-21

In orderto achieve still another aspect of the present invention, a longest coincidence data detecting apparatus includes a plurality of associative memory units, each of which compares a portion of an external data and a corresponding portion of an internal data in accordance with a mask bit data, and outputs a matching signal when the external data portion and the corresponding portion of the internal data are coincident with each other in the region designated by the mask bit data, a control section for respectively supplying the portions of the external data to the plurality of associative memory units in response to a start signal, for shifting a designation data by one bit from a least significant bit to produce a shifted designation data each time a shift signal is inputted, and for outputting, as the mask bit data to all of the plurality of associative memory units, the designation data when no shift signal is inputted, and the shifted designation data when the shift signal is inputted, and a coincidence determination unit for generating a matching signal indicative of coincidence between the external data and the internal data in portion when the matching signals are received from the plurality of associative memory units.

The present invention will be further understood from the following description with reference to the drawings in which:

Figure 1 is a circuit block diagram illustrating the longest coincidence data detecting apparatus according to an embodiment of the present invention;

Figure 2 is a diagram illustrating the distribution of an external data to associative memory units in the longest coincidence data detecting apparatus according to the embodiment of the present invention;

Figure 3 is a diagram illustrating an example of the external data and distribution of the external data in the longest coincidence data detecting apparatus according to the embodiment of the present invention;

Figure 4 is a diagram illustrating an example of the internal data and the external expression of the internal data in the longest coincidence data detecting apparatus according to the embodiment of the present invention;

Figure 5 is a diagram illustrating the changing state of a mask bit data in the longest coincidence data detecting apparatus according to the embodiment of the present invention;

CA 02239367 2000-07-21

Figures 6A to 6H are timing charts to describe the operation of the longest coincidence data detecting apparatus according to the embodiment of the present invention;

Figure 7 is a circuit block diagram illustrating the longest coincidence data detecting apparatus in accordance to a second embodiment of the present invention;

Figure 8 is a diagram illustrating the truth table of the encoder 7;and

Figure 9 is a timing chart to describe the operation of the longest coincidence data detecting apparatus according to the second embodiment.

Referring to Figure 1 which illustrates the structure of the longest coincidence data detecting apparatus according to an embodiment of the present invention in this embodiment, two associative memory units are provided.

As shown in Figure 1, the longest coincidence data detecting apparatus in the embodiment is composed of control circuits 1a and 1b, associative memory units (CAMs) 2a and 2b, an AND gate 3, a counter 4, a D-type flip-flop (DQ) 5, and a subtracting unit 6.

The control circuits 1 a and 1 b receive two portions of 8 bits of a 16-bit external data and the two portions of 8 bits are supplied to the associative memory units 2a and 2b in response to a START signal, respectively. Also, the control circuits 1 a and 1 b each has mask bit data and shifts the mask bit data one bit by one bit from the least significant bit to the most significant bit in response to a SHIFT signal. The shifted mask bit data are supplied to the associative memory units 2a and 2b, respectively. In this manner, the same mask bit data is supplied to the associative memory units 2a and 2b.

Each of the associative memory units 2a and 2b receives a portion of the external data outputted from a corresponding one of the control circuits 1 a and 1 b. Then, the associative memory unit compares the received portion of the external data and the portion of an internal data stored therein based on the mask bit data supplied from the control circuit. The associative memory unit 2a or 2b outputs a matching signal MATCH1 or MATCH0, when the received portion of the external data and the portion of the internal data are coincident with or match each other.

CA 02239367 2000-07-21

The AND gate 3 calculates a logic product of the matching signals outputted from the associative memory units 2a and 2b to output the calculation result as a MATCH signal. That is, the AND gate 3 outputs the MATCH signal indicating that the external data and the internal data are coincident within a region designated by the mask bit data.

The counter 4 is reset in response to the START signal and counts the number of times of input of the SHIFT signal. The D-type flip-flop 5 is reset in response to the START signal. The D-type flip-flop 5 receives the SHIFT signal as a clock signal, and outputs the MATCH1 signal supplied from the associative memory unit 2a in response to the clock signal. The subtracting unit 6 subtracts the data which is outputted from the D-type flip-flop 5 from a data corresponding to the count value supplied from the counter 4 to output the subtracting result as a MASKBITS signal.

Next, the operation of the longest coincidence data detecting apparatus according to the embodiment of the present invention will be explained.

As shown in Figure 2, two 8-bit data of the 16-bit external data shown in Figure 3 are supplied to the control circuits 1a and 1b, respectively. Now, it is assumed that Y_k is the k-th bit of the external data. Also, it is assumed that X_oj is the j-th bit of the first 8-bit data which is inputted to the control circuit 1a, and X_1; is the j-th bit of the second 8-bit data which is inputted to the control circuit 1 b. In this case, the relation

X^Y^i (0i i < 2, 0 j < 8) is satisfied. Therefore, the first bit data of 01010010 and the second bit data of 10110101 are held in the control circuits 1a and 1b.

The two 8-bit data are supplied from the control circuits 1 a and 1 b to the associative memory units 2a and 2b in response to the START signal, respectively, as shown in Figure 6A. Also, a mask bit data is set to 11111111 in response to the START signal, as shown in Figure 5. Then, the same mask bit data is also supplied from the control circuits 1a and 1b to the associative memory units, respectively in response to the START signal.

The data bit of the mask bit data corresponding to 1 indicates that the comparison between the external data and the internal data should be performed in a bit position corresponding to the mask bit of 1. On the other hand, the data bit of

CA 02239367 2000-07-21 the mask bit corresponding to 0 indicates that the comparison between the external data and the internal data should not be performed in a bit position corresponding to the mask bit of 0. For instance, in the embodiment, the mask bit data of 1111111 Τ' means that all the bits of the 8-bit external data portion are compared with all the bits of the 8-bit internal data portion. On the other hand, the mask bit data of 11111110” means that all the bits of the 8-bit external data portion other than the least significant bit are compared with all the bits of the 8-bit internal data portion other than the least significant bit.

Further, when the START signal is externally inputted, the counter4 and the D-type flip-flop 5 are cleared to 0.

In the associative memory unit 2a, all the bits of the 8-bit external data portion of 01010010 shown in Figure 3 are respectively compared with all the bits of the 8-bit internal data portion of 01010000 shown in Figure 4. This is because the mask bit data is set to 1111111 Τ' in this case. Also, in the associative memory unit 2b, all the bits of the 8-bit external data portion of 10110101 shown in Figure 3 are respectively compared with all the bits of the 8-bit internal data portion of 10110000 shown in Figure 4. This is also because the mask bit data is set to 11111111 in this case. It should be noted that the external expression of the internal data is ”0110 0111 0000 0000 shown in Figure 4. At this time, the external data and the stored data are not coincident with each other in the associative memory units 2a and 2b. Therefore, the matching signals MATCH0 and MATCH1 are both 0. As a result of that, the MATCH signal which is the logic product of them also becomes 0.

Next, a SHIFT signal of 1 is supplied to the control circuits 1a and 1b and the counter 4 and the D-type flip-flop, as shown in Figure 6B. The mask bit data are shifted by one bit into the direction of the most significant bit in the control circuits 1a and 1b and 0 is added to the shifted mask bit data in the least significant bit. As a result, a new mask bit data is set to 11111110. Thus, the comparison bit region can be designated by the mask bit data.

This mask bit data is supplied to the associative memory units 2a and 2b, and the comparison is performed so as to ignore the least significant bit. At the same time, the counter 4 is counted up by 1 so that 1 is output from the counter 4, as shown in Figure 6F. At this state, either of the MATCH0 signal or the MATCH1

CA 02239367 2000-07-21 signal is 0 as shown in Figures 6C and 6D and therefore the MATCH signal is still 0 as shown in Figure 6E.

Next, when the SHIFT signal becomes 1 again, the mask bit data for the associative memory units 2a and 2b are set to 11111100, as shown in Figure 5. As a result, the comparison is performed while the lower 2 bits are ignored.

At the same time, since the external data portion is coincident with or matches the internal data portion in the associative memory unit 2a, the MATCH1 signal of 1 is outputted from the associative memory unit 2a. On the other hand, since the coincidence is not yet accomplished in the associative memory unit 2b, the MATCH0 signal of 0 is outputted from the associative memory unit 2b to the AND gate 3 and the D-type flip-flop 5, as shown in Figure 6G. Also, the counter 4 is counted up to output 2”, as shown in Figure 6F. In this case, because the MATCH0 signal is 0, the MATCH signal is also 0. However, the MATCH1 signal of 1” is supplied to the D-type flip-flop 5.

Next, when the SHIFT signal becomes 1 again, the mask bit data of the control circuits 1 a and 1 b are set to 11111000, as described above. As a result, the comparison is performed while the lower 3 bits are ignored.

At the same time, the counter 4 is counted up by 1 to output 3, as shown in Figure 6F. Also, since the external data portion and the internal data portion are coincident with each other in the associative memory units 2b when the lower 3 bits are ignored, the MATCH0 signal is set to 1 as shown in Figure 6C. As a result, the logical product of the MATCH0 signal and the MATCH1 signal is set to 1 as the MATCH signal as shown in Figure 6E.

In this case, since the MATCH1 signal is already set to 1, the output of the flip-flop 5 is set to 1 in response to the SHIFT signal, as shown in Figure 6E. The output of 3 from the counter 4 is supplied to the subtracting unit 6. At this time, ”0 is applied to the binary expression of the count value of the counter 4 as the least significant bit, i.e., 110 is obtained. Therefore, the subtracting unit 6 subtracts the data of 1 supplied from the D-type flip-flop 5 from the binary expression of 110. As a result of 101, that is 5 is obtained. This value is outputted as the MASKBITS signal.

CA 02239367 2000-07-21

In the above-mentioned state, the output of the counter 4 is 3. Therefore, the least significant bit of 0 is added to the binary expression of the output of the counter 4, so that the output of the counter 4 is set to 6, i.e., 110. At this time, because the output of the D-type flip-flop 5 is 1, the MASKBITS signal is set to 5 as shown in Figure 6H. This means that the lower 5 bits from the least significant bit must be ignored to make the external data and the external expression of the internal data portions to be coincident with each other.

In this manner, a circuit section composed of the counter 4, the flip-flop 5 and the subtracting unit 6 functions to detect the number of bits of the noncoincident portion between the external data and the internal data. In this case, the circuit section may output the number of bit of coincident portion between the external data and the internal data.

As described above, according to the present invention, an external data of L bits and an internal data of L bits are compared to detect the longest coincidence data between the external data and the internal data. In this case, N M-bit associative memory units are provided to satisfy a relation of

X|j ~ ^Nj+i where O < i < N, 0 s j < M, the data, Χ_ι; is a data given to the bit j of the i-th associative memory means, and Y_k is the k-th bit of the external data. Therefore, it is sufficient to perform the shifting operation and comparing operation m times for detection of a longest coincidence data of L bits. In this manner, the longest coincidence data detection can be performed at higher speed, compared with a conventional example in which it is necessary to perform the shifting operation and comparing operation L times at maximum.

Also, there is provided a counter for counting a SHIFT signal externally inputted, a flip-flop for outputting a signal outputted from associative memory means using the SHIFT signal as a clock signal, and a subtracting unit for subtracting and outputting a signal outputted from the flip-flop from the count value by the counter. In this case, in order to make the external data and the external expression of the stored data coincident with each other, it is indicated the external data and the stored data must be compared by ignoring how many bits from the least significant bit.

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With respect to Figures 7 to 9, a second embodiment will now be described in which N = 4. The circuit illustrated in Figure 6 is very similar to the circuit illustrated in Figure 1. Figure 7, however, illustrates four control circuits 1a to 1 d, four associate memory units (CAMs) 2a to 2d with corresponding matching signals MATCH3 TO MATCH0 respectively. Encoder 7 receives matching signals MATCH3 to MATCH 1 and sends signal Y to D-type flip-flop 5 in accordance with the Truth Table of Figure 8. The output from counter 4 is multiplied by 4 at multiplier 8. The output of D-type flip-flop 5 is then subtracted from the output of multiplier 8 at subtracter 6. The results of this subtraction operation are shown in Figure 9 in the last row labelled MASKBITS. In particular, with respect to Figure 9, the relationship among the output of counter 4, D-type flip-flop 5 and the output of subtracter 6 (MASKBITS) is illustrated (i.e. MASKBITS = (4 x COUNTER_OUTPUT) - D-FF_OUTPUT).

Using the same data as in the previous example (see Figures 3, 4 and 5), external data (0110011100011001) to CAM2a to CAM2d, respectively, are 0001,1100,1100 and 0111 ; and storage data (0110011100000000)to CAM2a to CAM2d, respectively, are 0000,1100,1100 and 0100. Following the same steps as generally described with respect to the first embodiment, when the counter is 0, the mask is 1111 and MATCH3 = MATCH0 = 0, MATCH2 = MATCH 1 = 1, with the result that MATCH=0. Continuing, the counter is incremented to 1, the mask is now set to 1110 and Figure 9 now indicates that MATCH is still 0 (MATCH0 = 0, MATCH1 = MATCH2 = MATCH3 =1). The counter is next incremented to 2 and the mask is set to 1100 and Figure 9 now indicates that MATCH = 1 since MATCH0 = MATCH 1 = MATCH2 = MATCH3 =1 and accordingly, a longest coincidence has been determined. In particular, (4 x COUNTER OUTPUT) - D-FF OUTPUT) = 5, hence the lowest 5 bits should be disregarded and the most significant 11 bits of the external data are coincident with the most significant 11 bits of the storage data. This is confirmed by directly comparing the external data with the storage data.