Multiple level minimum logic network
Abstract
A network or interconnect structure utilizes a data flow technique that is based on timing and positioning of messages communicating through the interconnect structure. Switching control is distributed throughout multiple nodes in the structure so that a supervisory controller providing a global control function and complex logic structures are avoided. The interconnect structure operates as a "deflection" or "hot potato" system in which processing and storage overhead at each node is minimized. Elimination of a global controller and buffering at the nodes greatly reduces the amount of control and logic structures in the interconnect structure, simplifying overall control components and network interconnect components and improving speed performance of message communication.
Term
Term ended
Expired 19 July 2016, 10.2 years ago.
- Priority
- Filed
- Granted
- Expired
- Today
2 claims: 2 independent, 0 dependent
- 1CA 02227271 2002-02-22 70128-353 CLAIMS :1. A method of transmitting a message from a node N to a target destination in a first, a second and a third dimension of three dimensions in an interconnect structure arranged as a plurality of nodes in a topology of the three dimensions, the method comprising: determining whether a node en route to the target destination in the second and third dimensions and advancing one level toward the destination level of the first dimension is blocked by another message;advancing the message one level toward the destination level of the first dimension when the en route node is not blocked;moving the message in the second and third dimensions along a constant level in the first dimension otherwise;specifying the first dimension to describe a plurality of levels, the second dimension to describe a plurality of nodes spanning a cross-section of a level, and the third dimension to describe a plurality of nodes in the cross-section of a level;sending a control signal from a node on the level of the en route node to the node N in the first dimension, the control signal specifying whether the node en route is blocked;timing transmission of a message using a global clock specifying timing intervals to keep integral time modulus the number of nodes in a cross-section of a level;CA 02227271 2002-02-22 70128-353 Λ setting a first time interval a for moving the message in the second and third dimensions;setting a second time interval a - β for advancing the message one level toward the destination level, the global clock specifying a global time interval equal to the second time interval, the first time interval being smaller than the global time interval;and setting a third time interval for sending the control signal from the node on the level of the en route node to the node N, the third time interval being equal to β. 2. A method according to Claim 1, further comprising: timing the message moving and advancing steps so that the messages enter node N on level q at times having the form na + ςβ;and timing the control signal sending step so that the control signals enter node N on level q at times having the form na + ςβ so long as the node en route is not blocked. 3. A method according to Claim 1, further comprising: timing transmission of a message using a global clock;setting a first time interval for moving the message in the second and third dimensions;setting a second time interval for advancing the message one level toward the destination level in the first dimension;CA 02227271 2002-02-22 70128-353 specifying the first dimension to describe a plurality of levels, the second dimension to describe a plurality of nodes spanning a cross-section of a level, and the third dimension to describe a plurality of nodes in the cross-section of a level;specifying timing interval of the global clock to keep integral time modulus the number of nodes in a crosssection of a level, the global clock time interval being equal to the second time interval and the first time interval being smaller than the global time interval. 4. A method according to Claim 1 further comprising: defining a header and a payload in the message;encoding the destination in the second dimension in the header;determining whether a potentially en route node is en route to the target destination including the steps of: comparing the encoded destination in the second dimension to an encoded position of the potentially en route node in a single-bit comparison of the level-specific, single-bit destination code and the single-bit position code;resolving that the potentially en route node is en route when the encoded destination is the same as the encoded position of the potentially en route node, encoding the destination in the third dimension in the header in a plurality of single-bit codes, the singlebit codes relating to a level of the third dimension;CA 02227271 2002-02-22 70128-353 encoding the position of the potentially en route node in a single-bit code;and discarding the level-specific, single-bit destination code in the header as the message advances one level. 5. A method according to Claim 1 further comprising: on a level T of the first dimension, spanning one ring in 2T passes through the nodes in the second dimension so that 2T nodes in the third dimension designate one ring;and interconnecting the three dimensional interconnect structure so that advancing of levels from a start level to the destination level of the first dimension furnishes access to all nodes in a ring. 6. A method according to Claim 1 wherein a message injected into the interconnect structure at a node N(J, ql, zl) and targeted to exit the interconnect structure at a node N(0, q2, z2) and injected at a time (q2 - ql)modK * a + J causes the message to arrive at node N(0, q2, z2) at time 0. 7. A communication interconnect structure for transmitting messages, comprising: a plurality of nodes arranged in a structure including: a hierarchy of levels from a source level to a destination level;a plurality of nodes spanning a cross-section of a level;and CA 02227271 2002-02-22 70128-353 a plurality of nodes in a cross-section span, the level of a node being determined entirely by the position of the node in the structure;a plurality of interconnect lines coupling the nodes in the structure including for a node N on a level L: a message input interconnect line coupled to a node on a previous level L+l;a message input interconnect line coupled to a node on the level L;a message output interconnect line coupled to a node on the level L;a message output interconnect line coupled to a node X on a subsequent level L-l;a control input interconnect line coupled to the message output interconnect line of a node distinct from the node X on the level L-l;and a switch coupled to receive a message on the control input interconnect line and, in accordance with the message, to selectively transmit a message without buffering on the message output interconnect line coupled to the subsequent level L-l node or on the message output interconnect line coupled to the level L. 8. An interconnect structure according to Claim 7, further comprising: a control output interconnect line coupled to a control input terminal of the node on the previous level L+l;CA 02227271 2002-02-22 70128-353 a switch for determining that a message is blocking the node N and communicating via the control input interconnect line informing whether the node N is blocked;a global clock generating timing signals, the timing signals in discrete time steps of an integral time modulus the number of nodes on a level timing a message transmission time of a message transmitted from a level to a subsequent level and for timing a control signal transmission time of a control signal from a subsequent level to a level so that the control signal arrives first at a node;a control output interconnect line coupled to a control input terminal of the node on the previous level L+l;and a switch for determining that a message is blocking the node N and communicating via the control input interconnect line informing whether the node N is blocked. 9. A method of communicating messages in an interconnect structure comprising: arranging a plurality of nodes in a structure including a plurality of hierarchical levels from a source level to a destination level, the level of a node being determined entirely by the position of the node in the structure, a plurality of nodes spanning a cross-section of a level and a plurality of nodes in a cross-section span, the nodes having an input connection on the same level, an input connection on a previous level, an output connection on the same level and an output connection on a subsequent level;CA 02227271 2002-02-22 70128-353 specifying a destination node in the destination level for receiving a message;originating the message at a node in the source level;communicating a message from node to node including: determining at a node whether a node X on a subsequent level is directed toward the destination node;determining at a node whether the node on the subsequent level is blocked by another message, the determination being based on a control signal from a node distinct from the node X;advancing the message to the node on the subsequent level when the node is directed toward the destination node and a node is unblocked;and otherwise traversing the message to a node on the same level. 10. A method according to Claim 9 wherein determining whether a node on a subsequent level is directed toward the destination node further comprises: encoding the destination node in a message in the header field;encoding a designation of node position for the nodes at the levels;and determining that the node on the subsequent level is directed toward the destination node when the destination CA 02227271 2002-02-22 70128-353 node encoding and the node position designation encoding correspond. 11. A communication interconnect structure comprising: a plurality of nodes;and a plurality of interconnect lines coupling the nodes, a node X of the plurality of nodes having: a message input interconnect line coupled to a node A distinct from the node X;and a message input interconnect line coupled to a node B distinct from the node A and the node X, the node X accepting a message input from the node A and a message input from the node B with a control· interconnect line being coupled between the node A and the node B for communicating a control signal determining a priority relationship between conflicting messages, the control signal enforcing the priority relationship between the sending of a message from the node A to the node X and the sending of a message from the node B to the node X. 12. An interconnect apparatus, comprising: a plurality of nodes;and a plurality of interconnect lines in an interconnect structure selectively coupling the nodes in a hierarchical multiple level structure arranged to include: a plurality of J+l levels in an hierarchy of levels arranged from a lowest destination level Lq to a highest level Lj which is farthest from the lowest destination level Lg# the level of a node being determined CA 02227271 2002-02-22 7Q128-353 entirely by the position of the node in the structure, the interconnect structure transmitting a message M in a plurality of discrete time steps, the message M moving in a time step and the interconnect structure having interconnections to move the message M in one of three ways in the time step including: the message M enters a node in the interconnect structure from a device external to the interconnect structure;the message M exits the interconnect structure to a designated output buffer;and the message M either moves from a node U on a level Ljc to a different node V on the same level Ljç or moves from the node U to a node W on a level where k is greater than i so that the level Li is closer to the destination level Lq than the level L^, and the node U uses a control signal from a source distinct from the node V and the node W to determine where to send the message M. 13. An interconnect apparatus according to Claim 12, wherein the interconnect structure is self-routing. 14. An interconnect apparatus according to Claim 12, wherein a node on the level L^ has a plurality of interconnections including: a direct data input interconnection from a node on the level L^;a direct data output interconnection to a node on the level L^;CA 02227271 2002-02-22 70128-353 a direct data input interconnection from a node Ncm on the level Lm where m is greater than k so that the level Lm is farther from the destination level Lg than the level L^;and a direct data output interconnection to either a device Dg external to the interconnect structure or a node Ngj_ on the level Lj_ where k is greater than i so that the level is closer to the destination level Lg than the level L^. 15. An interconnect apparatus according to Claim 12, wherein a node on the level has a plurality of interconnections including : a direct data input interconnection from a node Νβ]ζ on the level L^;a direct data output interconnection to a node on the level L^;a direct data input interconnection from a device Dq external to the interconnect structure;and a direct data output interconnection to either a device Dg external to the interconnect structure or a node Ngj_ on the level Lj_ where k is greater than i so that the level Lj_ is closer to the destination level Lg than the level Lfc. 16. An interconnect apparatus according to Claim 12, wherein : CA 02227271 2002-02-22 70128-353 the plurality of nodes are arranged into a plurality of node groups in which all of the nodes of a given group Gm are on the same level and each node of the plurality of nodes is included in only one group of the plurality of groups;and a node N^ in the group Gm on the level has a plurality of interconnections including: a direct data input interconnection from a node in the group Gm on the level L^;and a direct data output interconnection to a node Ng^ in the group Gm on the level L^. 17. An interconnect apparatus according to Claim 12, wherein: the plurality of nodes are arranged into a plurality of mutually exclusive node groups including a group Gg and a group Gy in which all of the nodes of the group G(j are on the same level and all of the nodes of the group Gy are on the same level Lf;and if a node Np of the group Gg has an interconnect path for sending a message to a node Nq of the group Gy, then all nodes of the group Gg have interconnect paths for sending a message to a node of the group Gy. 18. An interconnect apparatus according to Claim 12, wherein: the plurality of nodes are arranged into a plurality of mutually exclusive node groups including a group Gg and a group Gy in which all of the nodes of the CA 02227271 2002-02-22 70128-353 group Gy are on the same level and all of the nodes of the group Gy are on the same level L^;and if an interconnect path exists for sending a message from a node of the group Gg to a node of the group Gy, and the group Gg includes a node Np and the group Gy includes a node Ng, then the interconnect structure includes an interconnect path for sending a message from the node Np to the node Ng. 19. An interconnect apparatus according to Claim 12, wherein: the plurality of nodes are arranged into a plurality of mutually exclusive node groups including a group Gy and a group Gy in which all of the nodes of the group Gg are on the same level and all of the nodes of the group Gy are on the same level L^;and if one node in the group Gg has an interconnect path for sending a message to a node in the group Gy, then all nodes in the group Gg have interconnect paths for sending messages to a node in the group Gy. 20. An interconnect apparatus according to Claim 12, wherein: a node Ng has a direct input interconnection from a node N^ in the interconnect structure and a direct input interconnection from a device G external to the interconnect structure;and the direct input interconnection from the node N^ has precedence over the direct input interconnection from CA 02227271 2002-02-22 70128-353 the external device G so that every message directed from the node N^ to the node Nq successfully moves from the node N^ to the node Nq. 21. An interconnect apparatus according to Claim 12, wherein: a node Νβ on the level Lj_ has a direct input interconnection from a node N^ also on the level Lj_ and a direct input interconnection from a node Ng on the level L^;and the direct input interconnection from the node N^ has precedence over the direct input interconnection from the node Ng so that every message directed from the node to the node Nq successfully moves from the node N^ to the node Nq. 22. An interconnect apparatus according to Claim 12, wherein the interconnect structure: carries messages and control signals;and includes a node N^ including: a direct message input interconnection for receiving a message having a header;a direct control input interconnection for receiving a control signal C&;a plurality of direct message output interconnections to a respective plurality of subsequent nodes for directing the message and CA 02227271 2002-02-22 70128-353 a control logic responsive to the control signal CA and the header of the message MA for determining a node of the plurality of subsequent nodes to direct the message MA. 23. An interconnect apparatus according to Claim 12, wherein the interconnect structure: carries messages and control signals;includes a node Np including: a direct message input interconnection for receiving a message Mg from a device G external to the interconnect structure;and a direct message input interconnection for receiving a message MA from a node NA;and the node NA has a control logic setting a precedence of the direct message input interconnection from the node NA to the node Np over the direct message input interconnection from the device G to the node Np so that, in a discrete time step, if the device G holds the message Mg for entry to the interconnect structure to the node Np and the node NA has the message MA directed to the node Np, then, in the discrete time step, the message MA is successfully sent from the node NA to the node Np and the message Mg is blocked from transmission to the node Np. 24. An interconnect apparatus according to Claim 12, wherein the interconnect structure: carries messages and control signals;CA 02227271 2002-02-22 70128-353 includes a node Np including: a direct message input interconnection for receiving a message Mg from a device G external to the interconnect structure;and a direct message input interconnection for receiving a message MA from a node NA;and the device G has a control logic and direct control input interconnection coupled to the control logic for receiving a control signal Cg from the node NA, the control signal Cg enforcing a precedence of the direct message input interconnection from the node NA to the node Np over the direct message input interconnection from the device G to the node Np so that, in a discrete time step, if the device G holds the message Mg for entry to the interconnect structure to the node Np and the node NA has the message MA directed to the node Np, then, in the discrete time step, the message MA is successfully sent from node na to node Np and the control logic receives the control signal Cg designating a blocking condition and, responsive to the control signal Cg blocking condition, the control logic blocks transmission of the message Mg to the node Np. 25. An interconnect apparatus according to Claim 12, wherein the interconnect structure : carries messages and control signals;includes a node Np including: CA 02227271 2002-02-22 70128-353 f a direct message input interconnection for receiving a message Mg from a device G external to the interconnect structure;and a direct message input interconnection for receiving a message M^ from a node N^;and the device G has a control logic and direct control input interconnection coupled to the control logic for receiving a control signal Cg from the node N^, the control signal Cg enforcing a precedence of the direct message input interconnection from the node to the node Ng over the direct message input interconnection from the device G to the node Nq so that, in a discrete time step, if the device G holds the message Mg for entry to the interconnect structure to the node Nd and the node Nj\ has no message directed to the node Nd, then, in the discrete time step, the control logic does not receive the control signal Cg designating a blocking condition and, responsive to the absence of the control signal Cg blocking condition, the control logic transmits the message Mg to the node Nd, wherein in the discrete time step: the node N^ is idle, or the node includes a control logic that: (1) directs the message M^ to a node Ng distinct from the node Nq;and (2) sends the control signal Cg designating the absence of the blocking condition. CA 02227271 2002-02-22 70128-353 26. An interconnect apparatus according to Claim 12, wherein the interconnect structure: carries messages and control signals;includes a node Np including: a direct message input interconnection for receiving a message M^ from a node N^;and a direct message input interconnection for receiving a message Mp from a node Np;and the node N^ has a control logic and a direct control input interconnection for receiving a control signal C^ from the node Np, the control signal C^ enforcing a precedence of the direct message input interconnection from the node Np to the node Np over the direct message input interconnection from the node N^ to the node Np so that, in a discrete time step, if the message is present at the node N^ and the node Np has the message Mp directed to the node Np, then, in the discrete time step, the message Mp is successfully sent from node Np to node Np and the control logic receives the control signal designating a blocking condition and, responsive to the control signal C^ blocking condition, the control logic blocks transmission of the message M^ to the node Np and directs the message to a node Np distinct from the node Np. 27. An interconnect apparatus according to Claim 12, wherein the interconnect structure: carries messages and control signals;CA 02227271 2002-02-22 7Q128-353 includes a node Ng including: a direct message input interconnection for receiving a message M^ from a node N^, the message M^ having a header;and a direct message input interconnection for receiving a message Mp from a node Np;and the node N^ has a control logic and a direct control input interconnection for receiving a control signal C^ from the node Np, the control signal enforcing a precedence of the direct message input interconnection from the node Np to the node Np over the direct message input interconnection from the node N^ to the node Np so that, in a discrete time step, if the message is present at the node N^ and the node Np has no message Mp directed to the node Np, then, in the discrete time step, the control logic does not receive the control signal designating a blocking condition and, responsive to the absence of the control signal blocking condition, the control logic uses the header of the message Mj\ to determine a preferred device for transmitting the message M^ and if the preferred device is the node Np, then the message M^ is sent to the node Np. 28. An interconnect apparatus according to Claim 27, wherein: in the discrete time step the node Np is idle. 29. An interconnect apparatus according to Claim 27, wherein: CA 02227271 2002-02-22 70128-353 in the discrete time step the node Np includes a control logic that: (1) directs the message Mp to a device distinct from the node Np;and (2) sends the control signal designating the absence of the blocking condition. 30. An interconnect apparatus according to Claim 27, wherein: a message Mp is present at the node Np, the message Mp having a header designating one or more target output buffers;if the node Np has an interconnect path to a node of the plurality of nodes N connected to a target output buffer designated by the message Mp, then the control logic of the node N^ directs the message to the node Np;and otherwise the control logic of the node N^ directs the message M^ to a node Np on the level Ιψ. 31. An interconnect apparatus according to Claim 12, further comprising : a node N^ on the level having a direct data output interconnection to a node Np on the level L-[, the node Np having an interconnect path to a node Np that is connected to an output buffer wherein: if a message M^ is present at the node N& and has a header designating the output buffer as a target output CA 02227271 2002-02-22 70128-353 buffer, and the message MA is not blocked from transmission to the node Ng;then a message Mg that is directed to the node Ng is sent directly to the node Ng;and otherwise the message is sent directly to a node Ng on the level L^. 32. An interconnect apparatus according to Claim 12, further comprising : a node N^ on the level L^, the node including a control logic that utilizes a header information of a message present at the node Njx to ascertain: whether a direct interconnect exists from the node Njx to a node belonging to a group Gy at the level Lj_ such that an interconnect path exists from a node in the group Gy to a node Νβ that is connected to an output buffer designated as a target output buffer by the message and whether an unblocked node exists in the group Gy;the control logic sending the message to a node of the group Gy if the direct interconnect and the unblocked node exist, and sending the message M^ to a node on the level Ljç otherwise. 33. An interconnect apparatus according to Claim 12, wherein: the interconnect structure transmits messages through the interconnect structure in discrete time steps;CA 02227271 2002-02-22 70128-353 the interconnect structure is coupled to one or more output buffers 0^, the message M having a header that designates target output buffers of the one or more output buffers to receive the message M;a selected output buffer of the plurality of output buffers being coupled to a plurality of output target devices and the selected output buffer including a plurality of buffer portions corresponding to and reserved for usage by respective devices of the plurality of output target devices, the message M being allocated to the buffer portions based on a position and a time of insertion into the interconnect structure of the message M^ and the discrete time step timing of transmission of the message M. 34. An interconnect apparatus comprising: a plurality of nodes;and a plurality of interconnect lines selectively coupling the nodes in an interconnect structure transmitting a message M in a plurality of discrete time steps, in which: a node Ny has a direct input interconnection from a node N^ in the interconnect structure and a direct input interconnection from a device G external to the interconnect structure;and the direct input interconnection from the node N^ has precedence over the direct input interconnection from the external device G so that a message Mj\ directed from the node N^ to the node Ny in the same time step as a message Mg directed from the external device G to the node Ny CA 02227271 2002-02-22 70128-353 successfully moves from the node N& to the node Νθ and the message Mq is deflected, wherein: the node distinct from the node Νρ has a direct control· interconnection to the device G external to the interconnect structure, the control interconnection for sending a message blocking command. 35. An interconnect apparatus, comprising : a plurality of nodes;and a plurality of interconnect lines selectively coupling the nodes in a hierarchical multiple level structure with the level of a node being determined entirely by the position of the node in the structure in which data moves only unilaterally from a source level to a destination level or laterally along a level of the multiple level structure, a data message being transmitted through the multiple level structure from a source node to a designated destination node, a level of the multiple levels including: one or more groups of nodes, the data message being transmitted to a group of the one or more groups of nodes that is en route to the destination node, a group of the one or more groups including: a plurality of nodes, the data message being transmitted to a node N of the plurality of nodes of a group unilaterally toward the destination level if the node is not blocked and otherwise the data message being transmitted laterally if the node is blocked, a node that transmits unilaterally to the node N being advised of a possible blocking condition at the node N by a node distinct from the node N. CA 02227271 2002-02-22 70128-353 36. An interconnect apparatus according to Claim 35, comprising: a plurality of interconnect lines selectively coupling the nodes in a hierarchical multiple level structure in which control signals move unilaterally from nodes on a level of the multiple levels to nodes on an adjacent sourceward level, the control signals designating whether an en route node is blocked or not blocked. 37. An interconnect apparatus according to Claim 35, wherein: an en route node on a level receives a data message transmitted laterally along the same level with precedence over a data message transmitted unilaterally from a node on an adjacent sourceward level, the en route node enforcing the precedence by transmitting a control signal to a node on the adjacent sourceward level indicating that the en route node is blocked. 38. An interconnect apparatus according to Claim 35, wherein: an en route node on a level receives a data message transmitted laterally along the same level with precedence over a data message transmitted unilaterally from a node on an adjacent sourceward level. 39. A method of moving messages M through an interconnect structure including a plurality of nodes N and a plurality of interconnect lines L to a plurality of output buffers B, the method comprising: selectively coupling the plurality of nodes N via the plurality of interconnect lines L so that an CA 02227271 2002-02-22 70128-353 interconnect line L(p,q) carries data directly from a node p to a node q;determining for a message M a set of nodes O(M) so that the output buffers B that are targets of the message M are connected to the set of nodes O(M);if the message M is located at the node p at a time t then at the time t, moving the message M on an interconnect line L(p,w) so that at time t+1, the message M is located at a node w, where the node w and the node p are different nodes;if the message M is located at the node p at the time t and the shortest path from the node p to a node of the set of nodes O(M) includes traversal of H interconnect lines L so that the node p is H hops from the nodes O(M), determining an interconnect line L(p,q) so that the shortest path from the node q to a node of the set of nodes O(M) includes traversal of H-l interconnect lines L so that the node q is H-l hops from the nodes O(M);if at time t, the message M is not blocked from using the interconnect line L(p,q) by a control signal originating from a node other than the node q, then at time t, sending the message M on the interconnect line L(p,q) so that at time t+1, the message M is located at the node q;and if at time t, the message M is blocked from using the interconnect line L(p,q) by a control signal originating from a node other than the node q, then at time t, sending the message M on an interconnect line L(p,r), where the node r and the node p are different nodes and the node r and the node q are different nodes, then at time t+1, sending the CA 02227271 2002-02-22 70128-353 message M on the interconnect line L(r,s), where the node s and the node p are different nodes, the node s and the node q are different nodes, the node s and the node r are different nodes, and the shortest path from the node s to a node of the plurality of nodes 0(M) includes traversal of no more than H interconnect lines L so that the node s is no more than H hops from the nodes O(M). 40. A network communicating messages in a sequence of discrete time steps, the network comprising: a plurality of nodes, the nodes including communication devices that receive messages and send messages;and a plurality of interconnect lines L interconnecting communication devices at the plurality of nodes, a node N of the plurality of nodes including: a connection to an interconnect line Lg^ for transmitting a message from a device U to the node N;a connection to an interconnect line Ly^ for transmitting a message from a device V to the node N;the network having a precedence relationship Pn(U,V) relating to the node N and the devices U and V such that the device U has precedence over the device V in sending a message to the node N so that for a message Mg at the device U that is directed to the node N via the interconnect line Lg^ at a time step t and a message My at the device V that is directed to the node N via the interconnect line Ly^ also at a time step t, the message Mg is successfully sent to the node N and the node V uses a control signal from a node not capable of receiving a CA 02227271 2002-02-22 70128-353 message directly from the node V to decide where to send the message My. 41. A network according to Claim 40, further comprising: a node W of the plurality of nodes including: a connection to an interconnect line Ly^ for transmitting a message from a device V to the node W;the message My is deflected to the node W. 42. A method of moving messages M through an interconnect structure including a plurality of nodes N and a plurality of interconnect lines L to a plurality of output buffers B in a sequence of discrete time steps, the method comprising: selectively coupling the plurality of nodes N via the plurality of interconnect lines L so that an interconnect line L(p,q) carries data directly from a node p to a node q;determining for a message M a set of nodes O(M) so that the output buffers B that are selected to receive the message M are connected to the set of nodes O(M);if the message M is located at the node p at a time t then at the time t, moving the message M on an interconnect line L(p,w) so that at time t+1, the message M is located at a node w, where the node w and the node p are different nodes;if the message M is located at the node p at the time t and the shortest path from the node p to a node of CA 02227271 2002-02-22 70128-353 the set of nodes O(M) includes traversal of H interconnect lines L so that the node p is H hops from the nodes O(M), determining an interconnect line L(p,q) so that the shortest path from the node q to a node of the set of nodes O(M) includes traversal of H-l interconnect lines L so that the node q is H-l hops from the nodes 0(M);if at time t, the message M is not blocked from using the interconnect line L(p,q) by a control signal originating from a node other than the node q, then at time t, sending the message M on the interconnect line L(p,q) so that at time t+1 the message M is located at the node q;and if at time t, the message M is blocked from using the interconnect line L(p,q) by a control signal originating from a node other than the node q, then at time t, sending the message M on an interconnect line L(p,r), where the node r and the node p are different nodes and the node r and the node q are different nodes, and a path exists from the node r to the set of nodes O(M) that does not pass through the node p and traverses no more than H+l hops. 43. A method according to Claim 42, further comprising: at time t+1, sending the message M on the interconnect line L(r,s), where the node s and the node p are different nodes, the node s and the node q are different nodes, the node s and the node r are different nodes, and the shortest path from the node s to the node of the plurality of nodes 0(M) includes traversal of no more than H interconnect lines L. 44. A network comprising: a plurality of nodes N;and CA 02227271 2002-02-22 70128-353 a plurality of interconnect lines L connecting the plurality of nodes N in a predetermined pattern, the interconnect lines carrying messages M and control signals C, the messages M and control signals C being received by a node of the plurality of nodes at a discrete time step t and the messages M being moved to subsequent nodes of the plurality of nodes in an immediately subsequent discrete time step t+1, the plurality of interconnect lines L connecting the plurality of nodes N to include: a node NA having a message input interconnection for receiving a message MA, a control input interconnection for receiving a control signal CA, a direct message output interconnection to a node Np, a direct message output interconnection to a node Np, a direct control output interconnection to a device G, and a control logic for determining whether the message MA is sent to the node Np or the node Np based on: (1) the control signal CA from a source distinct from the node ND and the node Np;
- 2(2) a location of the node NA within the plurality of interconnect lines L; and (3) a routing information contained in the message MA; the device G being an external device or a node ng45. A network according to Claim 44, wherein:CA 02227271 2002-02-22 70128-353 the control signal CA is sent by a node Np that is distinct from the node NA, the device G, the node Np, and the node Np. 46. An interconnect apparatus comprising: a plurality of nodes N;and a plurality of interconnect lines L connecting the plurality of nodes N in a predetermined pattern, the plurality of interconnect lines L connecting the plurality of nodes N to include: a node NA having a direct message input interconnection for receiving a message MA and having a plurality of direct message output interconnections for transmitting the message MA to a plurality of nodes including a preferred node Np being most preferred for receiving the message MA, the preferred node Np being determined only by routing information in a header of the message MA and the position of the node NA within the plurality of interconnect lines L;the preferred node Np having a plurality of direct message input interconnections for receiving a message Mp from a plurality of nodes including a priority node Ng which has priority for sending a message to the preferred node Np, the priority node Np being determined by position of the node Np within the plurality of interconnect lines L so that : CA 02227271 2002-02-22 70128-353 if the node is the same as the node Νθ, then the message M^ is the message Mp and is sent from the node N^ to the node Np;and if the node N^ is not the same as the node Np and the node Np directs a message Mp to the node Np, then the message Mp is sent from the node Np to the node Np, and the node N^ uses a control signal to determine where to send the message M^, the control signal not originating from a node capable of receiving a message directly from the node N^. 47. A network capable of carrying a plurality of messages M concurrently comprising: a plurality of output ports P;a plurality of nodes N, the individual nodes N including a plurality of direct message input interconnections and a plurality of direct message output interconnections, the individual nodes N for passing messages M to predetermined output ports of the plurality of output ports P, the predetermined output ports P being designated by the messages M;and a plurality of interconnect lines in an interconnect structure selectively coupling the nodes in a hierarchical multiple level structure arranged to include a plurality of J+l levels in an hierarchy of levels arranged from a lowest destination level Lq to a highest level Lj which is farthest from the lowest destination level Lq, the output ports P being connected to nodes at the lowest destination level Lq, the level of a node being determined entirely by the position of the node in the structure, CA 02227271 2002-02-22 70128-353 the network including a node of the plurality of nodes N, a control signal not originating at the node acting to limit the number of messages that are allowed to be sent to the node to eliminate contention for the predetermined output ports of the node so that the messages M are sent through the direct message output connections of the node to nodes Νβ that are a level L no higher than the level of the node N^, the nodes Νβ being on a path to the designated predetermined output ports P of the messages M. 48. An interconnect apparatus, comprising: a plurality of nodes;and a plurality of interconnect lines in an interconnect structure selectively coupling the nodes in a hierarchical multiple level structure arranged to include: a plurality of J+l levels with J an integer greater than 0 in an hierarchy of levels arranged from a lowest destination level Lq to a highest level Lj with the level of a node being determined entirely by the position of the node in the structure, the interconnect structure transmitting a plurality of multiple-bit messages entering the interconnect structure unsorted through a plurality of input ports, an individual message M of the plurality of messages being self-routing, the individual message M moving in a plurality of ways including three ways which are sufficient for the message M to exit the interconnect structure through an output port designated by the message M, the three ways being: CA 02227271 2002-02-22 70128-353 (1) the message M enters a node in the interconnect structure from a device external to the interconnect structure, the message M designating one or more designated output ports;(2) the message M moves through a node in the interconnect structure without buffering to a designated output port;and (3) the message M moves either through a node U on a level of the interconnect structure without buffering to a different node V on the same level or moves through the node U on a level of the interconnect structure without buffering to a node W on a level Lj_ nearer in the hierarchy to the destination level Lq than the level L^, and the node U uses a control signal from a source distinct from the node V and the node W to determine where to send the message M. 49. An interconnect apparatus as claimed in Claim 48, wherein a node on the level has a plurality of interconnections including: a direct data input interconnection from a node Νβ]ζ on the level a direct data output interconnection to a node Np^ on the level L^;a direct data input interconnection from a node NCm on a level Lm where m is greater than k, or from a device Dq external to the interconnect structure;and CA 02227271 2002-02-22 70128-353 a direct data output interconnection to a device De external to the interconnect structure, or a direct data output interconnection to a node Npj_ on the level Lj_ where k is greater than i so that the level Lj_ is closer in the hierarchy to the destination level Lg, wherein: among devices having a direct interconnection to the node N^, a precedence relationship exists for sending data to the node N^ so that: a node Νβ^ on the level having a direct interconnection to the node N^ has precedence over a device Dg where the device Dg is a node Ng^ on the level Lj_ or a device Dg external to the interconnect structure;the precedence relationship for a message MB to be sent from the node Νβ^ to the node and a message Mg to be sent from the device Dg to the node N^^ in a same time interval results in the message Μβ being sent and the message Mg prevented from being sent. 50. An interconnect apparatus as claimed in Claim 48, wherein the interconnect structure: carries messages and control signals;includes a node Ng including: a direct message input interconnection for receiving a message M^ from a node and a direct message input interconnection for receiving a message Mp from a node Np;and CA 02227271 2002-02-22 70128-353 the node N^ has a control logic and a control input interconnection for receiving a control signal from the node Np, the control signal enforcing a precedence of the direct message input interconnection from the node Np to the node Np over the message input interconnection from the node N^ to the node Np so that the node Np sends a message Mp to the node Np and sends a control signal (¾ designating a blocking condition to the node N^, the node N^ control logic receives the control signal designating the blocking condition and responds to the control signal by blocking transmission of the message M^ destined to arrive at the node Np at the same time as the message Mp, causing the blocked message M^ to be alternatively sent to a node Nq where the node Nq is distinct from the node Np and the node N^ is distinct from the node N^. 51. An interconnect apparatus as claimed in Claim 48, wherein the interconnect structure: carries messages and control signals;includes a node Np including: a direct message input interconnection for receiving a message M^ from a node N^, the message M^ having a header;and a direct message input interconnection for receiving a message Mp from a node Np;and CA 02227271 2002-02-22 70128-353 the node N^ has a control logic and a control input interconnection for receiving a control signal from the node Np, the control signal enforcing a precedence of the direct message input interconnection from the node Np to the node Np over the direct message input interconnection from the node N^ to the node Np so that a message arriving at the node N^ in the absence of a blocking control signal in a same time interval causes the node N^ control logic to use a header of the message to determine a selected device for transmitting the message M^, in case the selected device is the node Np then the message being sent to the node Np, wherein: the control logic of node N^ determines: whether, in a first condition, the node N^ has a direct output interconnection to a node Npj_ on the level i nearer in the hierarchy to the destination level Lq than the level in which the node Npj_ has a pathway to a designated output port designated by the message and whether, in a second condition, the node Npj_ is unblocked by another message;and the control logic of node N^, when the first and second conditions are satisfied, sends the message to the node Npj_;and the control logic of node N^, when the first and second conditions are not both satisfied, sends the message to a node Nq where node N^^ and node Np^ are distinct and the node Npi and the node Np are distinct. CA 02227271 2002-02-22 70128-353 52. An interconnect apparatus as claimed in Claim 48, further comprising : a plurality of output ports including a plurality of accessible output ports that are accessible to a node on the level L^, the accessible output ports being accessible via a pathway through the interconnect nodes;and each of the accessible output ports accessible to the node N^ also being accessible to a node Np^ on a level nearer in the hierarchy to the destination level Lq than the level L^, the node having a direct output interconnection to the node Npj_. 53. An interconnect apparatus as claimed in Claim 48, wherein: a node Np has a first data input interconnection from a node N^ and a second data input interconnection from a node Np;and a control interconnection between the node N^ and node Np resolves contention for sending messages to the node Np. 54. An interconnect apparatus as claimed in Claim 48, further comprising: a node N^ on the level L^ having a direct data output interconnection to a node N^j_ on a level Lj_ nearer in the hierarchy to the destination level Lq than the level L^, and having a precedence relationship with respect to a message Mq which, at a time T, moves through the node Nq and is preferentially sent to the node N^, but is blocked from CA 02227271 2002-02-22 70128-353 node Njx by a message Μβ so that the message Mg is deflected to a node on the level distinct from node Ngj^;a node Ng^- on the level having a direct data output interconnection to a node Ng^ on the level Lj_, the node Ngj_ having a pathway through the interconnect nodes to an accessible output port accessible to the message Mg, the message Mg being deflected to pass through the node Ngj^ at a time T', a first time step following the time T that a node directs message Mg to a lower level;wherein the interconnect structure disallows the message Μβ from being in a position to block the message Mg at the time T'. 55. A network according to Claim 48 further comprising: nodes B and C on a level Lj_]_ that are nodes capable of receiving a message directly from the node A on a level Lj;devices D and E, each of which is either a node on a level Lj_^ where N is greater than 1 or a device external to the network, the node B being capable of sending a message directly to the device D, the node C being capable of sending a message directly to the device E, the device D being incapable of sending a message directly or indirectly to the device E, the device E being incapable of sending a message directly or indirectly to the device D. 56. An interconnect structure comprising: a plurality of nodes;and CA 02227271 2002-02-22 70128-353 a plurality of interconnect lines in an interconnect structure selectively coupling the nodes in a structure, the interconnect structure transmitting a plurality of multiple-bit messages entering the interconnect structure unsorted through a plurality of input ports, an individual message M of the plurality of messages being self-routing, the interconnect structure including: a node Np having a first data input interconnection from a node N^ and a second data input interconnection from a node Np distinct from the node N^;and a control interconnection between the node N^ and node Np the control interconnection for carrying a control signal to resolve contention for sending messages to the node Np, the control signal being supplied from the node N^ or the node Np each distinct from the node Np with which messages are being communicated. 57. An interconnect apparatus as claimed in Claim 56, wherein the interconnect structure : carries messages and control signals;includes a node Np including: a direct message input interconnection for receiving a message from a node N^;and a direct message input interconnection for receiving a message Mp from a node Np;and the node has a control logic and a control input interconnection for receiving a control signal C^ from CA 02227271 2002-02-22 70128-353 the node Np, the control signal C& enforcing a precedence of the direct message input interconnection from the node Np to the node Ng over the message input interconnection from the node N^ to the node Ng so that the node Np sends a message Mp to the node Np and sends a control signal designating a blocking condition to the node N/^, the node NA control logic receives the control signal designating the blocking condition and responds to the control signal by blocking transmission of the message destined to arrive at the node Np at the same time as the message Mp, causing the blocked message to be alternatively sent to a node Ny where the node Ny is distinct from the node Np and the node Ny is distinct from the node N^. 58, An interconnect apparatus as claimed in Claim 56, wherein the interconnect structure : carries messages and control signals;includes a node Np including: a direct message input interconnection for receiving a message M^ from a node N^z the message having a header;and a direct message input interconnection for receiving a message Mp from a node Np;and the node N^ has a control logic and a control input interconnection for receiving a control signal from CA 02227271 2002-02-22 70128-353 the node Np, the control signal CA enforcing a precedence of the direct message input interconnection from the node Np to the node Np over the direct message input interconnection from the node NA to the node Np so that a message MA arriving at the node NA in the absence of a blocking control signal CA in a same time interval causes the node NA control logic to use a header of the message to determine a selected device for transmitting the message MA, in case the selected device is the node NE then the message MA being sent to the node Np. 59. A method of moving messages through an interconnect structure comprising: interconnecting a plurality of devices in a structure, the devices having a plurality of message input terminals and a plurality of message output terminals, a plurality of interconnect lines interconnecting the device with connections from a message output terminal of a sending device to a message input terminal of a receiving device;assigning a priority among a plurality of sending devices having output message terminals coupled to the input message terminal of a single receiving device;entering a message into the interconnect structure for transfer to one or more designated output ports;sending a message, without buffering, from a sending device to a receiving device en route to the one or more output ports using self-routing, with the sending device neither requesting of the receiving device nor receiving from the receiving device, permission to send the message to the receiving device;CA 02227271 2002-02-22 70128-353 communicating among a plurality of sending devices that send messages to a single receiving device, a sending device with priority for sending messages to the single receiving device having a control signal output terminal connected by an interconnect line to a control signal input terminal of a sending device without priority, the sending device with priority sending a control signal to the sending device without priority;deflecting a message intended to be sent from a sending device without priority to an intended receiving device, the deflected message being deflected to an alternative receiving device, the alternative receiving device also being en route to the one or more output ports, the message being deflected on the basis of a control signal being supplied from a node distinct from the node with which messages are being communicated. 60. A method of moving messages through an interconnect structure comprising: interconnecting a plurality of devices D to a node Ng using a plurality of direct node Ng input interconnections ;enforcing a precedence relationship among the devices D having a direct input interconnection to the node Ng for sending a message to the node Ng;sending a message from a node Nj\ to the node Ng in a time period T when: in the time period T a message moves through a node N^ having a direct input interconnection to the node CA 02227271 2002-02-22 70128-353 Np, the message MA is directed to be sent to the node Np in the time period T, and no message Mp directed to be sent to the node Np or deflected to the node Np moves through a node Np having a direct input interconnection to the node Np in the time period T in which the node Np has precedence over the node Na for sending messages to node Np. 61. A method as claimed in Claim 60 further comprising: aborting the sending of message MA to the node NA in the time period T if, in the time period T, the node Np sends a message Mp to the node Np;sending the message MA, aborted with respect to node Na, to a node Np, the node Np being distinct from the node Na and the node Np;and sending a control signal, by the node Np to the node Na causing the message MA to be aborted with respect to the node NA and enforcing the precedence relationship. 62. A method of moving messages M through an interconnect structure including a plurality of nodes N and a plurality of interconnect lines L to a plurality of output buffers B, the method comprising: selectively coupling the plurality of nodes N via the plurality of interconnect lines L so that an interconnect line L(p,q) carries data directly from a node p to a node q;CA 02227271 2002-02-22 70128-353 determining for a message M a set of nodes 0(M) so that the output buffers B that are targets of the message M are connected to the set of nodes 0(M);if the beginning of the message M is located at the node p at a step t then at the step t, moving·the message M on an interconnect line L(p,w) so that at a step t+1, the beginning of the message M is located at a node w, where the node w and the node p are different nodes;if the beginning of the message M is located at the node p at the step t and the shortest path from the node p to a node of the set of nodes O(M) is H hops, determining an interconnect line L(p,q) so that the shortest path from the node q to a node of the set of nodes O(M) is H-l hops;if at the step t, the message M is not blocked from using the interconnect line L(p,q) by a control signal originating from a node other than the node q, then at the step t, sending the beginning of the message M on the interconnect line L(p,q) so that at the step t+1, the message M is located at the node q;and if at the step t, the message M is blocked from using the interconnect line L(p,q) by a control signal originating from a node other than the node q, then at the step t, sending the message M on an interconnect line L(p,r), where the node r and the node p are different nodes and the node r and the node s are different nodes, then at the step t+1, sending the message M on the interconnect line L(r,s), where the node s and the node p are different nodes, the node s and the node q are different nodes and the node s and the node r are different nodes, and the shortest path from the node s to a node of the plurality of nodes O(M) is no more than H hops. CA 02227271 2002-02-22 70128-353 63. A method of moving messages M through an interconnect structure including a plurality of nodes N and a plurality of interconnect lines L to a plurality of output buffers B, the method comprising: selectively coupling the plurality of nodes N via the plurality of interconnect lines L so that an interconnect line L(p,q) carries data directly from a node p to a node q;determining for a message M a set of nodes 0(M) so that the output buffers B that are targets of the message M are connected to the set of nodes O(M);if a beginning portion of the message M is located at the node p at a step t then at the step t, moving the message M on an interconnect line L(p,w) so that at a step t+l, the beginning of the message M is located at a node w, where the node w and the node p are different nodes;if the beginning of the message the node p at the step t and the shortest p to a node of the set of nodes O(M) is H so that the shortest M is path hops, located at from the node an interconnect the node q to a line L(p,q) node of the set of nodes 0(M) is determining path from H-l hops;if at the step t, from using the interconnect the message M is not blocked line L(p,q) by a control signal originating from a node other than the node q, then at the step t, sending the message M on the interconnect line L(p,q) so that at the step t+l, the beginning portion of the message M is located at the node q;and if at the step t, the message M is blocked from using the interconnect line L(p,q) by a control signal originating from a node other than the node q, then at the CA 02227271 2002-02-22 70128-353 step t, sending the message M on an interconnect line L(p,r), where the node r and the node p are different nodes and the node r and the node q are different nodes, and the shortest path from the node r to a node of the plurality of nodes O(M) is no more than H hops. 64. A method of sending data comprising: providing an interconnect apparatus including a plurality of nodes N and a plurality of interconnect lines L connecting the plurality of nodes N in a predetermined pattern;connecting the plurality of nodes N using the plurality of interconnect lines L to include: a node NA having a direct message input interconnection for receiving a message MA and having a plurality of direct message output interconnections for transmitting the message MA to a plurality of nodes including a preferred node Np being most preferred for receiving the message MA, the preferred node Np being only determined by routing information in a header of the message Ma and the position of the node NA within the plurality of interconnect lines L;the preferred node Np having a plurality of direct message input interconnections for receiving a message Mp from a plurality of nodes including a priority node Np which has priority for sending a message to the preferred node Np, the priority node Np being determined by position of the node Np within the plurality of interconnect lines L;CA 02227271 2002-02-22 70128-353 if the node N^ is the same as the node Νβ, sending the message M^ as the message Mp from the node N^ to the node Np;and if the node N^ is not the same as the node Νβ and the node Νβ directs a message Mg to the node Np, then sending the message Μβ from the node Νβ to the node Np, and the node N^ uses a control signal from a source distinct from the node Np to determine where to send the message M^. 65, A method of sending messages comprising: providing a network for carrying a plurality of messages M concurrently including: a plurality of output ports P;and a plurality of nodes N, the individual nodes N including a plurality of direct message input interconnections and a plurality of direct message output interconnections, the individual nodes N for passing messages M to predetermined output ports of the plurality of output ports P, the predetermined output ports P being designated by the messages M;and a plurality of interconnect lines in an interconnect structure ;selectively coupling the nodes in a hierarchical multiple level structure to include a plurality of J+l levels with J an integer greater than 0 in an hierarchy of levels arranged from a lowest destination level Lq to a highest level Lj which is farthest in the hierarchy from the lowest destination level Lq, the level of a node being CA 02227271 2002-02-22 70128-353 determined entirely by the position of the node in the structure, the output ports P being connected to nodes at the lowest destination level Lq, including in the network a node of the plurality of nodes N;limiting the number of messages M that are allowed to enter the plurality of direct message input interconnections of node by using a control signal not originating at the node to eliminate contention for the predetermined output ports of the node so that the messages M are sent through the direct message output connections of the node to nodes Νβ that are a level L no higher than the level of the node the nodes Npj being on a path to the designated predetermined output ports P of the messages M. 66. A method of transmitting a message through an hierarchical interconnect structure including a plurality of nodes and a plurality of interconnect lines, the method comprising: selectively coupling the nodes in an hierarchical multiple level structure arranged to include a plurality of J+l levels with J an integer greater than 0 in an hierarchy of levels arranged from a lowest destination level Lq to a highest level Lj, the level of a node being determined entirely by the position of the node in the structure;entering a plurality of messages into the interconnect structure unsorted through a plurality of input ports;CA 02227271 2002-02-22 70128-353 moving, using self-routing, an individual message M of the plurality of messages through nodes, the message M moving in a plurality of ways including three ways which are sufficient for the message M to exit the interconnect structure through an output port designated by the message M, the three ways including: (1) entering the message M to a node in the interconnect structure from a device external to the interconnect structure, the message M designating one or more designated output ports;(2) moving the message M through a node in the interconnect structure without buffering to a designated output port;and (3) moving the message M either through a node U on a level of the interconnect structure without buffering to a different node V on the same level L^, the different node V also having a pathway to a designated output port;or moving the message M through the node U on the level of the interconnect structure without buffering to a node W on a level nearer in the hierarchy to the destination level Lq than the level L^, the node U using a control signal from a source distinct from the node V and the node W to determine where to send the message M. 67. An interconnect structure comprising: a plurality of nodes arranged in a topology of three dimensions;means for transmitting a message from a node N to a target destination including: CA 02227271 2002-02-22 70128-353 means for determining whether a node en route to the target destination in the second and third dimensions and advancing one level toward the destination level of the first dimension is blocked by another message;means for advancing the message one level toward the destination level of the first dimension when the en route node is not blocked;means for moving the message in the second and third dimensions along a constant level in the first dimension otherwise;means for specifying the first dimension to describe a plurality of levels, the second dimension to describe a plurality of nodes spanning a cross-seetion of a level, and the third dimension to describe a plurality of nodes in the cross-section of a level;means for sending a control signal from a node on the level of the en route node to the node N in the first dimension, the control signal specifying whether the node en route is blocked;means for timing transmission of a message using a global clock specifying timing intervals to keep integral time modulus the number of nodes in a cross-section of a level;means for setting a first time interval a for moving the message in the second and third dimensions;means for setting a second time interval a - β for advancing the message one level toward the destination level, the global clock specifying a global time interval CA 02227271 2002-02-22 70128-353 equal to the second time interval, the first time interval being smaller than the global time interval;and means for setting a third time interval for sending the control signal from the node on the level of the en route node to the node N, the third time interval being equal to β. 68. An interconnect structure according to Claim 67, further comprising: means for timing the message moving and advancing steps so that the messages enter node N on level q at times having the form not + qP;and means for timing the control signal sending step so that the control signals enter node N on level q at times having the form na + qP so long as the node en route is not blocked. 69. An interconnect structure according to Claim 67, further comprising: means for timing transmission of a message using a global clock;means for setting a first time interval for moving the message in the second and third dimensions;means for setting a second time interval for advancing the message one level toward the destination level in the first dimension;means for specifying the first dimension to describe a plurality of levels, the second dimension to describe a plurality of nodes spanning a cross-section of a CA 02227271 2002-02-22 70128-353 level, and the third dimension to describe a plurality of nodes in the cross-section of a level;means for specifying timing interval of the global clock to keep integral time modulus the number of nodes in a cross-section of a level, the global clock time interval being equal to the second time interval and the first time interval being smaller than the global time interval. 70. An interconnect structure according to Claim 67 further comprising: means for defining a header and a payload in the message;means for encoding the destination in the second dimension in the header;means for determining whether a potentially en route node is en route to the target destination including: means for comparing the encoded destination in the second dimension to an encoded position of the potentially en route node;means for resolving that the potentially en route node is en route when the encoded destination is the same as the encoded position of the potentially en route node, wherein: the destination in the third dimension in the header is encoded in a plurality of single-bit codes, the single-bit codes relating to a level of the third dimension;the position of the potentially en route node is encoded in a single-bit code;and CA 02227271 2002-02-22 70128-353 the means for comparing is a means for performing a single-bit comparison of the level-specific, single-bit destination code and the single-bit position code;and means for discarding the level-specific, singlebit destination code in the header as the message advances one level. 71. An interconnect structure according to Claim 67 wherein : a level T of the first dimension spans one ring in 2T passes through the nodes in the second dimension so that 2T nodes in the third dimension designate one ring;and the three dimensional interconnect structure is configured so that advancing of levels from a start level to the destination level of the first dimension furnishes access to all nodes in a ring. 72. An interconnect structure according to Claim 67 further comprising: injecting a message at a time (q2 - ql)modK * a + J into the interconnect structure at a node N(J, ql, zl) and targeting the message to exit the interconnect structure at a node N(0, q2, z2) causes the message to arrive at node N(0, q2, z2) at time 0. 73. A communication interconnect structure for transmitting messages, comprising: a plurality of nodes arranged in a structure including : a hierarchy of levels from a source level to a destination level;CA 02227271 2002-02-22 70128-353 a plurality of nodes spanning a cross-section of a level;and a plurality of nodes in a cross-section span, the level of a node being determined entirely by the position of the node in the structure;a plurality of interconnect lines coupling the nodes in the structure including for a node N on a level L: a message input interconnect line coupled to a node on a previous level L+l;a message input interconnect line coupled to a node on the level L;a message output interconnect line coupled to a node on the level L;a message output interconnect line coupled to a node on a subsequent level L-l;a control input interconnect line coupled to the message output interconnect line of a node on the level L-l;and a switch coupled to receive a message on the control input interconnect line and, in accordance with the message, to selectively transmit a message without buffering on the message output interconnect line coupled to the subsequent level L-l node or on the message output interconnect line coupled to the level L. 74. An interconnect structure according to Claim 73, further comprising: CA 02227271 2002-02-22 70128-353 a control output interconnect line coupled to a control input terminal of the node on the previous level L+l ;a switch for determining that a message is blocking the node N and communicating via the control input interconnect line informing whether the node N is blocked;a global clock generating timing signals, the timing signals in discrete time steps of an integral time modulus the number of nodes on a level timing a message transmission time of a message transmitted from a level to a subsequent level and for timing a control signal transmission time of a control signal from a subsequent level to a level so that the control signal arrives first at a node ;a control output interconnect line coupled to a control input terminal of the node on the previous level L+l;and a switch for determining that a message is blocking the node N and communicating via the control input interconnect line informing whether the node N is blocked. 75. A method of communicating messages in an interconnect structure comprising: arranging a plurality of nodes in a structure including a plurality of hierarchical levels from a source level to a destination level, the level of a node being determined entirely by the position of the node in the structure, a plurality of nodes spanning a cross-section of a level and a plurality of nodes in a cross-section span, the nodes having an input connection on the same level, an input connection on a previous level, an output connection CA 02227271 2002-02-22 70128-353 on the same level and an output connection on a subsequent level;specifying a destination node in the destination level for receiving a message;originating the message at a node in the source level;communicating a message from node to node including: determining at a node whether a node on a subsequent level is directed toward the destination node;determining at a node whether the node on the subsequent level is blocked by another message;advancing the message to the node on the subsequent level when the node is directed toward the destination node and a node is unblocked;and otherwise traversing the message to a node on the same level. 76. A method according to Claim 75 wherein determining whether a node on a subsequent level is directed toward the destination node further comprises: encoding the destination node in a message in the header field;encoding a designation of node position for the nodes at the levels;and determining that the node on the subsequent level is directed toward the destination node when the destination CA 02227271 2002-02-22 70128-353 node encoding and the node position designation encoding correspond. 77. A communication interconnect structure comprising: a plurality of nodes;and a plurality of interconnect lines coupling the nodes, a node X of the plurality of nodes having: a message input interconnect line coupled to a node A distinct from the node X;and a message input interconnect line coupled to a node B distinct from the node A and the node X, the node X accepting a message input from the node A and a message input from the node B with a control signal communicating between the node A and the node B for determining a priority relationship between conflicting messages, the control signal enforcing the priority relationship between the sending of a message from the node A to the node X and the sending of a message from the node B to the node X. 78. An interconnect apparatus, comprising : a plurality of nodes;and a plurality of interconnect lines in an interconnect structure selectively coupling the nodes in a hierarchical multiple level structure arranged to-include: a plurality of J+l levels in an hierarchy of levels arranged from a lowest destination level Lq to a highest level Lj which is farthest from the lowest destination level Lq, the level of a node being determined entirely by the position of the node in the structure, the CA 02227271 2002-02-22 70128-353 interconnect structure transmitting a message M in a plurality of discrete time steps, the message M moving in a time step and the interconnect structure having interconnections to move the message M in one of three ways in the time step including: the message M enters a node in the interconnect structure from a device external to the interconnect structure;the message M exits the interconnect structure to a designated output buffer;and the message M either moves from a node U on a level to a different node V on the same level or moves from the node U to a node W on a level Lj, where k is greater than i so that the level Lj, is closer to the destination level Lq than the level L^. 79. An interconnect apparatus according to Claim 78, wherein the interconnect structure is self-routing. 80. An interconnect apparatus according to Claim 78, wherein a node on the level Lj^ has a plurality of interconnections including: a direct data input interconnection from a node Νβ}ζ on the level L^;a direct data output interconnection to a node on the level L^;a direct data input interconnection from a node Nçm on the level Lm where m is greater than k so that the CA 02227271 2002-02-22 70128-353 level Lm is farther from the destination level Lg than the level L^;and a direct data output interconnection to a device Dg external to the interconnect structure or a node Ng| on the level Lj_ where k is greater than i so that the level Lj_ is closer to the destination level Lg than the level L^. 81. An interconnect apparatus according to Claim 78, wherein a node on the level has a plurality of interconnections including : a direct data input interconnection from a node Νβ}ζ on the level L^;a direct data output interconnection to a node on the level L^;a direct data input interconnection from a device Dg external to the interconnect structure;and a direct data output interconnection to a device Dg external to the interconnect structure or a node Ng^ on the level L-[ where k is greater than i so that the level is closer to the destination level Lg than the level L^. 82. An interconnect apparatus according to Claim 78, wherein : the plurality of nodes are arranged into a plurality of node groups in which all of the nodes of a given group Gm are on the same level and each node of the plurality of nodes is included in only one group of the plurality of groups;and CA 02227271 2002-02-22 70128-353 a node NAk in the group Gm on the level Ιψ has a plurality of interconnections including : a direct data input interconnection from a node Nfik ΐη the group Gm on the level L^;and a direct data output interconnection to a node in the group Gm on the level L^. 83. An interconnect apparatus according to Claim 78, wherein: the plurality of nodes are arranged into a plurality of mutually exclusive node groups including a group Gp and a group Gy in which all of the nodes of the group Gp are on the same level and all of the nodes of the group Gy are on the same level Lj_;and if a node Np of the group Gp has an interconnect path for sending a message to a node Nq of the group Gy, then all nodes of the group Gp have interconnect paths for sending a message to a node of the group Gy. 84. An interconnect apparatus according to Claim 78, wherein: the plurality of nodes are arranged into a plurality of mutually exclusive node groups including a group Gp and a group Gy in which all of the nodes of the group Gp are on the same level and all of the nodes of the group Gy are on the same level Lj_;and if an interconnect path exists for sending a message from a node of the group Gp to a node of the group CA 02227271 2002-02-22 70128-353 Gy, and the group Gy includes a node Np and the group Gy includes a node Ng, then the interconnect structure includes an interconnect path for sending a message from the node Np to the node Ng. 85. An interconnect apparatus according to Claim 78, wherein: the plurality of nodes are arranged into a plurality of mutually exclusive node groups including a group Gy and a group Gy in which all of the nodes of the group Gy are on the same level and all of the nodes of the group Gy are on the same level Lj_;and if one node in the group Gy has an interconnect path for sending a message to a node in the group Gy, then all nodes in the group Gy have interconnect paths for sending messages to a node in the group Gy. 86. An interconnect apparatus according to Claim 78, wherein: a node Ny has a direct input interconnection from a node N^ in the interconnect structure and a direct input interconnection from a device G external to the interconnect structure;and the direct input interconnection from the node N^ has precedence over the direct input interconnection from the external device G so that every message directed from the node N^ to the node Ny successfully moves from the node N^ to the node Ny. CA 02227271 2002-02-22 70128-353 87. An interconnect apparatus according to Claim 78, wherein: a node Np on the level Lj_ has a direct input interconnection from a node N^ also on the level Lj and a direct input interconnection from a node Ng on the level L^;and the direct input interconnection from the node N^ has precedence over the direct input interconnection from the node Ng so that every message M& directed from the node N/\ to the node Nq successfully moves from the node N& to the node Nq. 88. An interconnect apparatus according to Claim 78, wherein the interconnect structure: carries messages and control signals;and includes a node N& including: a direct message input interconnection for receiving a message having a header;a direct control input interconnection for receiving a control signal C^;a plurality of direct message output interconnections to a respective plurality of subsequent nodes for directing the message and a control logic responsive to the control signal Cjy and the header of the message for determining a node of the plurality of subsequent nodes to direct the message ma. CA 02227271 2002-02-22 70128-353 89. An interconnect apparatus according to Claim 78, wherein the interconnect structure : carries messages and control signals;includes a node Νβ including: a direct message input interconnection for receiving a message Mg from a device G external to the interconnect structure;and a direct message input interconnection for receiving a message M^ from a node N^;and the node N^ has a control logic setting a precedence of the direct message input interconnection from the node N^ to the node Νβ over the direct message input interconnection from the device G to the node Νβ so that, in a discrete time step, if the device G holds the message Mg for entry to the interconnect structure to the node Νβ and the node Ν/γ has the message M^ directed to the node Νβ, then, in the discrete time step, the message is successfully sent from the node N^ to the node Νβ and the message Mg is blocked from transmission to the node Ng. 90. An interconnect apparatus according to Claim 78, wherein the interconnect structure: carries messages and control signals;includes a node Νβ including: a direct message input interconnection for receiving a message Mg from a device G external to the interconnect structure;and CA 02227271 2002-02-22 70128-353 a direct message input interconnection for receiving a message MA from a node NA;and the device G has a control logic and direct control input interconnection coupled to the control logic for receiving a control signal Cg from the node NA, the control signal Cg enforcing a precedence of the direct message input interconnection from the node NA to the node Np over the direct message input interconnection from the device G to the node Np so that, in a discrete time step, if the device G holds the message Mg for entry to the interconnect structure to the node Np and the node NA has the message MA directed to the node Np, then, in the discrete time step, the message MA is successfully sent from node Na to node Np and the control logic receives the control signal Cg designating a blocking condition and, responsive to the control signal Cg blocking condition, the control logic blocks transmission of the message MG to the node Np. 91. An interconnect apparatus according to Claim 78, wherein the interconnect structure: carries messages and control signals;includes a node Np including: a direct message input interconnection for receiving a message Mg from a device G external to the interconnect structure;and a direct message input interconnection for receiving a message MA from a node NA;and CA 02227271 2002-02-22 70128-353 the device G has a control logic and direct control input interconnection coupled to the control logic for receiving a control signal Cg from the node N^, the control signal Cg enforcing a precedence of the direct message input interconnection from the node N/\ to the node Ng over the direct message input interconnection from the device G to the node Ng so that, in a discrete time step, if the device G holds the message Mg for entry to the interconnect structure to the node Ng and the node N^ has no message directed to the node Ng, then, in the discrete time step, the control logic does not receive the control signal Cg designating a blocking condition and, responsive to the absence of the control signal Cg blocking condition, the control logic transmits the message Mg to the node Ng, wherein in the discrete time step: the node N^ is idle, or the node N& includes a control logic that: (1) directs the message M^ to a node Ng distinct from the node Ng;and (2) sends the control signal Cg designating the absence of the blocking condition. 92. An interconnect apparatus according to Claim 78, wherein the interconnect structure: carries messages and control signals;includes a node Ng including: CA 02227271 2002-02-22 70128-353 a direct message input interconnection for receiving a message from a node N^;and a direct message input interconnection for receiving a message Mp from a node Np;and the node N& has a control logic and a direct control input interconnection for receiving a control signal (¾ from the node Np, the control signal enforcing a precedence of the direct message input interconnection from the node Np to the node Np over the direct message input interconnection from the node N^ to the node Np so that, in a discrete time step, if the message is present at the node N^ and the node Np has the message Mp directed to the node Np, then, in the discrete time step, the message Mp is successfully sent from node Np to node Np and the control logic receives the control signal C& designating a blocking condition and, responsive to the control signal blocking condition, the control logic blocks transmission of the message M^ to the node Np and directs the message to a node Np distinct from the node Np. 93. An interconnect apparatus according to Claim 78, wherein the interconnect structure: carries messages and control signals;includes a node Np including: a direct message input interconnection for receiving a message from a node Nj^, the message M& having a header;and CA 02227271 2002-02-22 70128-353 a direct message input interconnection for receiving a message Mp from a node Np;and the node N^ has a control logic and a direct control input interconnection for receiving a control signal from the node Np, the control signal C& enforcing a precedence of the direct message input interconnection from the node Np to the node Np over the direct message input interconnection from the node N^ to the node Np so that, in a discrete time step, if the message M^ is present at the node N^ and the node Np has no message Mp directed to the node Np, then, in the discrete time step, the control logic does not receive the control signal designating a blocking condition and, responsive to the absence of the control signal blocking condition, the control logic uses the header of the message M^ to determine a preferred device for transmitting the message M^ and if the preferred device is the node Np, then the message is sent to the node Np, wherein in the discrete time step: the node Np is idle;or the node Np includes a control logic that: (1) directs the message Mp to a device distinct from the node Np;and (2) sends the control signal designating the absence of the blocking condition. 94. An interconnect apparatus according to Claim 93, CA 02227271 2002-02-22 70128-353 a message Mg is present at the node Ng,. the message Mg having a header designating one or more target output buffers;if the node Ng has an interconnect path to a node of the plurality of nodes N connected to a target output buffer designated by the message Mg, then the control logic of the node N^ directs the message M& to the node Ng;and otherwise the control logic of the node N^ directs the message M^ to a node Ng on the level Ljç. 95. An interconnect apparatus according to Claim 78, further comprising: a node N& on the level Ιψ having a direct data output interconnection to a node Ng on the level Lj_, the node Ng having an interconnect path to a node N^ that is connected to an output buffer wherein: if a message is present at the node N^ and has a header designating the output buffer as a target output buffer, and the message M^ is not blocked from transmission to the node Ng;then a message Mg that is directed to the node Ng is sent directly to the node Ng;and otherwise the message M^ is sent directly to a node Ng on the level Lfc. 96. An interconnect apparatus according to Claim 78, further comprising: CA 02227271 2002-02-22 70128-353 t a node on the level the node including a control logic that utilizes a header information of a message present at the node N& to ascertain: whether a direct interconnect exists from the node to a node belonging to a group Gy at the level Lj_ such that an interconnect path exists from a node in the group Gy to a node Νβ that is connected to an output buffer designated as a target output buffer by the message M^;and whether an unblocked node exists in the group Gy;the control logic sending the message to a node of the group Gy if the direct interconnect and the unblocked node exist, and sending the message to a node on the level Lk otherwise. 97. An interconnect apparatus according to Claim 78, wherein: the interconnect structure transmits messages through the interconnect structure in discrete time steps;the interconnect structure is coupled to one or more output buffers 0^, the message M having a header that designates target output buffers of the one or more output buffers (¾ to receive the message M;a selected output buffer Opj of the plurality of output buffers being coupled to a plurality of output target devices and the selected output buffer including a plurality of buffer portions corresponding to and reserved for usage by respective devices of the plurality of output target devices, the message M being allocated to the buffer CA 02227271 2002-02-22 70128-353 portions based on a position and a time of insertion into the interconnect structure of the message and the discrete time step timing of transmission of the message M. 98. An interconnect apparatus, comprising: a plurality of nodes;and a plurality of interconnect lines selectively coupling the nodes in a hierarchical multiple level structure with the level of a node being determined entirely by the position of the node in the structure in which data moves only unilaterally from a source level to a destination level or laterally along a level of the multiple level structure, a data message being transmitted through the multiple level structure from a source node to a designated destination node, a level of the multiple levels including: one or more groups of nodes, the data message being transmitted to a group of the one or more groups of nodes that is en route to the destination node, a group of the one or more groups including: a plurality of nodes, the data message being transmitted to a node N of the plurality of nodes of a group unilaterally toward the destination level if the node is not blocked and otherwise the data message being transmitted laterally if the node is blocked. 99. An interconnect apparatus according to Claim 98, comprising: a plurality of interconnect lines selectively coupling the nodes in a hierarchical multiple level structure in which control signals move unilaterally from nodes on a level of the multiple levels to nodes on an CA 02227271 2002-02-22 70128-353 100 adjacent sourceward level, the control signals designating whether an en route node is blocked or not blocked. 100. An interconnect apparatus according to Claim 98, wherein: an en route node on a level receives a data message transmitted laterally along the same level with precedence over a data message transmitted unilaterally from a node on an adjacent sourceward level, the en route node enforcing the precedence by transmitting a control signal to a node on the adjacent sourceward level indicating that the en route node is blocked. 101. An interconnect apparatus according to Claim 98, wherein : an en route node on a level receives a data message transmitted laterally along the same level with precedence over a data message transmitted unilaterally from a node on an adjacent sourceward level. 102. A network communicating messages in a sequence of discrete time steps, the network comprising: a plurality of nodes, the nodes including communication devices that receive messages and send messages;and a plurality of interconnect lines L interconnecting communication devices at the plurality of nodes, a node N of the plurality of nodes including: a connection to an interconnect line Ly^ for transmitting a message from a device U to the node N;CA 02227271 2002-02-22 70128-353 101 a connection to an interconnect line for transmitting a message from a device V to the node N;the network having a precedence relationship Pn(U'V) relating to the node N and the devices U and V such that the device U has precedence over the device V in sending a message to the node N so that for a message My at the device U that is directed to the node N via the interconnect line Lyjq at a time step t and a message My at the device V that is directed to the node N via the interconnect line Ly^ also at a time step t, the message My is successfully sent to the node N and the node V uses a control signal to decide where to send the message My. 103. A network according to Claim 102 further comprising : a node W of the plurality of nodes including: a connection to an interconnect line Ly^ for transmitting a message from a device V to the node W;the message My is deflected to the node W. 104. A network comprising: a plurality of nodes N;and a plurality of interconnect lines L connecting the plurality of nodes N in a predetermined pattern, the interconnect lines carrying messages M and control signals C, the messages M and control signals C being received by a node of the plurality of nodes at a discrete time step t and the messages M being moved to subsequent nodes of the plurality of nodes in an immediately subsequent discrete CA 02227271 2002-02-22 70128-353 102 time step t+1, the plurality of interconnect lines L connecting the plurality of nodes N to include: a node NA having a message input interconnection for receiving a message MA, a control input interconnection for receiving a control signal CA, a direct message output interconnection to a node Np, a direct message output interconnection to a node Nj?, a direct control output interconnection to an external device G or a node and a control logic for determining whether the message MA is sent to the node Νθ or the node based on: (1) the control signal CA;(2) a location of the node NA within the plurality of interconnect lines L;and (3) a routing information contained in the message MA. 105. A network according to Claim 104, wherein: the control signal CA is sent by a node Np that is distinct from the node NA, the device G, the node Νθ, and the node Ng. 106. An interconnect apparatus comprising: a plurality of nodes N;and a plurality of interconnect lines L connecting the plurality of nodes N in a predetermined pattern, the plurality of interconnect lines L connecting the plurality of nodes N to include: CA 02227271 2002-02-22 70128-353 103 a node NA having a direct message input interconnection for receiving a message MA and having a plurality of direct message output interconnections for transmitting the message MA to a plurality of nodes including a preferred node Np being most preferred for receiving the message MA, the preferred node Np being determined only by routing information in a header of the message MA and the position of the node NA within the plurality of interconnect lines L;the preferred node Np having a plurality of direct message input interconnections for receiving a message Mp from a plurality of nodes including a priority node Ng which has priority for sending a message to the preferred node Np, the priority node Ng being determined by position of the node Ng within the plurality of interconnect lines L so that : if the node NA is the same as the node Ng, then the message MA is the message Mp and is sent from the node Na to the node Np;and if the node NA is not the same as the node Ng and the node Ng directs a message Mg to the node Np, then the message Mg is sent from the node Ng to the node Np. 107. A network capable of carrying a plurality of messages M concurrently comprising: a plurality of output ports P;a plurality of nodes N, the individual nodes N including a plurality of direct message input CA 02227271 2002-02-22 70128-353 104 interconnections and a plurality of direct message output interconnections, the individual nodes N for passing messages M to predetermined output ports of the plurality of output ports P, the predetermined output ports P being designated by the messages M;and a plurality of interconnect lines in an interconnect structure selectively coupling the nodes in a hierarchical multiple level structure arranged to include a plurality of J+l levels in an hierarchy of levels arranged from a lowest destination level Lq to a highest level Lj which is farthest from the lowest destination level Lq, the output ports P being connected to nodes at the lowest destination level Lq, the level of a node being determined entirely by the position of the node in the structure, the network including a node of the plurality of nodes N, a control signal operating to limit the number of messages that are allowed to be sent to the node to eliminate contention for the predetermined output ports of the node so that the messages M are sent through the direct message output connections of the node Ν/γ to nodes Npj that are a level L no higher than the level of the node N^, the nodes being on a path to the designated predetermined output ports P of the messages M. 108. An interconnect apparatus, comprising: a plurality of nodes;and a plurality of interconnect lines in an interconnect structure selectively coupling the nodes in a hierarchical multiple level structure arranged to include: CA 02227271 2002-02-22 70128-353 105 a plurality of J+l levels with J an integer greater than 0 in an hierarchy of levels arranged from a lowest destination level Lq to a highest level Lj with the level of a node being determined entirely by the position of the node in the structure, the interconnect structure transmitting a plurality of multiple-bit messages entering the interconnect structure unsorted through a plurality of input ports, an individual message M of the plurality of messages being self-routing, the individual message M moving in a plurality of ways including three ways which are sufficient for the message M to exit the interconnect structure through an output port designated by the message M, the three ways being: (1) the message M enters a node in the interconnect structure from a device external to the interconnect structure, the message M designating one or more designated output ports;(2) the message M moves through a node in the interconnect structure without buffering to a designated output port;and (3) the message M moves either through a node U on a level of the interconnect structure without buffering to a different node V on the same level Lfc or moves through the node U on a level L^ of the interconnect structure without buffering to a node W on a level L-[ nearer in the hierarchy to the destination level Lq than the level 109. An interconnect apparatus as claimed in Claim 108, wherein a node N^k on the level has a plurality of interconnections including: CA 02227271 2002-02-22 70128-353 106 a direct data input interconnection from a node Ngk on the level Ιψ;a direct data output interconnection to a node on the level L^;a direct data input interconnection from a node NCm on a ^m where m is greater than k, or from a device Dq external to the interconnect structure;and a direct data output interconnection to a device Dg external to the interconnect structure, or a direct data output interconnection to a node Ngj_ on the level Lj_ where k is greater than i so that the level Lj_ is closer in the hierarchy to the destination level Lq, wherein: among devices having a direct interconnection to the node N^, a precedence relationship exists for sending data to the node so that: a node on the level having a direct interconnection to the node has precedence over a device Dg where the device Dy is a node Ngi on the level Lj_ or a device De external to the interconnect structure;the precedence relationship for a message Mg to be sent from the node to the node and a message Mg to be sent from the device Dg to the node in a same time interval results in the message Μβ being sent and the message Me prevented from being sent. 110. An interconnect apparatus as claimed in Claim 108, wherein the interconnect structure: CA 02227271 2002-02-22 70128-353 107 carries messages and control signals;includes a node Ng including: a direct message input interconnection for receiving a message from a node N^;and a direct message input interconnection for receiving a message Mp from a node Np;and the node N^ has a control logic and a control input interconnection for receiving a control signal from the node Np, the control signal enforcing a precedence of the direct message input interconnection from the node Np to the node Ng over the message input interconnection from the node to the node Ng so that the node Np sends a message Mp to the node Ng and sends a control signal designating a blocking condition to the node N^, the node control logic receives the control signal C& designating the blocking condition and responds to the control signal C^ by blocking transmission of the message destined to arrive at the node Ng at the same time as the message Mp, causing the blocked message M^ to be alternatively sent to a node Nq where the node Nq is distinct from the node Ng and the node Nq is distinct from the node N^. 111. An interconnect apparatus as claimed in Claim 108, wherein the interconnect structure: carries messages and control signals;CA 02227271 2002-02-22 70128-353 108 includes a node Νβ including: a direct message input interconnection for receiving a message from a node N^, the message having a header;and a direct message input interconnection for receiving a message Mp from a node Np;and the node N^ has a control logic and a control input interconnection for receiving a control signal from the node Np, the control signal enforcing a precedence of the direct message input interconnection from the node Np to the node Np over the direct message input interconnection from the node N^ to the node Np so that a message. arriving at the node N^ in the absence of a blocking control signal (¾ in a same time interval causes the node N^ control logic to use a header of the message to determine a selected device for transmitting the message M^, in case the selected device is the node Np then the message being sent to the node Np, wherein the control logic of node N^ determines : whether, in a first condition, the node N^ has a direct output interconnection to a node Npj_ on the level i nearer in the hierarchy to the destination level Lq than the level Lfc in which the node Npi has a pathway to a designated output port designated by the message M^;and whether, in a second condition, the node Npi is unblocked by another message;and CA 02227271 2002-02-22 70128-353 109 the control logic of node N^, when the first and second conditions are satisfied, sends the message to the node Npi;and the control logic of node N^k* when the first and second conditions are not both satisfied, sends the message to a node Nq where node N^k and node are distinct and the node Nei and the node No are distinct. 112. An interconnect apparatus as claimed in Claim 108, further comprising: a plurality of output ports including a plurality of accessible output ports that are accessible to a node N^k on the level Lj^, the accessible output ports being accessible via a pathway through the interconnect nodes;and each of the accessible output ports accessible to the node N^k also being accessible to a node Nei on a level Lj_ nearer in the hierarchy to the destination level Lq than the level the node N^k having a direct output interconnection to the node Np^. 113. An interconnect apparatus as claimed in Claim 108, wherein: a node Np has a first data input interconnection from a node and a second data input interconnection from a node Np;and a control interconnection between the node and node Np resolves contention for sending messages to the node nECA 02227271 2002-02-22 70128-353 110 114. An interconnect apparatus as claimed in Claim 108, further comprising : a node Ng^ on the level having a direct data output interconnection to a node Ν/χΐ a level Li nearer in the hierarchy to the destination level Lq than the level Lfc, and having a precedence relationship with respect to a message Mg which, at a time T, moves through the node Ng and is preferentially sent to the node but is blocked from node Njx by a message Mg so that the message Mg is deflected to a node on the level distinct from node Ng^;a node Ngjç on the level having a direct data output interconnection to a node on the level Lj_, the node Ngi having a pathway through the interconnect nodes to an accessible output port accessible to the message Mg, the message Mg being deflected to pass through the node at a time Τ', a first time step following the time T that a node directs message Mg to a lower level;wherein the interconnect structure disallows the message Mg from being in a position to block the message Mg at the time Τ' . 115. A network according to Claim 108 further comprising: nodes B and C on a level Lj-χ that are nodes capable of receiving a message directly from the node A on a level Lj;devices D and E, each of which is either a node on a level Lj-N where N is greater than 1 or a device external CA 02227271 2002-02-22 70128-353 111 to the network, the node B being capable of sending a message directly to the device D, the node C being capable of sending a message directly to the device E, the device D being incapable of sending a message directly or indirectly to the device E, the device E being incapable of sending a message directly or indirectly to the device D. 116. An interconnect structure comprising: a plurality of nodes;and a plurality of interconnect lines in an interconnect structure selectively coupling the nodes in a structure, the interconnect structure transmitting a plurality of multiple-bit messages entering the interconnect structure unsorted through a plurality of input ports, an individual message M of the plurality of messages being self-routing, the interconnect structure including: a node Ng having a first data input interconnection from a node NA and a second data input interconnection from a node Np distinct from the node Na;and a control interconnection between the node NA and node Np for carrying a control signal to resolve contention for sending messages to the node Np, the control signal being supplied from the node NA or the node Np each distinct from the node Np with which messages are communicated. 117. An interconnect apparatus as claimed in Claim 116, wherein the interconnect structure : carries messages and control signals;CA 02227271 2002-02-22 70128-353 112 includes a node Np including: a direct message input interconnection for receiving a message M^ from a node N^;and a direct message input interconnection for receiving a message Mp from a node Np;and the node N^ has a control logic and a control input interconnection for receiving a control signal (¾ from the node Np, the control signal enforcing a precedence of the direct message input interconnection from the node Np to the node Np over the message input interconnection from the node N^ to the node Np so that the node Np sends a message Mp to the node Np and sends a control signal designating a blocking condition to the node N^, the node N& control logic receives the control signal designating the blocking condition and responds to the control signal by blocking transmission of the message Mj\ destined to arrive at the node Np at the same time as the message Mp, causing the blocked message to be alternatively sent to a node Ny where the node Nq is distinct from the node Np and the node Np is distinct from the node N^. 118. An interconnect apparatus as claimed in Claim 117, wherein: the message has a header;and OA 02227271 2002-02-22 70128-353 113 the message MA arriving at the node in the absence of a blocking control signal CA in a same time interval causes the node NA control logic to use a header of the message MA to determine a selected device for transmitting the message MA, in case the selected device is the node Np then the message MA being sent to the’node Ng. 119. A method of moving messages through an interconnect structure comprising: interconnecting a plurality of devices in a structure, the devices having a plurality of message input terminals and a plurality of message output terminals, a plurality of interconnect lines interconnecting the device with connections from a message output terminal of a sending device to a message input terminal of a receiving device;assigning a priority among a plurality of sending devices having output message terminals coupled to the input message terminal of a single receiving device;entering a message into the interconnect structure for transfer to one or more designated output ports;sending a message, without buffering, from a sending device to a receiving device en route to the one or more output ports using self-routing, with the sending device neither requesting of the receiving device nor receiving from the receiving device, permission to send the message to the receiving device;communicating among a plurality of sending devices that send messages to a single receiving device, a sending device with priority for sending messages to the single receiving device having a control signal output terminal CA 02227271 2002-02-22 70128-353 114 connected by an interconnect line to a control signal input terminal of a sending device without priority, the sending device with priority sending a control signal to the sending device without priority;and deflecting a message intended to be sent from a sending device without priority to an intended receiving device, the deflected message being deflected to an alternative receiving device, the alternative receiving device also being en route to the one or more output ports. 120. A method of sending data comprising: providing an interconnect apparatus including a plurality of nodes N and a plurality of interconnect lines L connecting the plurality of nodes N in a predetermined pattern;connecting the plurality of nodes N using the plurality of interconnect lines L to include: a node having a direct message input interconnection for receiving a message and having a plurality of direct message output interconnections for transmitting the message M& to a plurality of nodes including a preferred node Np being most preferred for receiving the message M^, the preferred node Np being only determined by routing information in a header of the message M^ and the position of the node within the plurality of interconnect lines L;the preferred node Np having a plurality of direct message input interconnections for receiving a message Mp from a plurality of nodes including a priority node Ng which CA 02227271 2002-02-22 70128-353 115 has priority for sending a message to the preferred node Np, the priority node Ng being determined by position of the node Ng within the plurality of interconnect lines L;if the node N^ is the same as the node Νβ, sending the message as the message Mp from the node to the node Np;and if the node N^ is not the same as the node Νβ and the node Νβ directs a message Μβ to the node Np, then sending the message Μβ from the node Np to the node Np. 121. A method of sending messages comprising: providing a network for carrying a plurality of messages M concurrently including: a plurality of output ports P;and a plurality of nodes N, the individual nodes N including a plurality of direct message input interconnections and a plurality of direct message output interconnections, the individual nodes N for passing messages M to predetermined output ports of the plurality of output ports P, the predetermined output ports P being designated by the messages M;and a plurality of interconnect lines in an interconnect structure;selectively coupling the nodes in a hierarchical multiple level structure to include a plurality of J+l levels with J an integer greater than 0 in an hierarchy of levels arranged from a lowest destination level Lq to a highest level Lj which is farthest in the hierarchy from the CA 02227271 2002-02-22 70128-353 116 lowest destination level Lq, the level of a node being determined entirely by the position of the node in the structure, the output ports P being connected to nodes at the lowest destination level Lq, including in the-network a node Ν/χ of the plurality of nodes N;limiting the number of messages M that are allowed to enter the plurality of direct message input interconnections of node to eliminate contention for the predetermined output ports of the node so that the messages M are sent through the direct message output connections of the node to nodes that are a level L no higher than the level of the node Ν^χ, the nodes Np being on a path to the designated predetermined output ports P of the messages M. 122. A method of transmitting a message through an hierarchical interconnect structure including a plurality of nodes and a plurality of interconnect lines, the method comprising : selectively coupling the nodes in an hierarchical multiple level structure arranged to include a plurality of J+l levels with J an integer greater than 0 in an hierarchy of levels arranged from a lowest destination level Lq to a highest level Lj, the level of a node being determined entirely by the position of the node in the structure;entering a plurality of messages into the interconnect structure unsorted through a plurality of input ports;moving, using self-routing, an individual message M of the plurality of messages through nodes, the message M CA 02227271 2002-02-22 70128-353 117 moving in a plurality of ways including three ways which are sufficient for the message M to exit the interconnect structure through an output port designated by the message M, the three ways including: 5 (1) entering the message M to a node in the interconnect structure from a device external to the interconnect structure, the message M designating one or more designated output ports;(2) moving the message M through a node in the 10 interconnect structure without buffering to a designated output port;and (3) ' moving the message M either through a node U on a level Ljç of the interconnect structure without buffering to a different node V on the same level L^, the 15 different node V also having a pathway to a designated output port;or moving the message M through the node U on the level of the interconnect structure without buffering to a node W on a level L| nearer in the hierarchy to the destination level Lg than the level L^. SMART & BIGGAR OTTAWA, CANADA PATENT AGENTS
Independent claims2
337 paragraphs in 106 sections, as filed
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-1MULTIPLE LEVEL MINIMUM LOGIC NETWORK
Coke S. Reed
FIELD OF INVENTION
The present invention relates to interconnection structures for computing and communication systems. More specifically, the present invention relates to multiple level interconnection structures in which control and logic circuits are minimized.
BACKGROUND OF THE INVENTION
Many advanced computing systems, including supercomputers for example, utilize multiple computational units to improve performance in what is called a parallel system. The system of interconnections among parallel computational units is an important characteristic for determining performance. One technique for interconnecting parallel computational units involves construction of a communication network similar to a telephone network in which groups of network elements are connected to switching systems. The switching systems are interconnected in a hierarchical manner so that any switching station manages a workable number of connections.
5 One disadvantage of a network connection is an increase in the latency of access to another computational unit since transmission of a message traverses several stages of a network. Typically, periods of peak activity occur in which the network is saturated with numerous messages so that many messages simultaneously contend for the use of a switching station. Various network types have been devised with amended sheet
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-2goals of reducing congestion, improving transmission speed and achieving a reasonable cost. These goals are typically attained by rapidly communicating between nodes and minimizing the number of interconnections that a node must ✓
support.
One conventional interconnection scheme is a ring of nodes with each node connected to two other nodes so that the line of interconnections forms a circle. The definition of a ring, in accordance with a standard definition of a ring network in the art of computing (IBM Dictionary of Computing. McDaniel G. ed., McGraw-Hill, Inc., 1994, p. 584) is a network configuration in which devices are connected by unidirectional transmission links to form a closed path. Another simple conventional scheme is a mesh in which each node is connected to its four nearest neighbors. The ring and mesh techniques advantageously limit the number of interconnections supported by a node. Unfortunately, the ring and mesh networks typically are plagued by lengthy delays in message communication since the number of nodes traversed in sending a message from one node to another may be quite large. These lengthy delays commonly cause a computational unit to remain idle awaiting a message in transit to the unit.
The earliest networks, generally beginning with telephone networks, utilize circuit switching in which each message is routed through the network along a dedicated path that is reserved for the duration of the communication analogous to a direct connection via a single circuit between the communicating parties. Circuit switching disadvantageously requires a lengthy setup time. Such delays are intolerable during the short and quick exchanges that take place between different computational units. Furthermore, a dedicated pathway is very wasteful of system bandwidth. One technique for solving lhe problems arising using circuit switching is called packet switching in which messages sent from one computational unit to another does not travel in a continuous stream to a dedicated circuit. Instead, each
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-3computational unit is connected to a node that subdivides messages into a sequence of data packets. A message contains an arbitrary sequence of binary digits that are preceded by addressing information. The length of the entire message is limited to a /
defined maximum length. A header containing at least the destination address and a sequence number is attached to each packet, and the packets are sent across the network. Addresses are read and packets are delivered within a fraction of a second. No circuit setup delay is imposed because no circuit is set up. System bandwidth is not wasted since there is no individual connection between two computational units. However, a small portion of the communication capacity is used for routing information, headers and other control information. When communication advances in isolated, short bursts, packet switching more efficiently utilizes network capacity. Because no transmission capacity is specifically reserved for an individual computational unit, time gaps between packets are filled with packets from other users. Packet switching implements a type of distributed multiplexing system by enabling all users to share lines on the network continuously.
Advances in technology result in improvement in computer system performance. However, the manner in which these technological advances are implemented will greatly determine the extent of improvement in performance. For example, performance improvements arising from completely optical computing strongly depend on an interconnection scheme that best exploits the advantages of optical technology.
SUMMARY OF THE INVENTION
In accordance with the present invention, a multiple level minimum logic network interconnect structure has a very high bandwidth and low latency. Control of interconnect structure switching is distributed throughout multiple nodes in the structure so that a supervisory controller providing a global control function is not
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-4necessary. A global control function is eliminated and complex logic structures are avoided by a novel data flow technique that is based on timing and positioning of messages communicating through the interconnect structure. Furthermore, the interconnect structure implements a deflection” or hot potato design in which 5 processing and storage overhead at each node is minimized by routing a message packet through an additional output-port rather than holding the packet until a desired output port is available. Accordingly, the usage of buffers at the nodes is eliminated.
Elimination of a global controller and buffering at the nodes greatly reduces the amount of control and logic structures in the interconnect structure, simplifying 10 overall control components and network interconnect components, improving speed performance of message communication and potentially reducing interconnection costs substantially. Implementation of the interconnect structure is highly flexible so that fully electronic, fully optical and mixed electronic-optical embodiments are achieved. An implementation using all optical switches is facilitated by nodes 15 exploiting uniquely simple logic and elimination of buffering at the nodes.
The multiple level minimum logic network interconnect architecture is used for various purposes. For example, in some embodiments the architecture is used as an interconnect structure for a massively parallel computer such as a supercomputer. 20 In other exemplary embodiments, the architecture forms an interconnect structure linking a group of workstations, computers, terminals, ATM machines, elements of a national flight control system and the like. Another usage is an interconnect structure in various telecommunications applications or an interconnect structure for numerous schedulers operating in a business main frame.
In accordance with one aspect of the present invention, an interconnect apparatus includes a plurality of nodes and a plurality of interconnect lines selectively connecting the nodes in a multiple level structure in which the levels include a richly interconnected collection of rings. The multiple level structure includes a plurality of J+l levels in a hierarchy of levels and a plurality of 2<sup>J</sup>K nodes at each level. If
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-5- ’ integer K is an odd number, the nodes on a level M are situated on 2<sup>J</sup>'<sup>M</sup> rings with each ring including 2<sup>M</sup>K nodes. Message data leaves the interconnect structure from nodes on a level zero. Each node has multiple communication terminals. Some are /
message data input and output terminals. Others are control input and output terminals. For example, a node A on level 0, the innermost level, receives message data from a node B on level 0 and also receives message data from a node C on level 1. Node A sends message data to a node D on level 0 and also sends message data to a device E that is typically outside the interconnect structure. One example of a device E is an input buffer of a computational unit. Node A receives a control input signal from a device F which is commonly outside the interconnect structure. An example of a device F is an output buffer of a computational unit. Node A sends a control signal to a node G on level 1.
All message data enters the interconnect structure on an outermost level J. For example, a node A on level J, the outermost level, receives message data from a node B on level J and also receives message data from a device C that is outside the interconnect structure. One example of device C is an output buffer of a computational unit. Node A sends message data to a node D on level J and also sends message data to a node E on level J-l. Node A receives a control input signal from a node F on level J-l. Node A sends a control signal to a device G that is typically outside the interconnect structure. An example of a device G is an output buffer of a computational unit.
Nodes between the innermost level 0 and the outermost level J communicate message data and control signals among other nodes. For example, a node A on a level T that is neither level 0 or level J receives message data from a node B on level T and also receives message data from a node C on level T+l. Node A sends message data to a node D on level T and also sends message data to a node E on
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-6level T-l. Node A receives a control input signal from a node F on level T-l. Node A sends a control signal to a node G on level TH-1.
Level M has 2<sup>LM</sup> rings, each containing 2<sup>M</sup>K nodes for a total of 2<sup>J</sup>K nodes on level M. Specifically:
Level 0 has 2<sup>J</sup> rings; each containing 2°K = K nodes for a total of 2<sup>J</sup>K nodes on level 0.
Level 1 has 2<sup>14</sup> rings, each containing 2*K = 2K nodes for a total of 2<sup>T</sup>K nodes on level 1.
Level 2 has 2<sup>J-2</sup> rings, each containing 2<sup>2</sup>K = 4K nodes for a total of 2<sup>J</sup>K nodes on level M.
Level J-2 has 2<sup>1<r</sup>‘<sup>2></sup> = 4 rings, each containing 2<sup>σ_2)</sup>Κ nodes for a total of 2<sup>J</sup>K nodes on level J-2.
Level J-l has 2<sup>J_(M)</sup> = 2 rings, each containing 2^<sup>-1</sup>^ nodes for a total of 2<sup>J</sup>K. nodes on level J-l.
Level J has 2<sup>J_I</sup> = 1 ring containing 2^<sup>-1</sup>^ nodes for a total of 2<sup>J</sup>K nodes on level J.
For a ring R<sub>T</sub> on a level T which is not the outermost level J, then one ring R<sub>T+i</sub> on level T+l exists such that each node A on ring R<sub>T</sub> receives data from a node B on ring R<sub>T</sub> and a node C on ring R<sub>T+1</sub>. For a ring R<sub>T</sub> on a level T which is not the innermost level 0, then there exist exactly two rings RIjm and R2<sub>T</sub>_! on level T-l such that a node A on ring R<sub>T</sub> sends message data to a node D on ring R<sub>T</sub> and a node E on either ring R1<sub>T</sub>_! or ring R2TJ. A message on any level M of the interconnect structure can travel to two of the rings on level M-l and is eventually able to travel to 2<sup>M</sup> of the rings on level 0.
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-7In the following discussion a predecessor of a node sends message data to that node. An immediate predecessor sends message data to a node on the same ring. A successor of a node receives message data from that node. An immediate successor receives message data to a node on the same ring.
For a node A<sub>RT</sub> on ring R<sub>T</sub> on level T, there are nodes B<sub>RT</sub> and D<sub>RT</sub> on ring R<sub>T</sub> of level T such that node B<sub>RT</sub> is an immediate predecessor of node A<sub>RT</sub> and node D<sub>rt</sub> is an immediate successor of node A<sub>RT</sub>. Node A<sub>RT</sub> receives message data from node B<sub>rt</sub> and sends message data to node D<sub>RT</sub>. Node A<sub>RT</sub> receives message data from a device C that is not on the ring R<sub>T</sub> and sends data to a device E that is not on ring R<sub>T</sub>. If the level is not the innermost level 0, then device E is a node on level ΤΙ and there is an immediate predecessor node F on the same ring as device E. Node A<sub>rt</sub> receives control information from device F. If node A<sub>RT</sub> is on node T equal to zero, then device E is outside the interconnect structure and device E sends control information to node A<sub>RT</sub>. For example, if device E is an input buffer of a computational unit, then the control information from device E to node A<sub>RT</sub> indicates to node A<sub>RT</sub> whether device E is ready to receive message data from node A<sub>RT</sub>. Node D<sub>rt</sub> receives message data from a device G that is not on ring R<sub>T</sub>. Node A<sub>RT </sub>sends a control signal to device G.
Control information is conveyed to resolve data transmission conflicts in the interconnect structure. Each node is a successor to a node on the adjacent outer level and an immediate successor to a node on the same level. Message data from the immediate successor has priority. Control information is send from nodes on a level to nodes on the adjacent outer level to warn of impending conflicts.
When the levels are evenly spaced and the nodes on each ring and each level are evenly spaced, the interconnect structure forms a three-dimensional cylindrical
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M-3240 PCT -8structure. The interconnect structure is fully defined by designating the interconnections for each node A of each level T to devices or nodes B, C, D, E, F and G. Each node or device has a location designated in three-dimensional cylindrical coordinates (r, Θ, z) where radius r is an integer which specifies the 5 cylinder number from 0 to J, angle Θ is an integer multiple of 2π/Κ, which specifies the spacing of nodes around the circular cross-section of a cylinder from 0 to K-l, and height z is a binary integer which specifies distance along the z-axis from 0 to 2<sup>s</sup>1. Height z is expressed as a binary number because the interconnection between nodes in the z-dimension is most easily described as a binary digit manipulation. On 10 the innermost level 0, one ring is spanned in one pass through the angles θ from 0 to
K-l and each height z designates a ring. On level 1, one ring is spanned in two passes through the angles Θ and two heights z are used to designate one ring. The ring structure proceeds in this manner through the outermost ring J in which one ring is spanned in all 2<sup>J</sup> heights along the z-axis.
Node A on a ring R receives message data from a node B, which is an immediate predecessor of node A on ring R. For a node A located at a node position Ν(γ,Θ,ζ), node B is positioned at N(r,(9-l)mod K,H<sub>r</sub>(z)) on level r. (G-l)mod K is equal K when Θ is equal to 0 and equal to Θ-l otherwise. The conversion of z to 2 0 H<sub>r</sub>(z) on a level r is described for z = [z<sub>K1</sub>, Zj_<sub>2</sub>, . . , z^, . . , z<sub>2</sub>, z<sub>H</sub> ZoJ by reversing the order of low-order z bits from z^ to zj into the form z = [zj_<sub>1t</sub> Zj.<sub>2</sub>, . . , Zf, Zo, z<sub>b</sub> Z2, ., Zr-iJ, subtracting one (modulus 2<sup>1</sup>) and reversing back the modified low-order z bits.
Node A also receives message data from a device C which is not on level r.
If node A is positioned on the outermost level r—J, then device C is outside of the interconnect structure. If node A is not positioned on the outermost level, then device C is a node located at position N(r+l,(0-l)mod K,z) on level r-f-1.
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-9Node A sends message data to a node D, which is an immediate successor to node A on ring R. Node D is located at node position N(r,(0 + l)mod K,h<sub>r</sub>(z)) on level r. (0+ l)mod K is equal 0 when Θ is equal to K-l and equal to 0+1 otherwise. The conversion of z to h<sub>r</sub>(z) on a level r is described for z = [ζ<sub>Μ</sub>, ζ<sub>Κ2ϊ</sub> . . , Zj., z^, . . , Z2, z<sub>H</sub> Zq] by reversing the order of low-order z bits from z^ to ζθ] into the form z — [zj-b <sup>z</sup>J-2» · · » Zj., Zq, z<sub>I?</sub> Z2, . ., Zf-i], adding one (modulus 2<sup>1</sup>) and reversing back the low-order z bits.
Node A also sends message data to a device E that is not on the same level r as node A. if node A is on the innermost level r=0, node A(r,0,z) is interconnected with a device (e.g. a computational unit) outside of the interconnect structure. Otherwise, node A is interconnected to send message data to device E, which is a node located at node position N(r-1 ,(0+ l)mod K,z) on level r-1.
Node A receives control information from a device F. If node A is on the innermost level r=0, the device F is the same as device E. If node A is not on the innermost level, device F is a node which is distinct from the device E. Node F is located at node position ΝζΓ-Ι,θ,Η^ίζ)) on level r-1.
Node A sends control information to a device G. If node A is on the outermost level r=J, then device G is positioned outside of the interconnect structure. Device G is a device, for example a computational unit, that sends message data to node D. If node A is not positioned on level r=J, then device G is a node which is located at node position N(r+l,0,h<sub>r+1</sub>(z)) on level r+1 and device G sends message data to node D.
In accordance with a second aspect of the present invention, a method is shown of transmitting a message from a node N to a target destination in a first, a
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M-3240 PCT Ύ·
-10second and a third dimension of three dimensions in an interconnect structure arranged as a plurality of nodes in a topology of the three dimensions. The method includes the steps of determining whether a node en route to the target destination in the first and second dimensions and advancing one level toward the destination level of the third dimension is blocked by another message, advancing the message one level toward the destination level of* the third dimension when the en route node is not blocked and moving the message in the first and second dimensions along a constant level in the third dimension otherwise. This method further includes the step of specifying the third dimension to describe a plurality of levels and specifying the first and second dimensions to described a plurality of nodes on each level. A control signal is sent from the node en route to the node N on a level q in the third dimension, the control signal specifying whether the node en route is blocked.
Transmission of a message is timed using a global clock specifying timing intervals to keep integral time modulus the number of nodes at a particular cylindrical height, the global clock time interval being equal to the second time interval and the first time interval being smaller than the global time interval. A first time interval a is set for moving the message in only the first and second dimensions. A second time interval a - β is set for advancing the message one level toward the destination level. A third time interval is set for sending the control signal from the node en route to the node N, the third time interval being equal to β.
In accordance with a third aspect of the present invention, a method is shown of transmitting a message from an input device to an output device through an interconnect structure. The message travels through the interconnect structure connecting a plurality of nodes in a three dimensional structure. The message has a target destination corresponding to a target ring on level 0 of the interconnect structure. A message M at a node N on level T en route to a target ring on level 0 advances to a node N’ on level T-l so long as the target ring is accessible from node N’ and no other higher priority message is progressing to node Ν’ to block the
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-11progress of message M. Whether the target ring is accessible from node N’ is typically efficiently determined by testing a single bit of a binary code designating the target ring. Whether a higher priority message is blocking the progress of message M is efficiently determined using timed control signals. If a message is blocked at a time t, the message is in position to progress to the next level at time t+2. If a message is blocked by a message M* on level T-l, then a limited time duration will transpire before the message M' is able to block message M again.
A global clock controls traffic flow in the interconnect structure. Data flow follows rules that allow much of the control information to be hidden” in system timing so that, rather than encoding all control information in a message packet header, timing considerations convey some information. For example, the target ring is encoded in the message packet header but, in some embodiments of the interconnect structure, designation of the target computational unit is determined by the timing of arrival of a message with respect to time on the global clock.
The disclosed multiple level interconnect structure has many advantages. One advantage is that the structure is simple, highly ordered and achieves fast and efficient communication for systems having a wide range of sizes, from small systems to enormous systems.
In addition, the interconnect structure is highly advantageous for many reasons. The interconnect structure resolves contention among messages directed toward the same node and ensures that a message that is blocked makes a complete tour of the messages at a given angle on a level before the blocking message is in position to block again. In this manner, a message inherently moves to cover all possible paths to the next level. A blocking message typically proceeds to subsequent levels so that overlying messages are not blocked for long.
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-12BRIEF DESCRIPTION OF THE DRAWINGS
The features of the invention believed to be novel are specifically set forth in the appended claims. However, the invention itself, both as to its structure and method of operation, may best be understood by referring to the following description and accompanying drawings.
Figures 1A, IB, 1C and ID are abstract three-dimensional pictorial illustrations of the structure of an embodiment of a multiple level minimum logic interconnect apparatus.
Figure 2 is a schematic diagram of a node, node terminals and interconnection lines connected to the terminals.
Figures 3A, 3B and 3C are schematic block diagrams that illustrate interconnections of nodes on various levels of the interconnect structure.
Figure 4 is an abstract schematic pictorial diagram showing the topology of levels of an interconnect structure.
Figure 5 is an abstract schematic pictorial diagram showing the topology of nodes of an interconnect structure.
Figure 6 is an abstract schematic pictorial diagram which illustrates the manner in which nodes of the rings on a particular cylindrical level are interconnected.
Figure 7 illustrates interconnections of a node on level zero.
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-13Figure 8 depicts interconnections of a node on level one.
Figure 9 depicts interconnections of a node on level two.
?
Figure 10 depicts interconnections of a node on level three.
Figure 11 is an abstract schematic pictorial diagram which illustrates interconnections between devices and nodes of a ring on the low level cylinder.
Figure 12 is an abstract schematic pictorial diagram which illustrates interconnections among nodes of two adjacent cylindrical levels.
Figure 13 is an abstract schematic pictorial diagram showing interconnections of nodes on cylindrical level one.
Figure 14 is an abstract schematic pictorial diagram showing interconnections of nodes on cylindrical level two.
Figure 15 is an abstract schematic pictorial diagram showing interconnections of nodes on cylindrical level three.
Figure 16 is an abstract schematic pictorial diagram illustrating the interaction of messages on adjacent levels of an embodiment of the interconnection structure.
Figure 17 is a timing diagram which illustrates timing of message communication in the described interconnect structure.
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-14Figure 18 is a pictorial representation illustrating the format of a message packet including a header and payload.
Figure 19 is a pictorial diagram which illustrates the operation of a lithium niobate node, a first exemplary node structure.
Figure 20 is a pictorial diagram which illustrates the operation of a nonlinear optical loop mirror (NOLM), a second exemplary node structure.
Figure 21 is a pictorial diagram which illustrates the operation of a terahertz optical asymmetrical demultiplexer (TOAD) switch, a third exemplary node structure.
Figure 22 is a pictorial diagram showing the operation of a regenerator utilizing a lithium niobate gate.
Figure 23 is an abstract schematic pictorial diagram illustrating an alternative embodiment of an interconnect structure in which devices issue message packets to multiple nodes.
Figure 24 is an abstract schematic pictorial diagram illustrating an alternative embodiment of an interconnect structure in which devices receive message packets from multiple nodes.
Figure 25 is an abstract schematic pictorial diagram illustrating an alternative embodiment of an interconnect structure in which devices issue message packets to nodes at various interconnect levels.
DETAILED DESCRIPTION
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-15Referring to Figures 1A, IB, 1C and ID, an embodiment of a multiple level minimum logic interconnect apparatus 100 includes multiple nodes 102 which are / connected in a multiple level interconnect structure by interconnect lines 104, The multiple level interconnect structure is shown illustratively as a three-dimensional structure to facilitate understandings
The nodes 102 in the multiple level interconnect structure are arranged to include multiple levels 110, each level 110 having a hierarchical significance so that, after a message is initiated in the structure, the messages generally move from an initial level 112 to a final level 114 in the direction of levels of a previous hierarchical significance 116 to levels of a subsequent hierarchical significance 118. Illustratively, each level 110 includes multiple structures which are called rings 120. Each ring 120 includes multiple nodes 102. The term rings” is used merely to facilitate understanding of the structure of a network in the abstract in which visualization of the structure as a collection of concentric cylindrical levels 110 is useful.
The different Figures 1A, IB, 1C and ID are included to more easily visualize and understand the interconnections between nodes. Figure 1A illustrates message data transmission interconnections between nodes 102 on the various cylindrical levels 110. Figure IB adds a depiction of message data transmission interconnections between nodes 102 and devices 130 to the interconnections illustrated in Figure 1A. Figure 1C further shows message data interconnections between nodes 102 on different levels. Figure ID cumulatively shows the interconnections shown in Figures 1A, IB and 1C in addition to control interconnections between the nodes 102.
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-16The actual physical geometry of an interconnect structure is not to be limited to a cylindrical structure. What is important is that multiple nodes are arranged in a first class of groups and the first class of groups are arranged into a second class of /
groups. Reference to the first class of groups as rings and the second class of groups 5 as levels is meant to be instructive but not limiting.
The illustrative interconnect apparatus 100 has a structure which includes a plurality of J+l levels 110. Each level 110 includes a plurality of 2<sup>T</sup>K nodes 102. Each level M contains 2<sup>J_M</sup> rings 120, each containing 2<sup>M</sup>K nodes 102. The total 10 number of nodes 102 in the entire structure is (J+1)2<sup>J</sup>K. The interconnect apparatus 100 also includes a plurality 2<sup>J</sup>K devices 130. In the illustrative embodiment, each device of the 2<sup>J</sup>K devices 130 is connected to a data output port of each of the K nodes 102 in each ring of the 2<sup>J</sup> rings of the final level 114. Typically, in an interconnect structure of a computer a device 130 is a computational unit such as a 15 processor-memory unit or a cluster of processor-memory units and input and output buffers.
Referring to Figure 2, an interconnect structure 200 of a node 102 has three input terminals and three output terminals. The input terminals include a first data 20 input terminal 210, a second data input terminal 212 and a control input terminal 214. The output terminals include a first data output terminal 220, a second data output terminal 222 and a control output terminal 224. The data input and output terminals of a node communicate message data with other nodes. The control terminals communicate control bits with other nodes for controlling transmission of 25 message data. The number of control bits for controlling message transmission is efficiently reduced since much of the logic throughout the interconnect structure 200 is determined by timing of the receipt of control bits and message data in a manner to be detailed hereinafter. Only one control bit enters a node and only one control bit leaves at a given time step. Messages are communicated by generating a clock signal amended sheet
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M-3240 PCT - -17for timing time units. Message transmission is controlled so that, during one time unit, any node 102 receives message data from only one input terminal of the data input terminals 212 and 214. Since, a node 202 does not have a buffer, only one of the node’s output ports is active in one time unit.
Referring to Figures 3 through 16, the topology of an interconnect structure 300 is illustrated. To facilitate understanding, the structure 300 is illustrated as a collection of concentric cylinders in three dimensions r, Θ and z. Each node or device has a location designated (r, Θ, z) which relates to a position (r, 2πθ/Κ, z) in three-dimensional cylindrical coordinates where radius r is an integer which specifies the cylinder number from 0 to J, angle θ is an integer which specifies the spacing of nodes around the circular cross-section of a cylinder from 0 to K-l, and height z is a binary integer which specifies distance along the z-axis from 0 to 2^1. Height z is expressed as a binary number because the interconnection between nodes in the zdimension is most easily described as a manipulation of binary digits. Accordingly, an interconnect structure 300 is defined with respect to two design parameters J and K.
Figures 3A, 3B and 3C are schematic block diagrams that show interconnections of nodes on various levels of the interconnect structure. Figure 3A shows a node Arj 320 on a ring R of outermost level J and the interconnections of node Arj 320 to node Brj 322, device C 324, node Drj 326, node 328, node Frçm) and device G 332. Figure 3B shows a node A<sub>RT</sub> 340 on a ring R of a level T and the interconnections of node A<sub>RT</sub> 340 to node Br<sub>T</sub> 342, node C<sub>R(</sub>j<sub>+1)</sub> 344, node D<sub>rt</sub> 346, node E<sub>R(</sub>t_i) 348, node F<sub>R(</sub>j,p 350 and node G<sub>R(</sub>j<sub>+</sub> 352. Figure 3C shows a node A<sub>R0</sub> 360 on a ring R of innermost level 0 and the interconnections of node A<sub>ro</sub> 360 to node B<sub>R0</sub> 362, node C<sub>R1</sub> 364, node D<sub>R0</sub> 366, device E 368 and node G<sub>r1</sub> 372.
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-18In Figures 3A, 3B and 3C interconnections are shown with solid lines with arrows indicating the direction of message data flow and dashed lines with arrows indicating the direction of control message flow. In summary, for nodes A, B and D and nodes or devices C, E, F, G:
(1) A is on level T.
(2) B and C send data to A.
(3) D and E receive data from A.
(4) F sends a control signal to A.
(5) G receives a control signal from A.
(6) B and D are on level T.
(7) B is the immediate predecessor of A.
(8) D is the immediate successor to A.
(9) C, E, F and G are not on level T.
The positions in three-dimensional cylindrical notation of the various nodes and devices is as follows:
(10) A is positioned at node N(r, Θ, z).
(11) B is positioned at node N(r, Θ-1, H<sub>T</sub>(z)).
(12) C is either positioned at node N(r+1, θ-l, z) or is outside the interconnect structure.
(13) D is positioned at node N(r, Θ+1, h^z)).
(14) E is either positioned at node N(r-1, Θ +1, z) or is outside the interconnect structure and the same as device F.
(15) F is either positioned at node N(r-1, Θ, H^z)) or is outside the interconnect structure and the same as device E.
(16) G is either positioned at node N(r4-1, θ, h<sub>T</sub>(z)) or is outside the interconnect structure.
In this notation, (G-l)mod K is equal K when Θ is equal to 0 and equal to Θ-1 otherwise. The conversion of z to H<sub>r</sub>(z) on a level r is described for z = [ζ<sub>Μ</sub>, zj_<sub>2</sub>, .
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-19- , Zr, Zr-i, . . , Z2» Zb Zol by reversing the order of low-order z bits from z^ to Zq] into the form z = [z<sub>J4</sub>, Zj.<sub>2</sub>, . . , z,., ζθ, Ζχ, . ., z^], subtracting (modulus 2<sup>1</sup>) and reversing back the low-order z bits. Similarly, (9+l)mod K is equal 0 when 9 is
Λ equal to K-l and equal to Θ+1 otherwise. The conversion of z to h<sub>r</sub>(z) on a level r is described for z = [z<sub>J4</sub>, zj_<sub>2</sub>, · · , Zc, z^, . . , Z2, z<sub>b</sub> Zq] by reversing the order of low-order z bits from z^i to Zq into'the form z = [zj.<sub>b</sub> z<sub>P2</sub>, . . , Zf, Zq, z<sub>b</sub> z<sub>2</sub>, . ., J, adding (modulus 2<sup>r</sup>) and reversing back the low-order z bits.
Referring to Figure 4, concentric cylindrical levels zero 310, one 312, two 314 and three 316 are shown for a J=3 interconnect structure 300 where level 0 refers to the innermost cylindrical level, progressing outward and numerically to the outermost cylindrical level 3. A node 102 on a level T is called a level T node.
An interconnect structure has J+l levels and 2<sup>J</sup>K nodes on each level. Referring to Figure 5, the design parameter K is set equal to 5 so that the interconnect structure 300 has four levels (J+l =3+1 =4) with 40 (2<sup>J</sup>K = (2<sup>3</sup>)5 = 40) nodes on each level.
Referring to Figure 6, the interconnect structure is fully defined by designating the interconnections for each node A 530 of each level T to devices or nodes B 532, C 534, D 536, E 538, F 540 and G 542.
Node A(r,0,z) 530 is interconnected with an immediate predecessor node B(r,(9-l)mod K,H<sub>r</sub>(z)) 532 on level r. If node A(r,9,z) 530 is on the outermost level r=J, node A(r,9,z) 530 is interconnected with a device (e.g. a computational unit of a computer) outside of the interconnect structure. Otherwise, node A(r,9,z) 530 is interconnected with a predecessor node C(r+l,(9-l)mod K,z) 534 on level r+1.
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-20Node A(r,9,z) 530 is interconnected with an immediate successor node D(r,(9+l)mod K,h<sub>r</sub>(z)) 536 on level r. If node A(r,6,z) 530 is on the innermost level r=0, node A(r,9,z) 530 is intercpnnected with a device (e.g. a computational unit) outside of the interconnect structure. Otherwise, node A(r,9,z) 530 is interconnected with a successor node E(r-l,(9+l)mod K,z) 538 on level r-1 to send message data.
If node A(r,9,z) 530 is on the innermost level r=0, node A(r,9,z) 530 is interconnected with a device (e.g. a computational unit) outside of the interconnect structure. Otherwise, node A(r,9,z) 530 is interconnected with a node F(r-l,9,H<sub>r</sub>_ i(z)) 540 on level r-1 which supplies a control input signal to node A(r,9,z) 530.
If node A(r,9,z) 530 is on the outermost level r=J, node A(r,9,z) 530 is interconnected with a device (e.g. a computational unit) outside of the interconnect structure. Otherwise, node A(r,9,z) 530 is interconnected with a node G(r-hl,9,h<sub>r+1</sub>(z)) 542 on level r+1 which receives a control output signal from A(r,9,z) 530.
Specifically, the interconnections of a node A for the example of an interconnect structure with interconnect design parameters J=3 and K=5 are defined for all nodes on a ring. Every ring is unidirectional and forms a closed curve so that the entire structure is defined by designating for each node A, a node D that receives data from node A.
Referring to Figure 7 in conjunction with Figure 6, interconnections of a node A on level zero are shown. Node A(0,9,z) 530 is interconnected to receive message data from immediate predecessor node B(0,(9-l)mod 5,z) 532 on level 0 and to send message data to immediate successor node D(0,(9 + l)mod 5,z) 536 on
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-21level 0. Although the interconnection term in the second dimension for nodes B and D is previously defined as H<sub>r</sub>(z) and h<sub>r</sub>(z), respectively, on level zero, H<sub>r</sub>(z) and h<sub>r</sub>(z) are equal to z. Node Α(0,θ,ζ) 530 is also interconnected to receive message data z from predecessor node C(l,(0-l)mod 5,z) 534 on level 1 and to send message data to a device E(0,z) 538. Node A(0,G,z) 530 is interconnected to receive a control input signal from a device F((0-l)mod 5,z) 540 and to send a control output signal to node GilAh/z)) 542 on level 1.
Referring to Figure 8 in conjunction with Figure 6, interconnections of a node A on level one are shown. Node Α(Ι,θ,ζ) 530 is interconnected to receive message data from immediate predecessor node B(l,(0-l)mod 5,Hi(z)) 532 on level and to send message data to immediate successor node D(1,(0+ l)mod 5,11^)) 536 on level 1. Height z is expressed as a binary number (base 2) having the form [z2,z<sub>n</sub>zo]. For level one, when z is ^,ζ^Ο] then h/z) and Hj(z) are both [z^z^l]. When z is [ζ^,Ι] then hj(z) and H/z) are both [Ζχ,Ζι,Ο]. Node A(l,0,z) 530 is also interconnected to receive message data from predecessor node C(2,(0-l)mod 5,z) 534 on level 2 and to send message data to successor node E(O,(0+l)mod 5,z) 538 on level 0. Node A(1 ,θ,ζ) 530 is interconnected to receive a control input signal from a node F(O,0,Hj(z)) 540 on level zero and to send a control output signal to node G(2,0,h<sub>2</sub>(z)) 542 on level 2.
Referring to Figure 9 in conjunction with Figure 6, interconnections of a node A on level two are shown. Node A(2,0,z) 530 is interconnected to receive message data from immediate predecessor node B(2,(0-l)mod 5,H<sub>2</sub>(z)) 532 on level and to send message data to immediate successor node D(2,(0+l)mod 5,h<sub>2</sub>(z)) 536 on level 2. Height z is expressed as a binary number (base 2) having the form [z^z^Zq]. For level two, when z is [ζ^Ο,Ο] then h<sub>2</sub>(z) is [ζχ,Ι,Ο] and H<sub>2</sub>(z) is [z2,l,1]. When z is [z^O, 1] then h<sub>2</sub>(z) is [Ζχ,Ι,Ι] and H<sub>2</sub>(z) is [z^, 1,0]. When z is
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-22[Z2,1,O] then h<sub>2</sub>(z) is [ζ^Ο,Ι] and H<sub>2</sub>(z) is [ζ^Ο,Ο]. When z is [2^,1,1] then h<sub>2</sub>(z) is [2^,0,0] and H<sub>2</sub>(z) is [2^,0,1]. Node A(2,9,z) 530 is also interconnected to receive message data from predecessor node C(3,(9-l)mod 5,z) 534 on level 3 and to send message data to successor node E(l,(0+l)mod 5,z) 538 on level 1. Node A(2,0,z) 530 is interconnected to receive a control input signal from a node F(l,9,H<sub>2</sub>(z)) 540 on level 1 and to send a control output signal to node G(3,0,h<sub>3</sub>(z)) 542 on level 3.
Referring to Figure 10 in conjunction with Figure 6, interconnections of a node A on level three are shown. Node A(3,0,z) 530 is interconnected to receive message data from immediate predecessor node B(3,(0-l)mod 5,H<sub>3</sub>(z)) 532 on level 3 and to send message data to immediate successor node D(3,(9-Fl)mod 5,h<sub>3</sub>(z)) 536 on level 3. For level three, when z is [0,0,0] then h<sub>3</sub>(z) is [1,0,0] and H<sub>3</sub>(z) is
[1.1.1] . When z is [0,0,1] then h<sub>3</sub>(z) is [1,0,1] and H<sub>3</sub>(z) is [1,1,0]. When zis
[0,1,0] then h<sub>3</sub>(z) is [1,1,0] and H<sub>3</sub>(z) is [1,0,0], When z is [0,1,1] then h<sub>3</sub>(z)is
[1.1.1] and H<sub>3</sub>(z) is [1,0,1]. When z is [1,0,0] then h<sub>3</sub>(z) is [0,1,0] and H<sub>3</sub>(z)is
[0,0,0]. When z is [1,0,1] then h<sub>3</sub>(z) is [0,1,1] and H<sub>3</sub>(z) is [0,0,1]. When zis
[1,1,0] then h<sub>3</sub>(z) is [0,0,1] and H<sub>3</sub>(z) is [0,1,0]. When z is [1,1,1] then h<sub>3</sub>(z)is
[0,0,0] and H<sub>3</sub>(z) is [0,1,1].
Node A(3,9,z) 530 is also interconnected to receive message data from predecessor node C(4,(9-l)mod 5,z) 534 on level 4 and to send message data to successor node E(2,(0+l)mod 5,z) 538 on level 2. Node A(3,0,z) 530 is interconnected to receive a control input signal from a node F(2,0,H<sub>3</sub>(z)) 540 on level 2 and to send a control output signal to node G(4,9,h<sub>4</sub>(z)) 542 on level 4.
Figure 11 illustrates interconnections between devices 130 and nodes 102 of a ring 120 on the cylindrical level zero 110. In accordance with the description of the interconnect structure 200 of a node 102 discussed with respect to Figure 2, a node 102 has three input terminals and three output terminals, including two data input terminals and one control input terminal and two data output terminals and one
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-23control output terminal. In a simple embodiment, a device 130 has one data input terminal 402, one control bit input terminal 404, one data output terminal 406 and one control bit output terminal 408.
/
Referring to Figure 11, nodes 102 at the lowest cylindrical level 110, specifically nodes Ν(Ο,θ,ζ), are connected to devices CU(G,z). In particular, the data input terminal 402 of devices CU(G,z) are connected to the second data output terminal 222 of nodes Ν(0,θ,ζ). The control bit output terminal 408 of devices CU(G,z) are connected to the control input terminal 214 of nodes N(0,G,z).
io
The devices CU(G,z) are also connected to nodes N(J,G,z) at the outermost cylinder level. In particular, the data output terminal 406 of devices CU(G,z) are connected to the second data input terminal 212 of nodes N(J,G,z). The control bit input terminal 404 of devices CU(G,z) are connected to the control output termined 15 224 of nodes N(0,G,z). Messages are communicated from devices CU(G,z) to nodes
N(J,G,z) at the outermost cylindrical level J. Then messages move sequentially inward from the outermost cylindrical level J to level J-l, level J-2 and so forth unit the messages reach level 0 and then enter a device. Messages on the outermost cylinder J can reach any of the 2<sup>J</sup> rings at level zero. Generally, messages on any 2 0 cylindrical level T can reach a node on 2<sup>T</sup> rings on level zero.
Figure 12 illustrates interconnections among nodes 102 of two adjacent cylindrical levels 110. Referring to Figure 12 in conjunction with Figure 2, nodes 102 at the T cylindrical level 110, specifically nodes N(T,G,z) 450, have terminals 25 connected to nodes on the T level, the T+l level and the T-i level. These connections are such that the nodes N(T,G,z) 450 have one data input terminal connected to a node on the same level T and one data input terminal connected to another source, usually a node on the next outer level T4-1 but for nodes on the
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-24outermost level J, a device is a source. In particular, nodes Ν(Τ,θ,ζ) 450 have a first data input terminal 210 which is connected to a first data output terminal 220 of nodes N(T+Ι,θ-l,z) 452. Also, nodes N(T,0,z) 450 have a first data output terminal 220 which is connected to a first data input terminal 210 of nodes N(Tl,0+l,z)454.
The nodes N(T,0,z) 450 also have a second data input terminal 212 and a second data output terminal 222 which are connected to nodes 102 on the same level T. The second data input terminal 212 of nodes N(T,0,z) 450 are connected to the second data output terminal 222 of nodes Ν^Γ,θ-Ι,Η-ρίζ)) 456. The second data output terminal 222 of nodes Ν(Τ,θ,ζ) 450 are connected to the second data input terminal 212 of nodes N(T,0+l,H<sub>T</sub>(z)) 458. The cylinder height designation Ηψζζ) is determined using an inverse operation of the technique for determining height designation h-r(z). The interconnection of nodes from cylindrical height to height (height z to height Ηψ(ζ) and height h^z) to height z) on the same level T is precisely defined according to a height transformation technique and depends on the particular level T within which messages are communicated. Specifically in accordance with the height transformation technique, the height position z is put into binary form where z = z^<sup>1</sup>'<sup>1</sup> + Zj_22<sup>j</sup>’<sup>2</sup> + ...+ Zy2<sup>T</sup> + 2^2<sup>7-1</sup> + ...+ z^<sup>1</sup> + Zo2°. A next height position hT(z) is determined using a process including three steps. First, binary coefficients starting with coefficient Zq, up to and but not including coefficient zp are reversed in order while coefficients Zj and above are kept the same. Thus, after the first step the height position becomes ζ^Σ<sup>1-1</sup> + zj_22<sup>J</sup>'<sup>2</sup> +...+ zT2<sup>T</sup> + Zo2° + ζχ2<sup>{</sup> + ...+ Zr_22<sup>T</sup>'<sup>2</sup> + 2^2™. Second, an odd number modulus 2<sup>T</sup>, for example one, is added to the height position after inversion. Third, circularity of the height position is enforced by limiting the inverted and incremented height position by modulus 2<sup>T</sup>. Fourth, the first step is repeated, again inverting the binary coefficients below the z<sup>1</sup> coefficient of the previously inverted, incremented and limited height position. The inverse operation for deriving height descriptor Ht(z) is
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-25- determined in the same manner except that, rather than adding the odd number modulus 2 to the order-inverted bit string, the same odd number modulus 2 is added to the order-inverted bit string.
/
The interconnection between nodes 102 on the same level is notable and highly advantageous for many reasons. For example, the interconnection structure resolves contention among messages directed toward the same node. Also, the interconnection structure ensures that a message on a particular level that is blocked by messages on the next level makes a complete tour of the messages on that level before any message is in position to block again. Thus a message inherently moves to cover all possible paths to the next level. Furthermore, a blocking message must cycle through all rings of a level to block a message twice. Consequently, every message is diverted to avoid continuously blocking other messages. In addition, blocking messages typically proceed to subsequent levels so that overlying messages are not blocked for long.
When messages are sent from second data output terminal 222 of a node N(T,0,z) 450 to a second data input terminal 212 of a node N(T,0+1,11^)), a control code is also sent from a control output terminal 224 of the node Ν(Τ,θ,ζ) 450 to a control input terminal 214 of a node N(T+l,0,h<sub>T+1</sub>(z)), the node on level T+l· that has a data output terminal connected to a data input terminal of node N(T,0+l,h<sub>T</sub>(z)). This control code prohibits node N(T+l,0,h<sub>T+1</sub>(z)) from sending a message to node N(T,0 + l,h<sub>T+1</sub>(z)) at the time node N(T,0,z) 450 is sending a message to node N(T,0 + l,h<sub>T+</sub>i(z)). When node N(T+l,0,h<sub>T+1</sub>(z)) is blocked from sending a message to node N(T,0+l,h<sub>T+1</sub>(z)), the message is deflected to a node on level T+l. Thus, messages communicated on the same level have priority over messages communicated from another level.
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-26The second data output terminal 222 of nodes Ν(Τ,θ-1,Ηγ(ζ)) are connected to a second data input terminal 212 of nodes N(T,G,z) 450 so that nodes N(T,G,z) 450 receive messages from nodes ΝζΤ,θ-Ι,Ηχίζ)) that are blocked from transmission to nodes Ν(Τ-1,θ,Η<sub>τ</sub>(ζ)). Also, the control output terminal 224 of nodes N(T5 l,G,H<sub>T</sub>(z)) to the control input terminal 214 of nodes N(T,G,z) 450 to warn of a blocked node and to inform nodes ΝζΓ,θ,ζ) 450 not to send data at this time since no node receives data from two sources at the same time.
Refening to Figure 13, interconnections of nodes 102 on cylindrical level 10 one exemplify the described interconnections and demonstrate characteristics and advantages that arise from the general interconnection technique. In this example, the number of nodes K at a cylindrical height is five and the number of heights 2<sup>1</sup> is 2<sup>2</sup>, or 4, for a three level (J+l) interconnect structure 500. Nodes Ν(Ι,θ,ζ) 510 have: (1) a first data input terminal 210 connected to a first data output terminal 220 15 of nodes N(2,G-l,z) 512, (2) a control output terminal 224 connected to control input terminal 214 of nodes N(2,G,h<sub>2</sub>(z)) 512, (3) a first data output terminal 220 connected to a first data input terminal 210 of nodes N(0,G + l,z) 516, (4) a control input terminal 214 connected to a control output terminal 224 of nodes Ν(0,θ,Η<sub>Γ</sub>(ζ)) 516, (5) a second data input terminal 212 connected to the second data output 20 terminal 222 of nodes ΝίΙ,θ-Ι,Η^ζ)) 520, and (6) a second data output terminal 222 connected to the second data input terminal 212 of nodes Νζΐ,θ + Ι,ΐι^ζ)) 522. For nodes N(l,G,z) 510 on level one, height z differs from height hj(z) and height Hi(z) only in the final bit position.
Messages are communicated through the interconnect structure 500 in discrete time steps. A global clock (not shown) generates timing signals in discrete time steps modulus the number of nodes K at a cylindrical height z of a cylindrical level r. When messages traverse the interconnect structure 500 on the same level (for
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M-3240 PCT — -27example, level one) because nodes on an inner level are blocked, messages are communicated from node to node in the discrete time steps. For the interconnect structure 500 with an odd number (K=5) of nodes at a cylindrical level, if data /
traverses level one for 2K time steps, then the message packet visits 2K different nodes. On time step 2K+1, message packets will begin repeating nodes following the sequential order of the first node traversal. Because the global clock generates the discrete time steps integral time modulus K, if a message packet on level one is over the target ring of that packet at a time T=0 (modulus K) and is deflected by a message on level zero, the message will be over the target ring also at a time T=0 (modulus K) to make another attempt to enter the target ring. In various embodiments, this timing characteristic is consistent throughout the interconnect structure so that, if a message packet is in a position to descend to the next level at a time T=0 (modulus K), the packet will once again be in a position to descend at a subsequent time T=0 (modulus K).
Referring to Figure 14 in conjunction with Figure 13, interconnections of nodes 102 on cylindrical level two further exemplify described interconnections. In Figure 14, a level two message path 620 is shown overlying the paths 610 and 612 of messages moving on level one. The number of nodes K at a cylindrical level is five and the number of levels 2<sup>J</sup> is 2<sup>2</sup>, or 4, for a three level (J 4-1) interconnect structure 500. Same-level interconnections of nodes Ν(2,θ,ζ) include: (1) a second data input terminal 212 connected to the second data output terminal 222 of nodes N(2,0-l,h<sub>2</sub>(z)) and (2) a second data output terminal 222 connected to the second data input terminal 212 of nodes N(2,04-l,H<sub>2</sub>(z)). For nodes N(2,0,z) on level two, height z differs from height h<sub>2</sub>(z) and height H<sub>2</sub>(z) only in the final two bit positions.
Generally stated in binary form for any suitable number of nodes K at a height and number of heights 2<sup>1</sup> in a level, bits z and h<sub>2</sub>(z) on cylindrical level two are related as follows:
[zj-i, Zj_<sub>2</sub>, . . ., Z2, 0, 0]' = [zj<sub>4</sub>, Zj.<sub>2</sub>, . . ;, Z2, 1, 0J;
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<td></td><td></td><td> -28-</td><td></td>
<td> [<sup>z</sup>J-b <sup>z</sup>J-2, * </td><td> ., Z2, 1, 0]'</td><td> [<sup>z</sup>J-b <sup>z</sup>J-2> ·</td><td> • ·, ¾ o, 1];</td>
<td> Zj_<sub>2</sub>, . .</td><td> -,¾ o, 1]'</td><td><sup>=</sup> t<sup>Z</sup>J-b Zj-2» ·</td><td> . ., Zi, 1, 1]; and</td>
<td> [<sup>z</sup>J-b Zj_<sub>2</sub>, . </td><td> • .,¾ 1, 1]'</td><td> = [Zj-1, Zj_2, .</td><td> • ·, Zz, θ, θ]·</td>
A second advantage of this interconnection technique for nodes on the same level is that blocked messages are directed to avoid subsequent blocking. Figure 14 illustrates a message blocking condition and its resolution. On level one, a message mo 610 is shown at node and a message mj 612 at node N<sub>01i</sub>. A message M 620 on level two at node is targeted for ring zero. At a time zero, message M 620 is blocked and deflected by message m<sub>x</sub> 612 to node N<sub>122</sub> at time one. Assuming that messages mo and m<sub>r</sub> are also deflected and traversing level one, at a time one message mo 610 is at node N<sub>ni</sub> and message mj 612 at node N<sub>101</sub>. At a time two, message M 620 moves to node N<sub>2i2</sub>, message mo 610 to node N^i and message πη 612 to node N<sub>2I1</sub>. Thus, at time two, message M 620 is deflected by message 610. At time four, message M 620 is again blocked by message mi 612. This alternating blocking of message M 620 by messages mo 610 and ηη 612 continues indefinitely as long as messages mo 610 and mi 612 are also blocked. This characteristic is pervasive throughout the interconnect structure so that a single message on an inner level cannot continue to block a message on an outer level. Because a single message packet cannot block another packet and blocking packets continually proceed through the levels, blocking does not persist.
Referring to Figure 15, interconnections of nodes 102 on cylindrical level three show additional examples of previously described interconnections. A level three message path 720 is shown overlying the paths 710, 712 and 714 of messages moving on level two. The number of nodes K at a cylindrical height is seven and the number of heights 2<sup>J</sup> is 2<sup>3</sup> (8), for a four level (J 4-1) interconnect structure. Samelevel interconnections of nodes Ν(3,θ,ζ) include: (1) a second data input terminal 212 connected to the second data output terminal 222 of nodes N(3,6-l,h<sub>3</sub>(z)) and (2) a second data output terminal 222 connected to the second data input terminal 212 of
AMENDED SHEET
CA 02227271 1998-01-20
M-3240 PCT — -29nodes Ν(3,Θ4-1,Η<sub>3</sub>(ζ)). For nodes N(3,0,z) on level three, height z differs from height h<sub>3</sub>(z) and height H<sub>3</sub>(z) only in the final three bit positions. Generally stated in binary form for any suitable number of nodes K at a cylindrical height and number of heights 2<sup>J</sup> in a level, bits z and h<sub>3</sub>(z) on cylindrical level three are related as follows:
<td> [<sup>z</sup>J-b <sup>Z</sup>J-2> ·</td><td> -, <sup>z</sup>3> 0, 0» 0]' — [Zj-1, Zj_2, .</td><td> ., z<sub>3</sub>; 1, 0, 0];</td>
<td> [Zj-lt Zj-2> </td><td> ., Z3, 1, 0, 0]' ='[Z<sub>W</sub>, Zj.<sub>2)</sub> .</td><td> ., z<sub>3</sub>, 0, 1, 0];</td>
<td> l<sup>z</sup>J-b <sup>z</sup>J-2» </td><td> ., z<sub>3</sub>, 0, 1,0]' = [zj.<sub>b</sub> Zj.<sub>2</sub>, .</td><td> ., z<sub>3</sub>, 1, 1, 0];</td>
<td> [Zj-i, Zj_<sub>2</sub>, .</td><td> ., z<sub>3</sub>, 1, 1, 0]' = [z<sub>M</sub>, Zj.2, .</td><td> ·, Z3, θ, 0, 1];</td>
<td> [Zj_i, Zj_2, .</td><td> ., Z<sub>3</sub>, 0, 0, 1]' = [Z<sub>M</sub>, Zj.2, .</td><td> ., z<sub>3</sub>, 1, 0, 1];</td>
<td> [<sup>z</sup>J_b <sup>z</sup>j_2, .</td><td> ., Z<sub>3</sub>, 1, 0, 1]' = [Zj-t, Zj_2, .</td><td> ., Z3, 0, 1, 1];</td>
<td> [Zj_i, Zj_<sub>2</sub>, .</td><td> ·, z<sub>3</sub>, 0, 1, 1]' = [Zj.j, Zj_2, .</td><td> ., z<sub>3</sub>, 1, 1, 1]; and</td>
<td> [Zj_l> Zj-2» -</td><td> ., Z<sub>3</sub>, 1, 1, 1]' = [Zj.<sub>b</sub> Zj_2, .</td><td> ·, z<sub>3</sub>, 0, 0, 0].</td>
Figure 15 illustrates another example of a message blocking condition and its resolution. On level two, a message mg 710 is shown at node Ng^, a message mj
712 at node N<sub>012</sub>, a message m<sub>2</sub> 714 at node Ng^ and a message m<sub>3</sub> 716 at node
N<sub>032</sub>. A message M 720 on level three at node N<sub>303</sub> is targeted for ring zero. At a time zero, message M 720 is blocked and deflected by message m<sub>3</sub> 716 to node N<sub>173 </sub>at time one. Assuming that messages mg, m<sub>n</sub> m<sub>2</sub> and m<sub>3</sub> are also deflected and 2 0 traversing level two, at a time one message mg 710 is at node N<sub>132</sub>, message πη 712 at node N<sub>12</sub>2, message m<sub>2</sub> 714 at node N<sub>102</sub> and message m<sub>3</sub> 716 at node N<sub>112</sub>. At a time two, message M 720 moves to node N^, message mg 710 to node N<sub>212</sub>, message mi 712 to node N^, message m<sub>2</sub> 714 to node and message m<sub>3</sub> 716 to node N222· Thus, at time two, message M 720 is deflected by message nq 712. At 25 time four, message M 720 is blocked by message m<sub>2</sub> 714. At time six, message M
720 is blocked by message mg 710. At time eight, message M 720 is again blocked by message m<sub>3</sub> 716. This alternating blocking of message M 720 by messages m<sub>Q </sub>710, πη 712, m<sub>2</sub> 714 and m<sub>3</sub> 716 continues indefinitely as long as messages mg 710, m<sub>t</sub> 712, m<sub>2</sub> 714 and m<sub>3</sub> 716 are also blocked.
AMENDED SHEET
CA 02227271 1998-01-20
M-3240 PCT ' '
-30This analysis illustrates the facility by which the described interconnect structure avoids blocking at any level. Thus, hot spots of congestion in the structure are minimized. This charâcteristic is maintained at all levels in the structure.
The described interconnect structure provides that every node Ν(0,θ,ζ) on level zero is accessible by any node N(J,0,z) on outermost level J. However, only half of the nodes Ν(Ο,θ,ζ) on level zero are accessible by a node N(J-l,0,z) on the level once removed from the outermost level. Data at a node N(l,0,z) on level one can access any node Ν(0,θ,ζ) on level zero so long as the binary representation of height z of level one and the binary representation of ring r of level zero differ only in the last bit. Similarly, data at a node N(2,#,z) on level two can access any node Ν(0,θ,ζ) on level zero so long as the binary representation of height z of level two and the binary representation of ring r of level zero differ only in the last two bits. A general rule is that, data at a node N(T,0,z) on level T can access any node Ν(Ο,θ,ζ) on level zero so long as the binary representation of height z of level T and the binary representation of ring r of level zero differ only in the last T bits. Accordingly, moving from the outermost level J to level J-l fixes the most significant bit of the address of the target ring. Moving from level J-l to level J-2 fixes the next most significant bit of the address of the target ring and so forth. At level zero, no bits are left to be fixed so that no header bit is tested and a message is always passed to a device. In some embodiments, an additional header bit is included and tested at a level zero node. This final bit may be used for various purposes, such as for directing message data to a particular buffer of a device when the device accepts the message data. An advantage of including an additional bit in the header and performing a bit test at the final node is that all the nodes at all levels of the interconnect structure operate consistently.
AMENDED SHEET
CA 02227271 1998-01-20
M-3240 PCT
-31In some embodiments of an interconnect structure, an additional header bit is included in a message packet. This bit indicates that a message packet is being transmitted. Another purpose for such an additional bit in the header is to identify which bit in the header is the control bit.
A message packet moves from a level T to the next inner level T-l so long as two conditions are met, as follows: (1) the target ring of the message packet is accessible from level T-l, and (2) the message packet is not blocked by a message on the level T-l.
One significant aspect of this structure is that any message packet at a node ΝΧΤ,θ,ζ) oh a level T that can access its target ring can also access the target ring from a node N(T-l,04-l,z) only if the bit T-l of the address ring is the same as bit T-l of the target ring. Therefore, analysis of only a single bit yields all information for determining a correct routing decision.
Referring to Figure 16, a general relationship between message packets on two adjacent levels T and T-l· 1 is described. In this example, a message packet M at a node N<sub>450</sub> on level four, which is targeted for ring zero, is potentially blocked by eight message packets mo 810, m<sub>x</sub> 811, m<sub>2</sub> 812, m<sub>3</sub> 813, m<sub>4</sub> 814, m<sub>5</sub> 815, m<sub>6</sub> 816 and m<sub>7</sub> 817 at nodes N<sub>3i0</sub> residing on each of the heights 0 to 7 on level three. Although the behavior of the interconnect structure is analyzed with respect to levels three and four for purposes of illustration, -the analysis is applicable to any arbitrary adjacent levels. At an arbitrary time step, illustratively called time step zero, the message M moves from node N<sub>450</sub> on level four to node N<sub>351</sub> on level three unless a z
control code is send to node N<sub>45o</sub> from a level three node having a data output terminal connected to node N<sub>351</sub>. In this example, node N<sub>3i0</sub> has a data output terminal connected to node N<sub>351</sub> and, at time step zero, message m<sub>7</sub> 817 resides at node N<sub>310</sub>. Accordingly, node N<sub>310</sub> sends a control code, in this example a single bit amended sheet
CA 02227271 1998-01-20 ri ι I ' 4 i t f f / r / r « ι i nr·* * > f <
M-3240 PCT <sup>: :</sup>
-32code, to node N<sub>450</sub>, causing deflection of message M to node N<sub>4D1</sub> (where D is a hexadecimal designation of 13) on an interconnection line. A bit line illustratively shows the control connection from node N<sub>310</sub> to node N<sub>450</sub>. At a time step one, message M moves from node N<sub>4Di</sub> to node N<sub>432</sub> on interconnection line regardless of whether a node N<sub>32</sub>g is blocked because ring zero is not accessible from node N<sub>328</sub>. At a time step two, message M moves from node N<sub>432</sub> to node N<sub>334</sub> unless a control blocking code is sent from node N<sub>352</sub> to node N<sub>432</sub> where node N<sub>352</sub> is the node on level three that has a data output terminal connected to a data input terminal of node N<sub>334</sub>. However, the message M is blocked from accessing node N<sub>334</sub> because message m<sub>6</sub> currently resides at node N<sub>352</sub> at time step two. A deflection control code is sent from node N<sub>352</sub> to node N<sub>432</sub> on control bit line 822. Furthermore, assuming that none of the message packets ηη progresses to level two and beyond, at time step four, message M is blocked by message m<sub>2</sub> via a control code sent on control bit line. At time six, message M is blocked by message nxj though a blocking control code on control bit line.
This example illustrates various advantages of the disclosed interconnection structure. First, deflections of the message M completely tour all of the heights on a level T if messages mj on level T-l continue to block progression to the level T-l for all levels T. Accordingly, a message M on a level T is blocked for a complete tour of the heights only if 2<sup>r_I</sup> messages are in position on level T-l to block message M. In general, a message mj on a level T-l must remain on the level T-l for 2<sup>T+1</sup> time steps to block the same message M on level T twice.
The description exemplifies an interconnect structure in which messages descend from an outer level to devices at a core inner layer by advancing one level when the height dimension matches the destination ring location and traversing the rings when the ring location does not match the height designation. In other embodiments, the messages may move from an inner level to an outer level. In amended sheet
CA 02227271 1998-01-20
<img file="CA2227271C_D0001.tif" />
M-3240 PCT some embodiments, the heights may be traversed as the level changes and the height held constant as the level remains stationary. In these embodiments, tlie progression of messages through nodes is substantially equivalent to the disclosed interconnect structure. However, the advantage of the disclosed network that avoids blocking of messages is negated.
Referring to Figure 17, a timing diagram illustrates timing of message communication in the described interconnect structure. In various embodiments of the interconnect structure, control of message communication is determined by timing of message arrival at a node. A message packet, such as a packet 900 shown in Figure 18, includes a header 910 and a payload 920. The header 910 includes a series of bits 912 designating the target ring in a binary form. When a source device CU(0i,Z]) at an angle 6<sub>r</sub> and height z<sub>A</sub> sends a message packet M to a destination device CU(6<sub>21</sub>z<sub>2</sub>) at an angle θ<sub>2</sub> and height z<sub>2</sub>, the bits 912 of header 910 are set to the binary representation of height z^.
A global clock servicing an entire interconnect structure keeps integral time modulus K where, again, K designates the number of nodes n at a cylinder height z. There are two constants a and β such that the duration of a exceeds the duration of β and the following five conditions are met. First, the amount of time for a message M to exit a node N(T,6+1,11^)) on level T after exiting a node Ν(Τ,θ,ζ) also on level T is a. Second, the amount of time for a message M to exit a node N(T-
1,6 +l,z) on level T-l after exiting a node N(T,6,z) on level T is a - β. Third, the amount of time for a message to travel from a device CU to a node N(r,6,z) is a - β. Fourth, when a message M moves front a node N(r,6,z) to a node N(r,0+l,h<sub>r</sub>(z)) in time duration a, the message M also causes a control code to be sent from node N(r,6,z) to a node N(r+l,6+l,h<sub>r</sub>(z)) to deflect messages on the outer level r+1. The time that elapses from the time that message M enters node N(r,6,z) until the
AMENDED SHEET
CA 02227271 1998-01-20
M-3240 PCT ......
-34control bit arrives at node N(r+l,0 + l,h<sub>r+1</sub>(z)) is time duration β. The aforementioned fourth condition also is applicable when a message M moves from a node N(J,0,z) to a node N(J,0+l,hj(z)) at the outermost level J so that the message /
M also causes a control code to be sent from node N(J,0,z) to â device CU(0,z). The time that elapses from the time that message M enters node N(r,0,z) until the control bit arrives at device CU(S,z) is time duration β. Fifth, the global clock generates timing pulses at a rate of a.
When the source device sends a message packet M to the destination device CU(0<sub>2</sub>,Z2), the message packet M is sent from a data output terminal of device CU(0!,Zj) to a data input terminal of node Ν^,θ^ζ^ at the outermost level J. Message packets and control bits enter nodes N(T,0,z) on a level T at times having the form na + ί,β where n is a positive integer. The message M from device CU(0i,Zj) is sent to the data input terminal of node NfLO^Zj) at a time to - β and is inserted into the data input terminal of node N(J,0!,Zi) at time to so long as the node Ν^,θ^ζ^ is not blocked by a control bit resulting from a message traversing on the level J. Time to has the form (θ<sub>2</sub>-θι)α -Μβ. Similarly, there is a time of the form (02-θ^α +Ίβ at which a data input terminal of node ΝίΙ,θ^ζ^ is receptive to a message packet from device CUCQ^Zj).
Nodes N(r,9,z) include logic that controls routing of messages based on the target address of a message packet M and timing signals from other nodes. A first logic switch (not shown) of node Ν(γ,Θ,ζ) determines whether the message packet M is to proceed to a node Ν(Τ-1,θ + 1,ζ) on the next level T-l or whether the node Ν(Τ-1,Θ+ l,z) is blocked. The first logic switch of node N(r,0,z) is set according to whether a single-bit blocking control code sent from node ΝίΤ-Ι,θ,Η-ι^ζ)) arrives at node Ν(γ,Θ,ζ) at a time to. For example, in some embodiments the first logic switch
AMENDED SHEET
CA 02227271 1998-01-20 > 7 ΙΟ 30 33 »<· »·»^ » ’ ’ i i η ο β · · · · ο
Ί - » ·> ΑΑ*> a β β » « ··« Q
M-3240 PCT <sup>1</sup> ···· ··* ·
-35- <sup>;</sup> takes a logic 1 value when a node Ν(Τ-1,Θ+ l,z) is blocked and a logic 0 value otherwise. A second logic switch (not shown) of node Ν(γ,Θ,ζ) determines whether the message packet M is to proceed to a node N(T-l,6+l,z) on the next level T-l or whether the node N(T-1,0+l,z) is not in a suitable path for accessing the destination device CU(0<sub>2</sub>,Z2) of the message packet M. The message packet M includes the binary representation of destination height Z2 (z^j), Z2ÇM), · - , Z2<i> - - 1 z^oy The node Ν(Τ,θ,ζ) on level T includes a single-bit designation zy of the height designation z (z<sub>J(</sub> zj.i, . . , zy, . . , z<sub>b</sub> Zq). In this embodiment, when the first logic switch has a logic 0 value and the bit designation Z2^ of the destination height is equal to the height designation Zy, then the message packet M proceeds to the next level at node N(T-l,0+l,z) and the destination height bit is stripped from the header of message packet M. Otherwise, the message packet M traverses on the same level T to node N(T,0+1,11^2)). If message packet M proceeds to node N(T1,0+l,z), then message packet M arrives at a time to + (a - β) which is equal to a time (¾ - Zj + l)cc + (J - 1)β. If message packet M traverses to node Ν(Τ,θ+ ljbyiz)), then message packet M arrives at a time to + a, which is equal to a time (Z2 - z<sub>1</sub> + l)a + Ιβ. As message packet M is sent from node N(r,0,z) to node N(T,0 + l,h<sub>T</sub>(z)), a single-bit control code is sent to node Ν(Τ+1,θ+1,Η<sub>τ+1</sub>(ζ)) (or device CU(0,z) which arrives at time to + β. This timing scheme is continued throughout the interconnect structure, maintaining synchrony as message packets are advanced and deflected.
The message packet M reaches level zero at the designated destination height
Z2. Furthermore, the message packet M reaches the targeted destination device z
CU(0<sub>2</sub>,Z2) at a time zero modulus K (the number of nodes at a height z). If the targeted destination device CU(0<sub>2</sub>,Z2) is ready to accept the message packet M, an input port is activated at time zero modulus K to accept the packet. Advantageously, all routing control operations are achieved by comparing two bits, without ever amended sheet
CA 02227271 1998-01-20
<img file="CA2227271C_D0002.tif" />
M-3240 PCT
-36comparing two multiple-bit values. Further advantageously, at the exit point of the interconnect structure as message packets proceed from the nodes to the devices, there is no comparison logic. If a device is prepared to accept a message, the message enters the device via a clock-controlled gate.
Many advantages arise as a consequence of the disclosed timing and interconnect scheme. In an optical implementation, rather than an electronic implementation, of the interconnect structure, signals that encode bits of the header typical have a longer duration than bits that encode the payload. Header bits are 10 extended in duration because, as messages communicate through the interconnect structure, timing becomes slightly skewed. Longer duration header bits allow for accurate reading of the bits even when the message is skewed. Γη contrast, payload bits encode data that is not read during communication through the interconnect structure. The disclosed timing scheme is advantageous because the number of 15 header bits in a message is greatly reduced. Furthermore, in some embodiments the number of header bits is decremented as bits are used for control purposes at each level then discarded while messages pass from level to level in the interconnect structure. In embodiments that discard a control bit for each level of the interconnect structure, logic at each node is simplified since the control bit at each level is located 2 0 at the same position throughout the interconnect structure.
That messages communicated on the same level have priority over messages communicated from another level is similarly advantageous because message contention is resolved without carrying priority information in the message header.
Message contention is otherwise typically resolved by giving priority to messages that Λ have been in an interconnect structure the longest or to predetermined prioritization. These techniques use information stored in the header to resolve contention.
AMENDED sheet
CA 02227271 1998-01-20 > Ο <3 “> Ο
M-3240 PCT •1
Β ·»
<img file="CA2227271C_D0003.tif" />
·37·
Although it is advantageous that the interconnect structure and message communication method determines message transmission routing using self-routing decision-making which is local to the nodes and depends on message timing, in some embodiments of the control structure, both local and global communication control is employed. For example, one embodiment of an interconnect structure uses local control which is based on timing to control transmission of message packets in a first transmission mode and alternatively uses global control via a scheduler to administer communication of lengthy strings of message data in a second mode. In the global mode, the usage of a scheduler makes the usage of control bit input and output terminals unnecessary.
One consequence of self-routing of message packets is that the ordering of message packet receipt at a target device may be variable. In some embodiments, the correct order of message segments is ordered by sending ordering information in the message header. Other embodiments employ an optical sorter to order message packets.
Although many advantages are realized through a control structure and communication method which utilizes timing characteristics, rather than control bits in the header, to control message routing, some interconnect node technologies more suitably operate in a routing system utilizing no timing component. Thus in these technologies, instead of introducing a message at predetermined time so that the message arrives at a preset destination _at a designated, routing information is contained in additional header bits. Accordingly, a designated target device position is included in header bits, for example bits following the designated target ring position.
In one embodiment, the label of a target device is represented as a single logic one in a string of logic zeros. Thus, when a message arrives at a device N, the
AMENDED SHEET
CA 02227271 1998-01-20
M-3240 PCT
-38device samples the Nth bit of the device element of the header (as distinguished from the ring element) and accepts the message if the Nth bit is a logic one. This technique is highly suitable for optical node implementations.
Nodes
The nodes N(r,0,z) have been described in generic terms to refer to various data communication switches for directing data to alternative data paths. Node structures which are presently available include electronic nodes, optical nodes and mixed optical/electronic nodes. What is claimed include, for example, interconnect and timing methods, an interconnect apparatus and an interconnect topology. These methods and apparati involve nodes in a generic sense. Thus, the scope of the claims is not limited by the particular type of node described herein and is to extend to any node known now or in the future, which performs the function of the nodes described herein.
One example of a node 1300 is shown, referring to Figure 19, which includes a lithium niobate (LiNbO3) gate 1302. The lithium niobate gate 1302 has two data input terminals 1310 and 1312, two data output terminals 1320 and 1322 and one control input terminal 1330. Various control circuitry 1340 is added to the lithium niobate gate 1302 to form a control output terminal 1332 of the node 1300. Node 1300 also includes optical to electronic converters 1354, 1356 and 1358. The lithium niobate gate 1302 is forms a 2x2 crossbar. Data paths 1342 and 1344 are optical and the control of the node 1300 is electronic. The lithium niobate gate 1302 is combined with a photodetectors 1350 and 1352 and a few electronic logic ?
components to form a node 1300 for various embodiments of an interconnect structure.
ANODES s®
CA 02227271 1998-01-20 <*>
•i *· e· a?
* ·» · » s » · «·· » « « · «a·· »· «
-39In operation, as a message packet 1360 approaches the node 1300, part of the message packet signal 1360 is split off and an appropriate bit of the message packet header (not shown) designating a bit of the binary representation of destination ring in accordance with the discussion hereinbefore, is read by the photodetector 1350. This bit is converted from optical form to an electronic signal. This bit, a bit designating the cylinder height upon which the node 1300 lies and a bit designating whether a destination node on the next level is blocked are processed electronically and a result of the logical tests of these bits is directed to the control input terminal 1330 of the lithium niobate gate 1302. In a first type of lithium niobate gate technology, if the resuit signal is a logic zero, the gate switches in the cross state. In a second type of lithium niobate gate technology, a logic zero result signal switches the gate in a bar (straight through) state.
Referring to Figure 20, an additional example of a node 1400 is shown.
Node 1400 uses a nonlinear optical loop mirror (NOLM) 1410 to perform a switching function. A nonlinear optical loop mirror is a device that makes use of the refractive index of a material to form a completely optical switch that is extremely fast. One example of a NOLM switch includes a data input terminal 1412 and a control input terminal 1414. Depending upon the signal at the control input terminal 1414, data either leaves the NOLM 1410 through the same data input terminal 1412 from which the data entered (hence the term mirror) or the data exits through a data output terminal 1416. Data is polarized and split into two signal halves of equal intensity. In the absence of a control pulse, the two halves of the signal recombine and leave the NOLM 1410 through the data input terminal 1414. When a control pulse is applied to the control input terminal 1414, the control pulse is polarized at right angles to the data pulse and inserted into the NOLM 1410 so that the control pulse travels with one half of the data pulse. The control pulse is more intense than the data pulse and the combined first half of the data pulse and the control pulse quickly pass the second half of the data pulse so that the second half of the data pulse > >1 ·> -> ί n
J 1 ·> -> rj ·>
> ·> Π Λ 0 o
non
Ί 1 i n
AMENDED SHEET
CA 02227271 1998-01-20 •j )
<img file="CA2227271C_D0004.tif" />
<img file="CA2227271C_D0005.tif" />
» • 9 • ·*
A » · β· ···
M-3240 PCT ·· “40is only minimally accelerated. Thus, the two halves of the data pulse travel with slightly different velocities and are 180° out of phase when the two halves are recombined. This phase difference causes the combined data pulse signal to pass through the data output terminal 1416. One disadvantage of the NOLM 1410 is that switching is operational only when a long optical transmission loop is employed, thus latency is a problem.
Referring to Figure 21, another example of a node 1500 is shown which uses a terahertz optical asymmetrical demultiplexer (TOAD) switch 1510. The TOAD switch 1510 is a variation of the NOLM switch 1410. The TOAD 1510 includes an optical fiber loop 1512 and a semiconductor element 1514, a nonlinear element (NLE) or a semiconductor optical amplifier for example. The TOAD switch 1510 has an input data terminal 1520 which also serves as an output data port under some conditions. The TOAD switch 1510 also has a separate second output data terminal 1522. The semiconductor element 1514 is placed asymmetrically with respect to the center 1516 of the fiber optic loop 1512. A distance 1518 from the semiconductor element 1514 to the center 1516 of the fiber optic loop 1512 is the distance to transmit one bit of data. The TOAD 1510 functions by removing a single bit from a signal having a high data rate. The TOAD 1510 is switched by passing a constant electrical current through the semiconductor element 1514. An optical signal entering the semiconductor material causes the index of refraction of the material to immediately change. After the optical signal terminates, the index of refraction slowly (a time span of several bits) drifts back to the level previous to application of the optical signal. A control pulse is an optical signal having an intensity higher than that of an optical data signal and polarization at right angles to the optical data signal.
An optical data input signal is polarized and split into two signal halves of equal intensity. The control pulse is injected in a manner to move through the fiber optic loop 1512 directly over the bit that is to be removed. Because the distance 1518 is exactly one bit long, one half of the split optical data signal corresponding to a bit
AMENDED SHEET
CA 02227271 1998-01-20 , . ·· > ·> > « <♦ ·♦ **«*,.
I 3 > Ί ' « 1 β··· ·· ·
-.11 9 5Α > 5 9 9 9 9 ··« 9
M-3240 PCT <sup>;</sup> ’........* I
-41- <sup>Λ</sup>' leaves the semiconductor element 1514 just as the other half of the bit enters the semiconductor element 1514. The control pulse only combines with one half of the optical data signal bit so that the velocity of the two halves differs. The combined data and control signal bit exits the TOAD 1510 at the input data terminal 1520.
Thus, this first bit is removed from the data path. A next optical signal bit is split and a first half and second half, moving in opposite directions, are delayed approximately the same amount as the index of refraction of the semiconductor element 1514 gradually changes so that this bit is not removed. After a few bits have passes through the semiconductor element 1514, the semiconductor material relaxes and another bit is ready to be multiplexed from the optical data signal. Advantageously, the TOAD 1510 has a very short optical transmission loop 1512.
Regenerators
It is a characteristic of certain nodes that messages lose strength and pick up noise as they propagate through the nodes. Using various other nodes, message signals do not lose strength but noise accumulates during message transmission. Accordingly, in various embodiments of the interconnect structure, signal regenerators or amplifiers are used to improve message signal fidelity after messages
Q have passed through a number of nodes.
Referring to Figure 22, one embodiment of a regenerator 1600 is shown which is constructed using a lithium niobate gate 1602. A lithium niobate gate 1602 regenerates message data having a transmission speed of the order of 2.5 gigabits.
The lithium niobate gate 1602 detects and converts an optical message signal to an electronic signal which drives an electronic input port 1604 of the lithium niobate gate 1602. The lithium niobate gate 1602 is clocked using a clock signal which is applied to one of two optical data ports 1606 and 1608 of the gate 1602. The clock
AMENDED SHEET
CA 02227271 1998-01-20 ) i ï no ο o« · <sub>Ί</sub> > » T 3 3394» >·)) 3 3 Ί Π 3 Φ *» e
M-3240 PCT <sup>; ;</sup> n,\. \/\/.λ.
-42signal is switched by the electronic control pulses and a high fidelity regenerated signal is emitted from the lithium niobate gate 1602.
Typically, an interconnect structure utilizing a lithium niobate gate 1602 in a regenerator 1600 also uses lithium niobate gates to construct nodes. One large power laser (not shown) supplies high fidelity timing pulses to all of the regenerators in an interconnect structure. The illustrative regenerator 1600 and node 1650 combination includes an optical coupler 1620 which has a first data input connection to a node on the same level C as the node 1650 and a second data input connection to a node on the overlying level C4-1. The illustrative regenerator 1600 also includes a photodetector 1622 connected to an output terminal of the optical coupler 1620, optical to electronic converter 1624 which has an input terminal connected to the optical coupler 1620 through the photodetector 1622 and an output terminal which is connected to the lithium niobate gate 1602. An output terminal of the lithium niobate gate 1602 is connected to a second lithium niobate gate (not shown) of a node (not shown). Two signal lines of the lithium niobate gate (not shown) are combined, regenerated and switched.
When regenerators or amplifiers are incorporated to improve signal fidelity and if the time expended by a regenerator or amplifier to recondition a message signal exceeds the time a - β, then the regenerator or amplifier is placed prior to the input terminal of the node and timing is modified to accommodate the delay.
Other Embodiments
The interconnect structure shown in Figures 1 through 16 is a simplified * structure, meant to easily convey understanding of the principles of the invention.
Numerous variations to the basic structure are possible. Various examples of alternative interconnect structures are discussed hereinafter, along with advantages achieved by these alternative structures.
<img file="CA2227271C_D0006.tif" />
AMENDED SHEET
CA 02227271 1998-01-20
<td></td><td> -»«» 9 · · ··· · ) > > Ί Λ Ο · ♦ · 4 M-3240 PCT · ......... -43- Referring to Figure 23, an alternative embodiment of an interconnect structure 1000 includes devices 1030 which issue message packets to multiple nodes 1002 of the outermost level J, In the interconnect apparatus 100 shown in Figures 1</td>
<td> 5</td><td> through 16, a device CU(G,z) initiates a message transmission operation by sending a message packet to a node N(J,9,z). In the alternative interconnect structure 1000, the device CU(6,z) initiates a message transmission operation by sending a message packet to node N(J,9,z) but, in addition, also includes interconnections to additional multiple nodes where z designates cylinder heights selected from heights 0</td>
<td> 10</td><td> to 2<sup>T</sup> of the outermost level J and 0 designates node angles selected from angles 0 to K of the heights z. In the case that a device sends messages to more than one node in the outermost level, the disclosed timing scheme maintains the characteristic that messages arrive at the target node at time zero modulus K.</td>
<td> 15</td><td> Devices are connected to many nodes in the outermost level J to avoid</td>
<td> ® ,,</td><td> congestion upon entry into the interconnect structure caused by multiple devices sending a series of messages at a high rate to nodes having converging data paths. In some embodiments, the nodes to which a device is connected are selected at random. In other embodiments, the multiple interconnection of a device to several nodes is</td>
<td> 20</td><td> selected in a predetermined manner. An additional advantage arising from the connection of a device to several nodes increases the input bandwidth of a communication network. Referring to Figure 24, an alternative embodiment of an interconnect</td>
<td> 25</td><td> structure 1100 includes devices 1130 which receive message packets from multiple nodes 1102 of the innermost level 0. In this example, the number of nodes K at a particular height z is nine and each device 1130 is connected to receive message from three nodes on level zero. The interconnect structure 1100 is advantageous for</td>
AMENDED SHEET
CA 02227271 1998-01-20 > ·».·>.> -a « s ô β · · · · φ > >> n a a η ο i » · · · ··· φ
Μ-3240 PCT ·* ······ ·· *
-44improving network exit bandwidth when the number of nodes K on at a particular height is large.
In the example in which the number of nodes K on a height z is nine and each device receives messages from three nodes on level zero, each node on ring zero is connected to a buffer that has three levels. At time 0, message data is injected into the level zero buffer. At time three, data is injected into the level one buffer. At time 6, data is injected into the level two buffer. A device CU(0,0) reads from the level zero buffer at node Ν(Ο,Θ,Ο), from the level one buffer at node
N(O,(04-3)mod 9,0), and from the level two buffer at node N(0,(0+6)mod 9,0).
This reading of message data is accomplished in a synchronous or nonsynchronous · manner. If in the synchronous mode, a time t is expended to transfer data from the buffer to the device. In this case, the device CU(0,0) reads from the level zero buffer at time t, reads from the level three buffer at time S+ί, and reads from the level six buffer at time 6+i. In an asynchronous mode, device CU(0,0) interconnects to the three buffers as described hereinbefore and reads message data whenever a buffer signals that data is available.
Referring to Figure 25, an alternative embodiment of an interconnect
0 structure 1200 includes devices Ϊ230 which issue message packets to multiple nodes 1202, not only in the outermost level J but also in other levels. In the alternative interconnect structure 1200, the device CU(9,z) initiates a message transmission operation by sending a message packet to node N(J,Q,z) but, in addition, also includes interconnections to additional multiple nodes ΝίΤ,^,ζ) where T designates levels of the interconnect structure 1200, z designates cylinder heights selected from heights 0 to 2<sup>J</sup> of the outermost level J and Θ designates node angles selected from angles 0 to K of the heights z. In the case that a device sends messages to nodes in more than level, message communication is controlled according to a priority, as amended sheet
CA 02227271 1998-01-20 ί 1 1 Ο > 5 9 · Ο »ν a ·% 9 9 9 ~ι » γ> » · Ο ·«· *
M-3240 PCT ’ ' ” ··’···· I
-45follows. First, messages entering a node N(r,6,z) from the same level T have a first priority. Second, messages entering a node N(r,G,z) from a higher level T+l have a second priority. Messages entering a node N(r,9,z) from a device CU(0,z) have last priority. The alternative embodiment of interconnect structure 1200 allows a device to send messages to neighboring devices more rapidly. The disclosed timing scheme maintains the characteristic that messages arrive at the node designated in the message header at time zero modulus K.
In these various embodiments, devices accept data from level zero nodes using one of various predetermined techniques. Some embodiments rely exclusively on timing to determine when the devices accept data so that devices accept data at ' time zero modulus K. Some embodiments include devices that accept message data at various predetermined times with respect to modulus K timing. Still other embodiments have devices that accept data whenever a buffer is ready to accept data.
Wave Division Multiplexing Embodiment
In another embodiment of an interconnect structure, message signal bandwidth is increased using wave division multiplexing. A plurality of K colors are defined and generated in a message signal that is transmitted using an interconnect structure having K devices at a cylinder height. Accordingly, each device is assigned a particular color. Message packets travel to a preselected target ring in the manner described hereinbefore for a single wavelength interconnect system. Message packets pass from level zero to the appropriate device depending on the color assigned to the message packet.
A message includes a header and a payload. The header and payload are distinguished by having different colors. Similarly, the payload is multiplexed using different colors, which are also different from the color of the header. Message
AMENDED SHEET
CA 02227271 1998-01-20 ' » 1’ on « · « « » · » O >:. ->4»· ft* -,
-»·» ft ft ft «4« ·
M-3240 PCT <sup>1</sup> ........* ·
-46bandwidth is also increased by combining different messages of different colors for simultaneous transmission of the messages. Furthermore, different messages of different colors are bound on a same target ring, combined an transmitted simultaneously. All messages are not demultiplexed at all of the nodes but, rather, are demultiplexed at input buffers to the devices.
Variable Base f Height Structure Embodiment
In a further additional embodiment, an interconnect structure has i<sup>J</sup> cylindrical heights on a level for each of J+l levels, where i is a suitable integer number such as (the previously described embodiment), 3, 4 or more. As was described previously, each height contains K nodes, and each node has two data input terminals, two data output terminals, one control input terminal and one control output terminal.
For example, an interconnect structure may have 3<sup>1</sup> heights per level. On level one, message data is communicated to one of three level zero heights. On level two, message data is communicated to one of nine level zero heights and so forth. This result is achieved as follows. First, the two output data terminals of a node
0 N(r,9,z) are connected to input data terminals of a node N(T-l,G+l,z) and a node
ΝίΤ,θ+Ι^τίζ)), in the manner previously discussed. However in this further embodiment, a third height transformation hT^h^h^z))) rather than a second height transformation hrih^z)) is equal to the original height designation z. With the nodes interconnected in this manner, the target ring is accessible to message data on every
5 third step on level one. In an interconnect structure having this form, although nodes having two output data terminals are suitable, advantages are gained by increasing the number of output data terminals to three. Thus, one data output terminal of a node on a given level is connected to two nodes on that level and to one node on a
AMENDED SHEET
CA 02227271 1998-01-20
-· ' >> ? ' ·» > « -» -»» η » η > ' > Ο ·* 1 ^444 44 Ο • -> > Λ -.tn ’ > η * a *·» »
M-3240 PCT ’ <sup>1</sup> ·'·· ·· ·
-47- ’ successive level. Accordingly, each level has 3<sup>J</sup> heights and a message packet and a message can descend to a lower level every other step.
In this manner, many different interconnect structures are formed by utilizing i<sup>J</sup> heights per level for various numbers i. Where i is equal to 4, the fourth height transformation h<sub>T</sub>(hy(h<sub>T</sub>(h<sub>T</sub>(z)))) is equal to the original height designation z. If i is 5, the fifth height transformation h^h^hyOïTÎh-Xz))))) is the same as the original height z, and so forth.
In the variable base i<sup>J</sup> height structure embodiment, whether the target ring is accessible from a particular node is determined by testing a more than one bit of a code designating the target ring.
Variable Base Transformation Technique Embodiment
In a still further embodiment of an interconnect structure, the height transformation technique outlined hereinbefore is modified as follows. In this embodiment, a base three notation height transform technique is utilized rather than the binary height transformation technique discussed previously. In the base three 2 0 transformation technique, a target ring is designated by a sequence of base three numbers. Thus, one a level n, the n low-order base three numbers of the height designation are reversed in order, the low-order-bit-reversed height designation is incremented by one, and the n low-order base three numbers are reversed back again. An exemplary interconnect structure has four levels (J==3 plus one), nine 25 heights (3<sup>J</sup> = 3<sup>3</sup>) per level and five nodes (K=5) per height. In accordance with the base three height transformation technique, node N<sub>2(2</sub>oi)3 on level 2 has a first data input terminal connected to a data output terminal of node N<sub>3(201)2</sub> on level 3, a second data input terminal connected to a data output terminal of node N<sub>2(220)2</sub> on level two. Node N^ojp also has a first data output terminal connected to a data
AMENDED SHEET
CA 02227271 1998-01-20
M-3240 PCT
Ί 9 □ e» a *i ->
» 9 >
· · · ·»«09 a ο · o « ·» a · · *·«· β · ·99 ββ »*·· ··«
48input terminal of node Ni^qj^ on level one and a second data output terminal connected to a data input terminal of node N<sub>2(211)4</sub>. Node N<sub>2ç2a</sub>i)3 also has a control input bit connected to a control output bit of node N<sub>1(200)3</sub> and a control output bit connected to a control input bit of node N<sub>3(2n)3</sub>. In this embodiment, the header includes a synch bit followed by the address of a target ring in base three. For example, the base three numbers are symbolized in binary form as 00, 01 and 10 or using three bits in the form 001, 010 and 100.
Further additional height transformation techniques are possible using various numeric bases, such as base 5 or base 7 arithmetic, and employing the number reversal, increment and reversal back method discussed previously.
Multiple Level Step Embodiment
In another embodiment, an interconnect structure of the nodes have ten terminals, including five input terminals and five output terminals. The input terminals include three data input terminals and two control input terminals. The output terminals include three data output terminals and two control output terminals.
In this interconnect structure, nodes are generally connected among five adjacent cylindrical levels. Specifically, nodes Ν(Τ,θ,ζ) at the T cylindrical level have terminals connected to nodes on the T, T+l, TT2, T-l and T-2 levels. These connections are such that the nodes Ν(Τ,θ,ζ) have data input terminals connected to nodes on the same level T, the next outer level T+l and the previous outer level T+2. In particular, nodes Ν(Τ,θ,ζ) have data input terminals connected to data output terminals of nodes Ν(Τ,θ-1^τ(ζ)), NfT+Ι,θ-Ι,ζ) and Ν(Τ+2,θ-1,ζ). Nodes Ν(Τ,θ,ζ) also have control output terminals, which correspond to data input terminals, connected to nodes on the next outer level T+l and the previous outer level T+2. Nodes Ν(Τ,θ,ζ) have control output terminals connected to control input terminals of nodes Ν(Τ+1,θ-1,ζ) and Ν(Τ+2,θ-1,ζ). Nodes N(T,0,z) also have
AMENDED SHEET
CA 02227271 1998-01-20
M-3240 PCT
-49data output terminals connected to nodes on the same level T, the next inner level ΤΙ and the subsequent inner level T-2. In particular, nodes Ν(Τ,θ,ζ) have data output terminals connected to data output terminals of nodes Ν(Τ,θ+1,Η<sub>τ</sub>(ζ)), N(T1,04-1,z) and N(T-2,04-l,z). Nodes ΝίΤ,θ,ζ) also have control input terminals, which correspond to data output terminals, connected to nodes on the next inner level T-l and the subsequent inner level T-2. Nodes Ν(Τ,θ,ζ) have control input terminals connected to control output terminals of nodes Ν(Τ-1,θ+1,ζ) and N(T-2,04-l,z).
This ten-terminal structure applies only to nodes at the intermediate levels 2 to J-2 since nodes at the outer levels J and J-l and at the inner levels 1 and 0 have the same connections as the standard six-terminal nodes.
This ten-terminal structure allows messages to skip past levels when possible and thereby pass through fewer nodes at the cost of increasing logic at the nodes. Only one message is allowed to enter a node at one time. The priority of message access to a node is that a message on the same level has top priority, a message from a node one level removed has second priority and a message from a node two levels away has last priority. Messages descend two levels whenever possible. The timing rules for an interconnect structure using the six-terminal nodes. Advantages of the ten-terminal node interconnect structure are that messages pass more quickly through the levels.
Other interconnect structure embodiments include nodes having more than ten terminals so that data and control terminals are connected to additional nodes on additional levels. For example, various/nodes N(T,0,z) also have associated control input terminals and data output terminals, which are connected to nodes on inner levels T-3, T-4 and so on. In other examples, various nodes N(T,0,z) also have associated control output terminals and data input terminals, which are connected to
AMENDED SHEET
CA 02227271 1998-01-20
<img file="CA2227271C_D0007.tif" />
M-3240 PCT “49/1nodes on outer levels T4-3, T+4 and so on. Γη various interconnect structure embodiments, nodes may be connected among all levels or selected levels.
Multiple Interconnections to the Same Level Embodiment
Additional interconnect structure embodiments utilize additional interconnections among nodes on the same level. Specifically, nodes N(T,0,z) on the level T have interconnections in addition to the connections of (1) an output data terminal connected to an input data terminal of nodes N(T,04-l,h<sub>T</sub>(z)) and (2) an input data terminal connected to an output data terminal of nodes Ν(Τ,θ-1,Η<sub>τ</sub>(ζ)). Thus nodes N(T,0,z) on the level T have interconnections including a connection of (1) an output data terminal connected to an input data terminal of nodes N(T,0+l,g<sub>T</sub>(z)) and (2) an input data terminal connected to an output data terminal of nodes ΝΠζθ-Ι,Ιίτζζ)). Like cylinder height h<sub>T</sub>(z), height g-r(z) is on the half of the interconnect structure of level T that is opposite to the position of height z (meaning bit T of the binary code describing height h<sub>T</sub>(z) and gy(z) is complementary to bit T of height z).
Multiple Interconnections to a Next Level Embodiment
A multiple interconnections to a next level embodiment is similar to the multiple interconnections to the same level embodiment except that node N(T,0,z) has one output data terminal connected to one node N(T,04-1,11-^)) on level T and two output data terminals connected to two nodes N(T-l,04-l,z) and N(T-1,04-1,g<sub>T</sub>. <sub>t</sub>(z)) on level T-l. Thus one data oulptit interconnection traverses the same level, a second interconnection progresses one level and a third interconnection both progresses one level and traverses. Like height h-r(z), height g-r(z) is on the half of the interconnect structure of level T that is opposite to the position of height z.
AMENDED SHEET
CA 02227271 1998-01-20
M-3240 PCT
-49/2Conflicts between node access are resolved by applying a first priority to messages moving on the same level, a second priority to messages progressing one level and a third priority to messages both progressing one level and traversing.
The description of certain embodiments of this invention is intended to be illustrative and not limiting. Numerous other embodiments will be apparent to those skilled in the art, all of which are included within the broad scope of this invention. For example, many different types of devices may be connected using the interconnect structure including, but not limited to, workstations, computers, 10 terminals, ATM machines, elements of a national flight control system and the like.
Also, other interconnection transformations other than h<sub>T</sub> and H<sub>T</sub> may be implemented to describe the interconnections between nodes.
The description and claims occasionally make reference to an interconnect 15 structure which is arranged in multiple dimensions. This reference to dimensions is useful for understanding the interconnect structure topology. However, these dimensions are not limited to spatial dimensions but generally refer to groups of nodes which are interconnected in a particular manner.
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Contents106
40 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9 Sheet 10 Sheet 11 Sheet 12 Sheet 13 Sheet 14 Sheet 15 Sheet 16 Sheet 17 Sheet 18 Sheet 19 Sheet 20 Sheet 21 Sheet 22 Sheet 23 Sheet 24 Sheet 25 Sheet 26 Sheet 27 Sheet 28 Sheet 29 Sheet 30 Sheet 31 Sheet 32 Sheet 33 Sheet 34 Sheet 35 Sheet 36 Sheet 37 Sheet 38 Sheet 39 Sheet 40
33 members in 14 offices
Priority claims9
| Document | Office | Kind | Date |
|---|---|---|---|
| 08505513 | United States of America | – | |
| 50551395 | United States of America | A | |
| 50551395 | United States of America | A | |
| 9611828 | United States of America | W | |
| 9611828 | United States of America | W | |
| 08505513 | – | – | – |
| PCTUS9611828 | – | – | – |
| US19950505513 | – | – | – |
| WO1996US11828 | – | – | – |
Members33
| Document | Office | Kind | |
|---|---|---|---|
| CA2227271A1 | Canada | A1 | |
| WO9704399A2 | World Intellectual Property Organization (WIPO) | A2 | |
| AU6498896A | Australia | A | |
| WO9704399A3 | World Intellectual Property Organization (WIPO) | A3 | |
| EP0842473A2 | European Patent Office (EPO) | A2 | |
| MX9800626A | Mexico | A | |
| KR19990035759A | Republic of Korea | A | |
| HK1010926A1 | Hong Kong, China | A1 | |
| US5996020A | United States of America | A | |
| JP2000500253A | Japan | A | |
| NZ313016A | New Zealand | A | |
| AU725826B2 | Australia | B2 | |
| EP1058194A2 | European Patent Office (EPO) | A2 | |
| EP1058195A2 | European Patent Office (EPO) | A2 | |
| US6272141B1 | United States of America | B1 | |
| US2001021192A1 | United States of America | A1 | |
| DE1058195T1 | Germany | T1 | |
| US2001034798A1 | United States of America | A1 | |
| GR20010300054T1 | Greece | T1 | |
| ES2160556T1 | Spain | T1 | |
| NZ503094A | New Zealand | A | |
| CA2227271CThis record | Canada | C | |
| KR100401682B1 | Republic of Korea | B1 | |
| JP3594198B2 | Japan | B2 | |
| EP0842473B1 | European Patent Office (EPO) | B1 | |
| AT327537T | Austria | T | |
| ATE327537T1 | Austria | T1 | |
| US7068671B2 | United States of America | B2 | |
| DE69636165D1 | Germany | D1 | |
| US2007186008A1 | United States of America | A1 | |
| US7426214B2 | United States of America | B2 | |
| EP1058194A3 | European Patent Office (EPO) | A3 | |
| EP1058195A3 | European Patent Office (EPO) | A3 |
2 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| LapsedLapsedMKLA | MKLA | |
| Examination requestEEER | EEER |
Numbers
- Publication
- 2227271
- Publication, DOCDB
- 2227271
- Publication, EPODOC
- CA2227271
- Application
- 2227271
- Application, DOCDB
- 2227271
- Application, EPODOC
- CA19962227271
Titles2
- English
- MULTIPLE LEVEL MINIMUM LOGIC NETWORK
- French
- RESEAU LOGIQUE MINIMAL A NIVEAUX MULTIPLES
Classification
- CPC, 6
- G06F15/17393
- G06F15/16
- G06F15/17375
- G06F15/803
- H04L12/42
- H04L45/06
- IPC, 4
- G06F15 173
- G06F15 80
- H04L12 56
- H04L12 58