Pseudo-random generator

WO 95/20278

PCIYUS95/00716

- ί PSEUDO-RANDOM GENERATOR

Field of the Invention .....

Thia invention relates generally to pseudo-random bit generators and, more specifically, to circuitry and concomitant methodology for generating cryptographically strong pseudo-random bits.

Background^ the Invention

A very large number of important processes and methods use an auxiliary input which is assumed to he truly random. Examples of such processes and methods include sorting, simulation and testing of complex systems, encryption, and many other cryptographic primitives. Producing a truly random auxiliary input of sufficient length is difficult. Typically, the auxiliary input is produced by a pseudo-random bit generator. Informally, a pseudo-random bit generator is any process or method which takes a short truly random string and produces a long pseudo-random¹ string.

Many pseudo-random bit generators have been proposed and discussed in prior art literature, such as the popular linear congruentiai bit generator. In evaluating the utility of these bit generators, the conventional approach is to subject each bit generator to a standard regimen of empirical and analytical statistical tests to determine if the generators produce acceptable random bits. Those generators that pass the standard tests are often assumed to produce sufficiently good pseudo-random bit streams for the various purposes for which they are to be employed.

However, this assumption may be erroneous. For instance, it has been shown that the linear congruentiai bit generator is hardly general purpose since after observing its outputs for a short period, it becomes possible to compute the future outputs correctly. It has also been shown how to predict the bits of the following generator: given a polynomial, output successive digits of the algebraic number defined by the polynomial. As another example, Monte Carlo simulations of a well-known physical system were recently shown to give results far from the known values when several well-known generators were used as input for the simulations.

While certain traditional generators may not be general purpose,

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PCT/US95/00716 they may be sufficient for certain purposes. For example, it has been shown that a few simple bit generators (including the linear congruential) are sufficient, in a rigorous sense, for a few specific applications. In short, there are examples where the traditional generators are known to be sufficient and there are examples where they are known to be insufficient. For all other cases there are no guarantees. Moreover, for complex methods and processes it is unlikely that the traditional generators will ever be proven to produce sufficiently random output.

Most recently, a different approach to pseudo-random bit generation has been developed based on the theory of one-way functions. For the immediate discussion, a one-way function is a function that is easy to compute but hard to invert on an overwhelming fraction of its range. With this notion in mind, a cryptographically strong pseudo-random (CSPR) bit generator is a generator that takes a short, truly random seed as input, then repeatly uses a one-way function to produce a long pseudo-random string of bits such that there is no feasible technique or procedure which can distinguish between the outputs of a CSPR bit generator and a truly random string of bits.

It is also known that a CSPR bit generator will pass all statistical tests whose running times are small compared to the time required to invert the one-way function. In particular, using CSPR bits rather than truly random bits in test or other application environments whose running times are small with respect to the time to invert a one-way function will not impact on the results in any demonstrable way.

In addition to the many direct applications of CSPR bit generators mentioned previously, these bit generators may be used to compute cryptographically strong pseudorandom functions (CSPR functions). These functions take two parameters, namely, a function index and a function input. For a randomly chosen fixed index, an adversary with no knowledge of the index cannot choose a function input and then predict even a single bit of the resulting function value in a feasible amount of time. This is true even if the adversary has already seen many function values for many function inputs of its choosing.

CSPR functions have several applications. Two important applications are as follows. First, they can be used in a simple protocol for identifying party À to party B over a non-secure channel when À and B share a secret key. The shared key is used as a CSPR function index. B queries any party on the channel claiming to be A with a random function input. Only A will be able to return the correct function value.

Second, CSPR functions can be used to distribute independent

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- 3random bits to each of the processes in a parallel or distributed computation. A single seed is first broadcast to each process. This shared seed is used as the CSPR function index. Using its process identification number as a function input, each process computes a CSPR function value as its random seed. Each process may now use this seed and a CSPR bit generator to compute CSPR bits for its own use.

Summary of the Invention

Cryptographically strong pseudo-random bit generators and functions are implemented by circuitry and a concomitant methodologies which utilize secure block cypher encoders to implement a cryptographically strong pseudo-random bit generator.

Broadly, in accordance with one serial aspect of the present invention, a stream of cryptographically strong pseudo-random bits is generated from first and second seeds, of the same length, and a block cypher encoder having a fixed random encoder key. The first seed serves as the first input to the block cypher encoder. Each subsequent input to the block cypher encoder is provided as the last output of the block cypher encoder. Each bit in the stream of cryptographically strong pseudorandom bits is determined in correspondence to an inner product between the input to the block cypher encoder and the second seed.

In accordance with another serial aspect of the present invention, a stream of cryptographically strong pseudorandom bits is generated from a first seed and a plurality S of second seeds, all seeds being of the same length, and a block cypher encoder having a fixed random encoder key. The first seed serves as the first input of the block cypher encoder. Each subsequent input to the block cypher encoder is provided as the last output of the block cypher encoder. S consecutive bits in the stream of cryptographically strong pseudorandom bits are determined in correspondence to S distinct inner products between the input to the block cypher encoder and the S second seeds.

In accordance with a parallel aspect of the present invention, a stream of cryptographically strong pseudorandom bits in groups of N is generated with N block cypher encoders, each having a different fixed random key, and N first and N second seeds, all of the seeds being of the same length. Each of the first seeds serves as one input to a corresponding block cypher encoder. Each subsequent input to each encoder is provided as its last output. Output bits in each group in the stream of cryptographically strong pseudo

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2179497 PCT/US95/007Ï6 random bits are determined in correspondence to an inner product between. the input to each encoder and a corresponding second seed.

In accordance with another parallel aspect of the present invention, a stream of cryptographically strong pseudo-random bits in groups of NS is generated with N block cypher encoders, each having a different fixed random key, and N first and NS second seeds, all of the same length. Each of the first seeds serves as one input to a corresponding block cypher encoder. Each subsequent input to each encoder is provided as its last output. Output bits in each group in the stream of cryptographically strong pseudo-random bits are determined in correspondence to S inner products between the input to each encoder and the S second seeds.

In accordance with yet another serial aspect of the present invention, a stream of cryptographically strong pseudo-random bits is generated with two block cypher encoders, each having a different fixed random encoder key, and first and second seeds of the same length. The two block cypher encoders are connected such that the output of the first encoder serves as the input of the second encoder. Moreover, the output of the second encoder serves as the next input to the first encoder once the first seed has been processed by the first encoder. The stream of cryptographically strong pseudo-random bits is determined in correspondence to an inner product between successive inputs to the first encoder and the second seed.

In accordance with still another serial aspect of the present invention, a stream of cryptographically strong pseudorandom bits is determined with two block cypher encoders, each having a different fixed random encoder key, and a first seed and S second seeds all of the same length. The two block cypher encoders are connected such that the output of the first encoder serves as the input of the second encoder. Moreover, the output of the second encoder serves as the next input to the first encoder once the first seed has been processed by the first encoder. The stream of cryptographically strong pseudo-random bits is determined in correspondence to S inner products between successive inputs of the first encoder and the S second seeds.

In accordance with a combined serial-parallel aspect of the present invention, a stream of cryptographically strong pseudo-random bits in sets of N is generated with: N groups of two-block cypher encoders, each of the two-block encoders having a different fixed random encoder key; and N first seeds and N second seeds, all seeds being of the same length. Each of the two-block cypher encoders is connected such that the output of the first encoder serves as the input

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-5of the second encoder. Moreover, the output of the second encoder serves as the next input to the first encoder once the corresponding first seed from the N first seeds has been processed by the first encoder. Output bits in each set in the stream of cryptographically strong pseudo-random bits are determined in correspondence to N inner products between successive inputs of the first encoder of each of the two-block cypher encoders and its corresponding second seed from the N second seeds.

In accordance with another combined serial-parallel aspect of the present invention, a stream of cryptographically strong pseudo-random bits tn sets of NS is generated with: N groups of two-block cypher encoders, each of the two-block encoders having a different fixed random encoder key; and N first seeds and NS second seeds all of the same length. Each of the two-block cypher encoders is connected such that the output of the first encoder serves as the input of the second encoder. Moreover, the output of the second encoder serves as the next input to the first encoder once the corresponding first seed from the N first seeds has been processed by the first encoder. Output bits in each set in the stream of cryptographically strong pseudo-random bits are determined in correspondence to NS inner products between successive inputs of the first encoder and the S second seeds corresponding to each of the N groups of two20 block encoders.

In accordance with the pseudo-random function aspect of the present invention, a cryptographically, strong pseudo-random function value is computed from a function index and a function input. The function index includes first and second seeds of length n and a key for a block cypher encoder.

The function input is a string of length m. A bit pointer is initialised to point to the least significant bit of the function input. Each block cypher is arranged to feed back its output to its input. The current block cypher input is initially assigned to be the value of the first seed. An output stream of length 2n is generated in correspondence to 2n inner products between 2n successive inputs of the block cypher encoder and the second seed. If the bit pointer does not point to the most significant bit, then one of two steps is completed, namely: (1) if the input bit in the function input pointed at by the bit pointer is a first bit value, then the first n bits of the output stream become the current cypher input; or (2) if the bit in the function input pointed at by the bit pointer is a second bit value, then the last n bits of the output stream become the current cypher input. In either case, the bit pointer is incremented, and another output stream of length 2n is computed using the current block cypher input. If the bit pointer does

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PCT/US95/00716 point to the most significant bit, then the function value is either determined to be the first n bits of the previous output stream if the most significant bit of the function input is a first bit value, or the function value is determined to be the last n bits if the most significant bit is a second bit value.

A feature of the inventive aspects of the present invention is that

CSPR functions may be based on any of the CSPR bit generators previously summarized.

The organization and operation of this invention will be understood from a consideration of the detailed description of the illustrative embodiment, which follows, when taken in conjunction with the accompanying drawing.

Brief Description of the Drawing

FIG. 1 is a block diagram of an illustrative serial, cryptographically strong random bit generator in accordance with the present invention;

FIG. 2 is a block diagram of another illustrative serial, cryptographically strong random bit generator in accordance with the present invention.

FIG. 3 is a block diagram of an illustrative parallel, cryptographically strong random bit generator in accordance with the present invention; and

FIG. 4 is a block diagram of another illustrative serial, secure, cryptographically strong random bit generator in accordance with the present invention.

Detailed Description

By way of introducing terminology and notation useful in elucidating the present invention, an overview discussion is first presented;

following this overview, illustrative embodiments in accordance with the present invention are described.

Overview

À ’feasible computation on inputs of length M takes time proportional to Μ, M , or M , where C is some fixed constant. Infeasible computations are those that are not feasible. À function F is one-way if it is feasible to compute but infeasible to invert for a random element in its range. A function is a one-way permutation if it is one-way and, in addition, length preserving and one-to-one, that is, if F(x) = y, then the lengths of x and y are equal and for every y there is exactly one x. Hereafter, F will denote a one-way

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PCT/US95/00716 permutation.

Two distributions μ_υ μ₂ on binary strings are indistinguishable if any feasible computation that guesses that a given string is generated under μ! or μ₂ succeeds with probability l/2+«(n) where €(n)is negligible, that is, e(n)=l/T(n) and T(n) is the running time of some infeasible computation. A cryptographically strong pseudo-random distribution is indistinguishable from the uniform distribution.

À cryptographically strong pseudo-random bit generator G accepts a random seed x of length X and outputs a longer bit string y of length Y=X°^ and the output distribution is pseudo-random. This means that even a single bit of y cannot be predicted by looking at other bits of y.

Whereas the most recent realizations disclosed in the prior art to configure cryptographicaily-strong pseudorandom bit generators utilize one-way functions, the subject matter in accordance with the present invention is based on a block cypher encoder — such an encoder may be realized via the Data

Encryption Standard (DES), as published by the National Bureau of Standards, Department of Commerce, FIPS, pub 46, January, 1977. DES has a reasonably fast implementation and is commercially available; for example, device type VM009 available from the VLI Technology Inc. of Tempe, AZ implements DES.

A block cypher encoder takes as input a random key k and an input string x of size X to produce an output string of size X. For a fixed key k, the output y of a block cypher encoder, denoted F(k,x), is a permutation. In addition, the present invention makes more efficient use of the input seeds than the realizations in the prior art.

Illustrative Embodiments

As alluded to in the Overview, the generators of the present invention are made practical by basing them on block cyphers¹ encoders. One manner in which a block cypher encoder is used as a fundamental component to construct a cryptographically strong pseudo-random bit generator is set forth with reference to FIG. 1. In FIG. 1, a serial block cypher encoder is depicted by element 150; the permutation effected by block cypher 150 is denoted F. A fixed random key k, provided by random key generator 140, serves as one input to block cypher encoder 150 via bus 141. The other input to block cypher encoder is provided via bus 131 from an input register 130, which is shown as providing a set of bits denoted X* on output bus 131. Input register 130 has two inputs, namely, the first seed χθ as provided by first seed generator 110 over bus 111,

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PCT/US95/00716 and the output of block encoder 150, denoted x^, as provided by feedback bus 151. Input register 130 operates so that X| is first assigned the value x^, whereas any the subsequent value of x^ is provided by overwriting the last value of χ^ with the updated value Xi₊₁. The input X[ to encoder 150 also serves as one input to inner product device 160, also via bus 131» In addition, inner product device 160 has as an input, via bus 121, the second seed h produced by second seed generator 120. In general, the length of the first and second seeds are the same. The length of the random key does not need to be the same length as the first and second seeds; the size of the random key usually depends on how the block cypher works. Inner product device 160 determines an inner product, represented by <x.,h>=b., as follows: (a) compute the bitwise AND of x. with h; and (b) output as the inner product result the parity of all bits from the bitwise ANDing, that is, output a 0 if there are an even number of one bits, and a 1 if there are an odd number of one bits. Each b. bit is sequentially provided on output lead 161.

Another embodiment in which a block cypher encoder is used as a fundamental component to construct a cryptographically strong pseudo-random bit generator is set forth with reference to FIG. 2. In FIG. 2, a serial block cypher encoder is depicted by element 250; the permutation effected by block cypher 250 is denoted F. A fixed random key k, provided by random key generator 240, serves as one input to block cypher encoder 250 via bus 241. The other input to block cypher encoder is provided via bus 231 from an input register 230, which is shown as providing a set of bits denoted x^ on output bus 231. Input register 230 has two inputs, namely, the first seed χθ as provided by first seed generator 210 over bus 211, and the output of block encoder 250, denoted xj₊₁, as provided by feedback bus 251. Input register 230 operates so that X£ is first assigned the value Xq, whereas any the subsequent value of x^ is provided by overwriting the last value of with the updated value X|_+i. The input x* to encoder 250 also serves as one input to inner product device 260, also via bus 231. In addition, inner product device 260 has as inputs, via bus 221, the S second seeds h_x, h₂, hg produced by second seed generator 220. In general, the length of the first seed, the S seeds, and the random key are all the same. Inner product device 260 determines, during the cycle, a set of S inner products, the set being represented by {<Xj,hj>, <χ^^>, —, <x-,hg>} (or as <x_i,£> in compact notation), as follows: (a) compute the bitwise AND of x^ with hj, j—1, 2, ..., S; and (b) output as the j⁴¹¹ inner product result the parity of all bits from the bitwise ANDing, that is, output a 0 if there are an even number

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- 9 of one bits, and a 1 if there are an odd number of one bits. The result of the j^thinner product is a bit, denoted bj, which is the bit in the set of S consecutive bits that compose the stream of cryptographically strong pseudo-random bits that appear on output bus 261 of inner product device 260. Another way to represent the output on bus 261 for the cycle is b.j, j=l, 2, ..., S, as depicted in FIG. 2

Yet another manner in which a block cypher encoders are used as a fundamental component to construct a cryptographically strong pseudo-random bit generator is set forth with reference to FIG. 3. In FIG. 3, one block cypher encoder in an arrangement of parallel block cypher encoders 350, 355, ... is depicted by element 350; the permutation effected by each block cypher encoder is denoted F. Elements 310, 320, 330, 340, 350, and 360 in FIG. 3 operate in the same manner as described with respect to elements 110, 120, 130, 140, 150, and 160 in FIG. 1. Similarly, elements 315, 325, 335, 345, 355, and 365 in FIG. 3 operate in the same manner as described with respect to elements 110, 120, 130, 140, 150, and 160 in FIG. 1; and so forth for the remaining encoders (not shown).

In particular, fixed random key kp provided by random key generator 340, serves as one input to block cypher encoder 350 via bus 341. The other input to block cypher encoder is provided via bus 331 from an input register 330, which is shown as providing a set of bits denoted xj¹ on output bus 331. Input register 330 has two inputs, namely, the first seed Xq as provided by first seed generator 310 over bus 311, and the output of block encoder 350, denoted Xi+p as provided by feedback bus 351. Input register 330 operates so that iq¹ is first assigned the value xJ, whereas any the subsequent value of x/is provided by overwriting the last value of with the updated value Xj+_P The input Xj¹ to encoder 350 also serves as one input to inner product device 360, also via bus 331. In addition, inner product device 360 has as an input, via bus 321, the second seed h¹ produced by second seed generator 320. In general, the length of the first χθ and second h¹ seeds and the random key k¹ are the same. Inner product device 360 determines an inner product, represented by <x₁¹,h> = b/, as follows: (a) compute the bitwise AND of s^¹ with h^l; and (b) output as the inner product result the parity of all bits from the bitwise ANDing, that is, output a 0 if there are an even number of one bits, and a 1 if there are an odd number of one bits. Each bj¹ bit is provided on output lead 361.

In addition, fixed random key k£, provided by random keygenerator 345, serves as one input to block cypher encoder 355 via bus 346. The other input to block cypher encoder is provided via bus 336 from an input

I

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- 10 register 335, which is shown as providing a set of bits denoted x^ on output bus 336. Input register 335 has two inputs, namely, the first seed x^ as provided by first seed generator 315 over bus 316, and the output of block encoder 355, denoted x²+1, as provided by feedback bus 356. Input register 335 operates so that x^ is first assigned the value Xq, whereas any the subsequent value of _Xi² is provided by overwriting the last value of x^ with the updated value x^p The input x$² to encoder 355 also serves as one input to inner product device 365, also via bus 335. In addition, inner product device 365 has as an input, via bus 326, the second seed h² produced by second seed generator 325. In general, the length of the first xj and second h^z seeds and the random key k² are the same. Inner product device 365 determines an inner product, represented by <Xj²,h> = b², as follows: (a) compute the bitwise AND of s^² with h^l; and (b) output as the inner product result the parity of all bits from the bitwise ANDing, that is, output a 0 if there are an even number of one bits, and a 1 if there are an odd number of one bits. Each b² bit is provided on output lead 361.

Finally, to control the production of the parallel bits bj¹, b², ...

during the i^tlx cycle, timing device 370 is coupled to each block cypher encoder 330, 335, ... and each inner product device 360, 365, ... to output the parallel bits during a desired cycle time interval.

All of the above implementations have considered feeding back the output of a given block cypher encoder to its input to provide what is, in effect, as sequence of random seeds for processing. To provide an added measure of security, the implementation of FIG. 4 is employed. In particular, with reference to FIG. 4, two block cypher encoders 450 and 455 are used as fundamental components to construct a cryptographically strong pseudo-random bit generator. In FIG. 4, a first block cypher encoder is depicted by element 450 and a second block cypher encoder is depicted by element 455; the permutation effected by each block cypher encoder is denoted F. The output of block cypher encoder 450 is connected to the input of block cypher encoder via bus 451. A first fixed random key k_b provided by random key generator 440, serves as one input to block cypher encoder 450 via bus 441. À second fixed random key k₂, provided by random key generator 445, serves as one input to block cypher encoder 455 via bus 446. The other input to block cypher encoder is provided via bus 431 from an input register 430, which is shown as providing a set of bits denoted \ on output bus 431. Input register 430 has two inputs, namely, the first seed χθ as provided by first seed generator 410 over bus 411, and the output of block encoder 455, denoted X£₊₁, as provided by feedback bus 456. Input register 430

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PCTYUS95/00716 operates so that is first assigned the value χθ, whereas any the subsequent value of x^ is provided by overwriting the last value of with the updated value Xi₊i- The input X| to encoder 450 also serves as one input to inner product device 460, also via bus 431. In addition, inner product device 460 has as an input, via bus 421, the second seed h produced by second seed generator 420. In general, the length of the first and second seeds and the random keys ki and k₂are the same. Inner product device 460 determines an inner product, represented by <x.,h>=bj, as follows: (a) compute the bitwise AND of x. with h; and (b) output as the inner product result the parity of all bits from the bitwise ANDing, that is, output a 0 if there are an even number of one bits, and a 1 if there are an odd number of one bits. Each bj bit is sequentially provided on output lead 461,

It is clear to one with ordinary skill in the art that, because of the teachings of with respect to the embodiment of FIG. 2, that seeds h¹, h², ... in

FIG. 3 or the seed h in FIG. 4 may be replaced by a plurality of seeds (e.g,, for h¹ ** hj, hg, ...) so that a multiple number of bits per inner product per cycle would be generated. It is also clear that the two-block encoder of FIG. 4 may be combined with the embodiments that teach a single block encoder to yield combined serial-parallel variations on the generation of stream of cryptographically strong pseudorandom output bits.

Embodiment for Pseudo-Random Functions

Let G() designate a CSPR bit generator which, as in the foregoing section, takes as input strings x, k and h, where x and h are n bit strings. Let H() designate a CSPR function. G() will be used in order to compute H(). In fact, the inputs of G(), the strings x, k, and h, are together the function index of H(). Let the function input of H() be denoted d, an m bit string. For the sake of this description of HQ, G() outputs a string of length 2n. The first n bits are designated y_0 and the second n bits are y_l. Let hit (d,i) (which is shorthand

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- 12 notation for a bit pointer) be the bit of function input. H(x,k,h,d) is computed as follows:

1. x_0 = x.

2. for i=l to m,

a. compute G(x_(i-l),k,h) = y_0 y_l

b. if bit(d,i) = 0, then x_i = y_0, else if bit(d,i) = 1, then x_i — y_l

c. output x_m.

The above technique for determining H(x,k,h,d) has been described 10 with reference to the most basic generator G() as described with respect to

FIG. 1. It is also clear that the other CSPR bit generators disclosed herein, such as represented by FIG. 2, 3 or 4, or combinations thereof, can be used to compute a CSFR function with only minor modifications to the above scheme.

It is to be understood that the above-described embodiment is 15 simply illustrative of the principles in accordance with the present invention.

Other embodiments may be readily devised by those skilled in the art which may embody the principles in spirit and scope. Thus, it is to be further understood that the circuit arrangements described herein are not limited to the specific forms shown by way of illustration, but may assume other embodiments limited only by the scope of the appended claims.