Method and system for the arrangement of vocoder data for the masking of transmission channel induced errors

WO93/15502 2l2a708 Pcr/uss3/oo7o3 METHOD AND SYSTEM FOR THE ARRANGEMENT OF VOCODER DATA FOR THE MASKING OF TRANSMISSION CHANNEL INDUCED ERRORS BACKGROUND OF THE INVENTION I.

Field of the Invention The present invention relates to the organization of data for trancmi~sion.

More particularly, the present invention relates to a novel and improved method and ~ysleln for the packing of variable rate vocoder generated data into data packets for tra~cmicsion, and for the unpacking of received variable vocoder data packets for speech reconstruction.

II.

Description of the R~l~te-l Art In the field of digital communications various arrangements of digital data for transmission are used.

The data bits are commonly organized into data packets for transfer over the communication medium.

In the case of data generated by a vocoder, the data is also organized for trarl~ sion.

Generally in the preparation of a data packet for tra~micsion over a communication channel some form of forward error correction encoding may be used to protect the data from tra~cmission channel induced errors.

In the event that channel errors do occur in the error correction encoded data, in many instances the errors may be detected and corrected.

While error correction techniques do provide a valuable method for reducing channel errors, such techniques alone may not sufficiently provide the level of protection necessary.

In the case where portions of the data packet are of significantly greater importance than others, it is desirable to provide further forms of protection from channel errors.

An example of such a case is where the data packet contains vocoder data where certain parameters are of greater significance in reconstruction of the speech data therefio~ It is therefor an object of the present invention to provide in communication of digital information further protection of more significant portions of the information from channel induced errors.

Wo 93/15502 Pcr/uS93/00703 ~:12~ 7~ 3 SUMMARY OF THE INVENTION The present invention is a novel and improved method and apparatus for organizing vocoder output data representative of vocoded 5 speech into data packets for traI-cmicsion, and extracting from the received data packets the data for input to the vocoder for reconstruction into speech.

In Code Division Multiple Access (CDMA) communications, as in all digital communications syslellls, tral cmiss10n channel conditions may 10 induce errors into the digital data as it is communicated over the transmission medium.

Error correction coding techniques, along with power control techniques, can reduce channel errors.

However there are limitations to each of these techniques which can result in less than optimum ~ys~e~. performance.

For example, in the CDMA sysl~lll an increase in transmitter power can reduce susceptibility to channel errors.

However increases in transmitter power presents an adverse impact on sysLelll capacity.

In the CDMA sy~lelll each user's signal appears as inler~elence to others.

There is also a limit on the total noise in the syslem to which the signal 20 processing gain of a CDMA receiver can still extract its intended signal from the noise.

Total channel illtel~rence caused by the users is thus a function of the number of users and the power at which they are transmifflng.

As the signal power of a user's transmitter increases, the signal to noise ratio of the intended user receiver improves.

However this 25 particular user's increase in signal power serves as an increase in inlelrerellce to u~inten~led recipient user receivers.

As such there is a decrease in signal to noise ratio, with a greater reliance on processing gain to extract these users signals which may result in a degradation in per~orlllance.

Therefore although increases in transmitter power can 30 provide a reduction in susceptibility to channel induced errors, system capacity factors limit its usage.

The present invention implements a data format scheme that improves the reliability of the data by masking some of the CDMA transmission channel errors.

In the variable rate vocoder, speech is 35 generally encoded at the highest rate to achieve the highest quality of sound upon reconstruction.

However, pauses in speech and background 2128708 P~TlUS931007O3 3 IPE~YJS 15 SEP 199~ noise are less important and may be encoded at a lower rate.

In data encoded at the highest encoding rate it is particularly important to provide a high level of protection on the data to ensure that upon reception decoding reliable data is used.

In data encoded at the highest 5 encoding rate, certain parameter data, in particular certain bits of this parameter data, representative of the encoded speech are of greater significance than others.

The present invention recognizes the effect of CDMA channel errors on transmitted data, and provides a data format which reduces the impact of the channel errors on the more significant 10 data portions.

The present invention ~ oses a method and syslem by which certain parameter data and certain bits of the parameter data are organized to mask channel errors.

In accordance with the present invention it is realized that data which is transmitted first in a 15 transmission data packet is less susceptible to CDMA channel errors.

When such errors occur, they generally occur in a short burst, typically a length of eight or less bits for the preferred full rate frame rate.

Another error condition occurs when the receiver cannot correctly make a rate ~le~ on for the received frame of vocoder data.

However 20 in this case the vocoder may be given a packet of random bits.

The present invention provides a scheme for distinguishing between these two cases.

In the present invention a data packet is organized with some of the most perceptually significant bits of vocoder parameter data placed 25 at the beginning of the data packet while the remainder of the most perceptually significant bits of vocoder parameter data are interleaved throughout the rest of the packet.

Error correcling bits are computed from the most peree~Jt-lally significant bits of vocoder parameter data and are also interleaved throughout the packet.

With a high 30 probability, the single error correcl~lg code now allows a distinction to be made for a received data packet between one of a short burst of errors and one of many error throughout the frame.

In this way, a data packet with a few errors can be used sllccessfully, with the most perceptually significant bits of vocoder parameter data being correct.

35 However a data packet with many errors can be identified and ignored.

~MEN~'ED SIIEET CA 02128708 1998-02-23 3a In accordance with the present invention, there is provlded in a vocoding system a method for formatting vocoded speech parameter data corresponding to a frame of speech samples into a data packet for transmission comprising the steps of:

receiving different sets of vocoded speech parameter data wherein certain portions of certain vocoded speech parameter data are of greater relatlve importance than other portions of sald vocoded speech parameter data;

providing said certain portions of one of said certain vocoded speech parameter data set at a beginnlng of a data packet;

providing said other portions of said one certain vocoded speech parameter data set and other vocoded speech parameter data sets following said certain portions of one of said certain speech parameter data set in said data packet; and interleaving said certain portions of other certain ones of vocoded speech parameter data sets withln said other portions of said one certain vocoded speech parameter data and said other vocoded speech parameter data sets within said data packet.

In accordance with another aspect of the invention~ there is provided in a vocoding system in which a variable rate linear prediction coding ~LPC) vocoder encodes frames of speech samples so as to produce corresponding sets of encoded speech parameter data based upon an analysis of speech samples in each speech sample frame and predetermined subframes 74769-19 CA 02128708 1998-02-23 3b thereof, a method for formattin~ a frame of one rate parameter data for transmlsslon so as to reduce the lmpact of transmission channel induced errors in a transmitted frame of parameter data as received and reconstructed into a corresponding frame of speech samples, said method comprisin~ - the steps of:

receiving a first set of Line Spectral Pair (LSP) frequency data;

receiving a first plurality of sets of pitch data;

receiving a first plurality of sets of codebook data;

computing a parity check code from certain ones of said LSP data, said pitch data and said codebook data;

assembling in a predetermined sequence at a beginning of a data packet a first portlon of each one of sald LSP data of said first set of LSP data;

assembling in a predetermlned sequence a second portlon of each one of said LSP data of said first set of LSP data, said sequence of second portlons of LSP data followlng said sequence of first portions of said LSP data in said data ~0 packet;

providing a sequence of pitch data and codebook data from said plurality of first sets of pitch and codebook data following sald sequence of second portions of LSP data in said data packet; and providing said parity check code within said data packet.

In accordance with another aspect of the invention, there is provided in a vocoding system in which a vocoder 74769-19 CA 02128708 1998-02-23 produces variable rate frames of parameter data and corresponding frame rate indications, a data packing system for assembling each frame of parameter data into a data packet comprising:

parity check bit computation means for receivlng a frame rate indlcation and predetermined portions of a frame of parameter data, said parity check bit computation means responsive to a highest frame rate indication for computing and providing an output of parity check bit data; and data packing means for receiving said frame rate indication, said frame of parameter data and said parity check bit data, said packing means responsive to said frame rate indication for organizing said frame of parameter data for output according to a predetermined format in a data packet, wherein at said highest rate indication said packing means arranging said data packet beginning with a sequence of a portion of each parameter data of one set of parameter data followed by a sequence of a remaining portion of each parameter data of said one set of parameter data, other sets of parameter data and said parity check bit data.

In accordance with another aspect of the invention, there is provided in a vocoding system in which received variable data rate frames of vocoded speech parameter data are decoded into corresponding frames of speech samples, a method for reordering said parameter data is formatted in a data packet within each received frame wherein parameter data of a highest rate frame contains a portion of each parameter data 74769-19 CA 02128708 1998-02-23 3d of one set of parameter data in a predetermined order at a beglnning of the data packet followed by another portion of each parameter data of the one set of parameter data in a predetermined orderl and with other parameter data sets following the one set of parameter data, and having parity data within sald data packet computed from parameter data within said data packet, sald method comprising the steps of:

receiving a highest rate frame of parameter data;

reassembling corresponding ones of said portions and said another portion of each parameter data of sald one set of parameter data;

computlng parity data from parameter data in said received highest rate frame of parameter data;

comparing said computed parity data with said parity data in said received hlghest rate frame of parameter data;

providing an output of said parameter data if said computed parity data is the same as said recelved parlty data.

In accordance with another aspect of the invention, there is provlded in a vocoding system ln whlch received variable rate frames of data contain vocoded speech parameter data, with the frame data formatted according to a predetermined format, and the parameter data is decoded into correspondlng frames of speech samples, a system for reorganizing parameter data wlthin each received frame of parameter data comprlslng:

lnput means for receiving and storing a frame of data, and for provlding an output of said data in a predetermined 74769-19 CA 02128708 1998-02-23 order accordlng to a control signal; and unpacklng means for, recelvlng a frame rate lndlcatlon for each recelved frame of data and responslve thereto for provldlng sald control signal.

74769-19 2 1 2 8 7 0 8 4 P~T~ 9 3 / 007 0 3 EP 199 BRIEF DESCRIPTION OF THE DRAWINGS The features, objects, and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein:

Figure 1 is a block diagram of an exemplary vocoding system;

Figures 2a - 2d are a series of charts illustrating the vocoder output parameter bit distribution for the various vocoder output data frame rates;

Figure 3 graphs a - e are a series of charts illustrating the arrangement of data packets as transferred between the vocoder and microprocessor;

Figure 4 is a block diagram illustrating the circuitry for assembling vocoder data into packets for transfer from the vocoder to the microprocessor, and for ~ ssenlhling packets received from the microprocessor at the vocoder into a form for vocoder use in reconstructing speech frame data; and Figure 5a - 5h are a series of charts illustrating the arrangement of data packets within the transmission packets for various transmission modes and vocoder frame rates.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the figures, Figure 1 illustrates in block diagram form an exemplary implementation of a vocoding system 10.

It should be reali7~ that Figure 1 illustrates but one physical implementation 30 such as in a mobile station.

For the implementation in the environment of a Mobile Telephone Switching Offfce (MTSO) and cell base station in a cellular system, the elements of Figure 1 may be physically separated as described below.

For digital communication of voice, sounds such as speech 35 and/or background noise are sampled and digitized by well known techniques.

For example, in Figure 1, sound is converted by microphone 12 to an analog signal which is then be convelLed to a digital signal by codec 14.

Codec 14 typically ~erfor".s an analog to ~MENDED SHEET 2 1 2 8 7 3 8 4/1 P~S9 3 / OEOP7~ digital conversion process using a standard 8 bit/~llaw format.

In the alternative, the analog signal may be ~MEND~D S~EFr ~ 93/15~02 CA 02128708 1997-08-22 P ~ /U~ - 00703 directly converted to digital form in a uniform pulse code modulation (PCM) format.

In an exemplary embodin~ent codec 14 uses an 8 kHz sampling and provides an output of 8 bit samples at the sampling rate so as to realize a 64 kbps data rate.

The 8 bit samples are output from codec 14 to vocoder 16 where a ~law/uniform code conversion process is pelfor-l-ed.

In vocoder 16, the samples are organized into frames of input data wherein each frame is comprised of a predetermined number of samples.

In a preferred implementation of vocoder 16 each frame is comprised of 160 samples or of 20 msec. of speech at the 8 kHz sampling rate.

It should be understood that other sampling rates and frame sizes may be used.

Each frame of speech samples is encoded by vocoder 16 with the resultant parameter data formatted into a corresponding data packet in accordance with the present invention as described herein.

Vocoder 16 is preferably configured as a variable rate vocoder which encodes each frame of speech samples at a rate dependent on speech activity and systeln operating conditions.

The vocoder data packets are then output to microprocessor 18 for trarcmi~sion formatting.

Microprocessor 18 provides an output of the transmission formatted data to a transceiver (not shown) for modulation and transmission.

On the receive end the transmission formatted data packets are received and demodulated by the transceiver and then provided to microprocessor 18.

In miaoprocessor 18 the transmission formatting is removed and the extracted data packet for each speech frame is output to vocoder 16.

Vocoder 16 reconstructs from each data packet the samples of a co~esyonding speech frame.

These reconstructed speech frame samples are output to codec 14 where conventionally decoded and converted to analog form.

The analog speech samples are then output to speaker 20 where converted to an acoustical signal.

A yrefelled implementation of vocoder 16 ~ltili7es a form of the Code Excited Linear Predictive (CELP) coding techniques so as to provide a variable rate in coded speech data. A Linear Predictive Coder (LPC) analysis is performed upon a constant number of samples, and the pitch and codebook searches are performed on varying numbers of samples depending upon the transmission rate. A variable rate vocoder of this type is described in further detail in copending U.S.

Patent ,_ CA 02128708 1997-08-22 r, ~ WO 9~15502 PCI~/US93/00703 No. 5,414,796 issued May 9, 1995, and assigned to the Assignee of the present invention.

Vocoder 16 may be implemented in an application specific integrated circuit (ASIC) or in a dig~tal signal processor.

In the variable rate vocoder just mentioned, the speech analysis 5 &ames are 20 msec. in length, implying that the extracted parameters are output in a burst 50 times per second.

Furthermore the rate of data output is varied from roughly 8 kbps to 4 kbps to 2 kbps, and to 1 kbps.

At full rate, also referred to as rate 1, data transmission between the vocoder and the microprocessor is at an 8.55 kbps rate.

For the full rate 10 data the parameters are encoded for each &ame and represented by 160 bits.

The full rate data frame also includes a parity check of 11 bits thus resulting in a full rate &ame being comprised of a total of 171 bits.

In the full rate data &ame, the transmission rate between the vocoder and the microprocessor absent the parity check bits would be 8 kbps.

At half rate, also referred to as rate 1/2, data transmission between the vocoder and the microprocessor is at a 4 kbps rate with the parameters encoded for each &ame using 80 bits.

At quarter rate, also ref~led to as rate 1/4, data trarumission between the vocoder and the microprocessor is at a 2 kbps rate with the parameters encoded for each frame using 40 bits.

At eighth rate, also referled to as rate 1/8, data transrnission between the vocoder and the microprocessor is slightly less than a 1 kbps rate with the parameters encoded for each &ame using 16 bits.

In the communication system in which vocoder 16 is implemented it may also be desirable to send signaling or other non-vocoder data.

In the case where all signaling or other non-vocoder data is to be transmitted rather than vocoder data, which is referred to as a blank frame, the vocoder data for the &ame need not be transferred to the microprocessor for transmission.

Depending upon the data transmission rate, searches are ~erfo~led to compute the pitch filter and codebook excitation parameters multiple tirnes on different subframes of each speech frame.

At all rates, there is only one LPC computation per speech &ame.

With only one rate selected for each &ame, the pitch and codebook searches are done in various size sub&ames coLres~onding to the selected rate as described below.

At full rate there are four pitch subframes and two codebook subframes for each pitch subframe.

At full rate there are four pitch ,,. ~ , , wO 93/15502 ~ ~ 2 ~ 7 i ~ PCr/US93/00703 updates, one for each of the four pitch subframes, each 40 samples long (5 msec.).

Furthermore at full rate there are eight codebook updates, one for each of the eight codebook subframes, each 20 samples long (2.5 msec.).

At half rate, there are two pitch subframes and two codebook 5 subframes for each pitch subframe.

Pitch is updated twice, once for each of the two pitch subframes while the codebook is updated four times, once for each of the four codebook subframes.

At quarter rate, there is one pitch subframe and two codebook subframes for the single pitch subframe.

Pitch is updated once for the pitch subframe while the codebook twice, once for 10 each of the two codebook subframes.

At eighth rate, pitch is not determined and the codebook is updated only once in the speech frame.

Although the LPC coeffi~ierlts are computed only once per frame, they are linearly inlel~olated, in a Line Spectral Pair (LSP) representation, up to six times using the resultant LSP frequencies from the previous 15 frame to approximate the results of LPC analysis with a ~mming window cenlered on each subframe.

The exception is that at full rate, the LPC coefficients are not il~tel~olated for the codebook subframes.

In ~ ition to performing the pitch and codebook searches less often at lower rates, less bits are also allocated for the tr~rlcmiccion of the LPC 20 coefficients.

The number of bits allocated at the various rates is shown in Figures 2a - 2d.

Each one of Figures 2a - 2d represents the number of vocoder encoded data bits allocated to each 160 sample frame of speech.

In Figures 2a - 2d, the number in the respective LPC block is the num~er of bits used at the corresponding rate to encode the short term LPC 25 coefficients.

In the ~referred embodiment the number of bits used to encode the LPC coefficients at full, half, quarter and eighth rates are respectively 40, 20,10 and 10.

In order to implement variable rate coding, the LPC coefficients are first transformed into Line Spectrum Pairs (LSP) and the resulting LSP 30 frequencies are individually encoded using DPCM coders.

The LPC order is 10, such that there are 10 LSP frequencies and 10 independent DPCM coders.

The exemplary bit allocation for the DPCM coders at full, half, quarter and eighth rates is respectively 4, 2, 1 and 1.

In the vocoder the LSP frequencies are converted back to LPC filter coefficients for use in the pitch 35 and codebook searches.

21 2&708 P~S93/00703 IP~S 15 SEP 199~' With respect to the pitch search, at full rate as illustrated in Figure 2a, the pitch update is computed four times, once for each quarter of the speech frame.

For each pitch update at the full rate, 10 bits are used to encode the new pitch parameters.

Pitch updates are 5 done a varying numbers of times for the other rates as shown in Figures 2b - 2d.

As the rate decreases the number of pitch updates also decreases.

Figures 2b illustrates the pitch updates for half rate which are computed twice, once for each half of the speech frame.

Similarly Figure 2c illustrates the pitch updates for quarter rate which is 10 computed once every full speech frame.

As was for full rate, 10 bits are used to encode the new pitch parameters for each half and quarter rate pitch update.

However for eighth rate, as illustrated in Figure 2d, no pitch update is computed since this rate is used to encode frames when liKle or no speech is present and pitch redundancies do not exist.

For each 10 bit pitch update, 7 bits represent the pitch lag and 3 bits represent the pitch gain.

The pitch lag is limited to be between 17 and 143.

The pitch gain is linearly quantized to between 0 and 2 for representation by the 3 bit value.

With respect to the codebook search, at full rate as illustrated in 20 Figure 2a, the codebook update is computed eight times, once for each eighth of the speech frame.

For each codebook update at the full rate, 10 bits are used to encode the new codebook parameters.

Codebook updates are done a varying number of times in the other rates as shown in Figures 2b - 2d.

However, as the rate decreases the number of 25 codebook updates also decreases.

Figure 2b illustrates the codebook updates for half rate which is computed four times, once for each quartér of the speech frame.

Figure 2c illuskales the codebook updates for quarter rate which is computed twice, once for each half of the speech frame.

As was for full rate, 10 bits are used to encode the new 30 codebook parameters for each half and quarter rate pitch update.

Finally, Figure 2d illustrates the codebook updates for eighth rate which is computed once every full speech frame.

It should be noted that at eighth rate 6 bits are tra~cmitte~l, 2 bits representali~e of the codebook gain while the other 4 bits are random bits.

Further ~ csjon on the 35 bit allocations for the codebook updates are ~l~rihed in further detail below.

~MENDED SHEET WO g3/15502 2 1 2 ~' 7 ~ ~ Pcr/US93/oo703 The bits allocated for the codebook updates represent the data bits needed to vector quantize the pitch prediction residual.

For full, half and quarter rates, each codebook update is comprised of 7 bits of codebook index plus 3 bits of codebook gain for a total of 10 bits.

The codebook gain 5 is encoded using a differential pulse code modulation (DPCM) coder operating in the log ~om~in.

Although a similar bit arrangement can be used for eighth rate, an alternate scheme is ~referfed.

At eighth rate codebook gain is represented by 2 bits while 4 randomly generated bits are used with the received data as a seed to a pseudorandom number 10 generator which replaces the codebook.

It should be understood that in the alternative codebook data may be output rather than using the pseudorandom number generator approach.

Table I as follows is a chart which illustrates the various parameters and bit allocations thererore generated by the vocoder for each speech 15 frame, and also used by the vocoder in reco~ cting speech samples for a speech frame.

TABLE I Code Rate Code Rate 1 1/2 1/4 1/8 1 1/2 1/4 1/8 LSP1 4 2 1 1 CBINDEX1 7 7 7 LSP2 4 2 1 1 CBINDEX2 7 7 7 LSP3 4 2 1 1 CBINDEX3 7 7 LSP4 4 2 1 1 CBINDEX4 7 7 LSP5 4 2 1 1 CBINDEX5 7 LSP6 4 2 1 1 CBINDEX6 7 LSP7 4 2 1 1 CBINDEX7 7 - - LSP8 4 2 1 1 CBINDEX8 7 LSP9 4 2 1 1 CBGAIN1 3 3 3 2 LSP10 4 2 1 1 CBGAIN2 3 3 3 PLAG1 7 7 7 - CBGAIN3 3 3 PLAG2 7 7 - - CBGAIN4 3 3 PLAG3 7 - - - CBGAIN5 3 PLAG4 7 - - - CBGAIN6 3 PGAIN1 3 3 3 - CBGAIN7 3 PGAIN2 3 3 - - CBGAIN8 3 PGAIN3 3 - - - C~ L) - 4 PGAIN4 3 - - - PCB 11 2 ~ 2 8 7 Q ~ lo PCTlllS 9 3 / 007 03 IPE~WS 15 SEP ~994 Table II describes each parameter as referenced in Table I, and also in Tables m - VI:

TABLE II LSPi Line Spectral Pair frequency i PLAGi Pitch Lag for the ith pitch subframe PGAINi Pitch Gain for the ith pitch subframes CBINDEXi Codebook Index for the ith codebook subframe CBGAINi Codebook Gain for the ith codebook subframe CBSEED Random seed for an eighth rate data packet PCB Parity Check Bits used to detect and correct errors in a full rate data packet As ~ sed later herein, and in particular reference to Tables m - VI, the least significant bit (LSB) of a particular pararneter is referred to as PARAMETER(0) with the more significant bits respectively PARAMETER(1), PARAMETER(2), etc.

For example in a full rate 10 frame where LSPl = 1011 in binary form, the most significant bit LSPl(3) = 1, the next most significant bit LSP1(2) = 0, the next to least significant bit LSP1(1) = 1, and the least significant bit LSP1(0) = 1.

Vocoder 16 organizes the computed parameter bits for each 15 speech frame into data packets for output to micr~rocessor 18.

In the mobile station implementation all elements of vocoding sy~tem 10 are located typically within the unit.

However in a MTSO/cell base station implementation, microprocessor 18 may be located at the MTSO with vocoder 16 or located at the cell base station with the apt>ropliate 20 transmission interface.

Mic~opr~e~or 18 may receive a vocoder data packet in response to a data packet request provided from mi~lop~ocP~sor 18 to vocoder 16, or on the initiative of vocoder 16.

It should be understood that many dir~erent schemes well known in the art may be used in affecting a 25 l~ansfer of the data packet from microprocessor 18 to vocoder 16.

Data is packed at vocoder 16 for transfer to microprocPssor 18 in a unique arrangement which provides advantages over conventional data formats.

In an exemplary implementation, vocoder 16 communicates 30 with microprocessor 18 via an 8 bit parallel port, with the vocoder operating its parallel port in a passive mode.

Under an exemplary communication protocol between microprocessor 18 and vocoder 16, data transfer is always AMENDED ~E~T WO 93/15502 2 1 t~ O ~ PCI/US93/00703 initiated by microprocessor 18.

In this communication scheme, data packets sent to vocoder 16 by microprocessor 18 are referred to as commAnd packets while data packets sent from vocoder 16 to microprocessor 18 are rerelred to as response packets. (~ommAnds are sent 5 in the commAnd packets from microprocessor 18 and are acknowledged by vocoder 16 in two levels.

First, vocoder 16 indicates whether the packet from microprocessor 18 was received in good shape.

If so, it indicates that it understands the rommAnd and is c~lyil~g out the co~nmAnded function by echoing the commands back to micr~rocessor 18.

The data packets are transferred between microprocessor 18 and vocoder 16 typically in 22 byte blocks with each byte in a block comprised of 8 data bits.

The transfer of a data packet in a block from vocoder 16 to microprocessor 18 for trar~cmission~ and from microprocessor 18 to vocoder 16 for decoding of received traI cmicsion data is the same.

15 Figures 3a - 3e illustrate the composition of each vocoded speech frame data packet for each of full, half, quarter, eighth rates, and for a blank frame.

In Figures 3a - 3e, the block of data is represente-l in graphical form with byte number 1 being ~ sfe.led first with bit numbers 7 and 0 in each byte respectively being the first and last bits trans~.led for the respective 20 byte.

Since in the exemplary embodiment a constant transfer block is used, while the number of actual data packet bits vary depending on the rate for the data packet, several bits of a byte up to entire bytes are comprised of unneeded bits.

Figures 3a - 3e illustrate this fact by having byte bit positions in the block shaded for bits used and unshaded for bits unused or 25 ignored.

Figure 3e applies to the case where in certain trar cmissions, the microprocessor provides non-vocoder data, such as signaling data or other user data, for the frame.

On the receiving end a blank frame is transferred to the vocoder.

In this blank frame in which no vocoder data is present, should the data be transferred from the microprocessor to the vocoder it is 30 ignored.

Figure 4 illustrates in exemplary block diagram form the associated circuitry for organizing the parameter data cG..e~onding to each speech frame into data packets for tra~cmission to the micro~rocessor.

In Figure 4, vocoder 16 is illustrated as having a vocoder engine 30 which -35 computes the parameter data as described in the above mentioned copending application.

Vocoder engine 30 also computes from the wo 93/15502 Pcr/uss3/oo7o3 ~12 3 r~ 12 received parameter data the colres~onding frame of speech samples.

Vocoder 16 further comprises output frame buffer 32, packing logic 34, output packet buffer 36, parity check bit logic 38 and microprocessor interface logic 40.

Vocoder engine 30 computes the parameters for each speech frame and provides an output frame of the colles~nding parameter data bits to output frame buffer 32 where temporarily stored.

The parameter data may also be provided directly to parity check bit logic 38 for computation of the parity check bits for full rate data.

Vocoder engine 30 also for each speech frame provides an output indicative of the rate selected for the vocoded speech frame.

The rate data is typically provided to packing logic 34, parity check bit logic 38 and mi~oprocessor 18 via microprocessor interface logic 40.

In the alternative, the frame parameter data may be provided from buffer 32 to parity check bit logic 38 for each speech frame or only in les~nse to rate data indicative of a full rate frame.

In this configuration, the rate in~iic~tion may also be provided to buffer 32 which is responsive to a full ràte i~lic~tion for providing the parameter dah to parity check bit logic 38.

Parity check bit logic 38 is responsive to a full rate indication for computing 11 parity check bits based upon the 18 most perceptually significant bits of the full rate data.

The bits which are designated as of the group of perce~lually significant bits have been determined to most adversely affect speech quality in the decoded speech should an error occur in one of these bits.

The parity check bits are added to the full rate data packet to provide error correction to these 18 most ~erce~ ally significant bits.

In an exemplary and ~refer,ed embo-lim~nt, the error protection generated by parity check bit logic 38 is based upon a cyclic code to generate 10 parity bits to form a (28, 18) code, where the cyclic code is a shortened BCH code.

The terminology (n, k) implies ~at the code word is n bits long and there are k information bits. A single parity check bit is computed using the 28 bits of this code so as to form a final (29,18) code.

The 18 most perce~ ally significant bits are ~csemhled into an input polynomial in the GF(2), a Galois Field of two elements, according to equation (1) as follows:

wo 93/15502 PCI/US93/00703 13 a(x)= LSPl[3]xl7 + LSP2[3]xl6 + LSP3[3]xl5 + LSP4[3]xl4 + LSPs[3]x13 + LSP6[3]xl2 + LSP7[3]xll + LSPg[3]xl0 + LSPg[3]x9 + LSPlo[3]x8 + CBGAINl[l]x7 + CBGAIN2[1]x6 + CBGAIN3[1]x5 + CBGAIN4[1]x4 + CBGAlNs[1]x3 + CBGAIN6[1]x2 + CBGA~7[1]xl + CBGAINg[1]xO. (1) where LSPi[3] is the most significant bit (MSB) of the LSP code i, CBGAINj[1] is the second-most MSB of CBGAIN code i, and xi represents a bit position in the polyno~ l for the parameter bit.

In effect, a(x) is made up of the MSBs of all ten LSP codes, and the second-most MSB of the 10 CBGAIN codes.

The first 10 parity dhedc bits are generated using the cydic code with a generator polynomial of:

gpc(X)=xl0+x9+x8+x6+x5+x3+l (2) The term r(x) shall be defined as the remainder of the binary division of the input polynomial and the generator polynomial a(x)xl~ /gpc(x) = q(x) + r(X)/gpc(X)- (3) where a(x)xl~ is 10 bit position shift of a(x) with q(x) being the quotient of the division, and r(x) being the remainder of the division.

The quotient q(x) is not used and the bits of r(x) shall be assigned according to equation 4 as follows:

r(x) = PCB[10] x9 + PCB[9] x8 + PCB[8] x7 + PCBpl x6 + PCB[6] x5 + PCB[5] x4 + PCB[4] x3 + PCB[3] x2 + PCB[y x1 + PCB[1] x~ . (4) It should be noted that PCB[1] through PCB[10] are inverted before 30 transmission and before PCB[0], the 11th protection bit, is determined.

PCB[0] shall be a parity bit on the 18 ~rote-ted bits in a(x) and the ten paritycheck bits in r(x). PCB[0] shall be a logical "0" if the exclusive~R of all 28 bits results in "0"; PCB[Q]) shall be a logical "1" if the exclusive~R of all 28bits results in "1".

That is, PCB[0] = LSP1[3] ~ LSP2[3] ~13 LSP3[3] ~ LSP4[3] ~ LSP5[3] ~ LSP6[3] ~33 LSP7[3] ~3 LSP8[3] ~3 LSP9[3] ~3 LSP10[3] ~CBGAIN1[1] ~3 CBGAIN2[1] ~ CBGAIN3[1] ~3 CBGAIN4[1] ~ CBGAIN5[1] ~3 CBGAIN6[1] CBGAIN7[1] ~3 CBGAIN8[1] ~ PCB[10] ~ PCB[9] ~ PCB[8] ~ PCB[7] PCB[6] ~ PCB[5] ~33 PCB[4] ~E3 PCB[3] ~13 PCB[2] ~3 PCB[1] (5) 2128708 P~ 93~00703 14 IPEA/US 15 S~P 199 where ~ denotes the exclusive~R of the operands.

Logic 38 may be constructed using conventional processing/logic elements.

Logic 38 performs the multiplications and divisions as just ordinary multiplies and divides of one polynomial with another, 5 except that the coefficients are restricted to be binary and the arithmetic is performed modulo 2 with no carries or borrows.

Logic 38 provides an output of the parity check bits to buffer 32 for temporary storage.

As mentioned previously the parameter bits as set forth in Table I are provided to buffer 32 from vocoder engine 30, 10 along with the parity check bits for a full rate frame.

These frame bits are then packed for tra~mission.

Packing logic 34 receives the rate indication for each frame and in response thereto addresses buffer 32 to output parameter bits, and parity check bits if applicable, in a specified order.

The bits output from 15 buffer 32 are provided to packet buffer 36 for eventual transfer to microprocessor 18 as discussed with refere~ce to Figure 3.

It should be understood that in the alternative, bits may be output from buffer 32 directly to microprocessor 18 in an organized manner as discussed herein.

It should also be understood that buffers 32 and 36 may 20 configured as a single memory.

In any implementation the bits are organized for each rate as set forth in Tables m - VI.

In general, vocoder 16 provides an output of the parameter data to microprocessor 18 in an order which co~responds to the analysis of the speech frame as ~ se~1 with referel~e to Figures 2a - 2d.

The LSP 25 data which is based upon the entire frame of speech samples are provided near the l,egi~ ng of the packet.

The pitch data from the first pitch subframe of speech samples in the frame are provided next.

The pitch data is then followed by the codebook dah from the codebook subframe(s) of speech samples which correspond to the speech samples 30 of the first pitch subframe of speech samples.

If more than one codebook subframes of speech samples correspond to the pitch subframe of speech samples, then the codebook data for the first codebook subframe is provided and followed by the codebook data for the next codebook subframe.

After the codebook data for the codebook 35 subframes which co~respond to the pitch subframe is output, the pitch data for the next pitch subframe of speech samples is provided, if present for the encoding rate.

The codebook data ~MEN~ED SHEET 2 1 ~ ~3 7 0 8 15 P~1~113 9 3 / aO7 03 IP~ S 15 SEP 1994 for this next pitch subframe are then output as discussed previously.

For the speech sample frame, should there be more pitch subframes and corresponding codebook subframes of speech samples for which pitch and codebook data is generated, the pitch data is output first 5 followed by the corresponding codebook data.

This output process is repeated for any remaining pitch and codebook data for the speech sample frame.

In general for the pitch subframe the pitch gain values are placed before the pitch lag values in the data packet.

Similarly for the codebook subframes the codebook index values are place before the 10 codebook gain values in the data packet.

Specifics on the deviatiorls from this general exemplary implementation of ordering of the parameter data are provided in Tables III - VI.

Furthermore it should be understood that various other ordering schemes-may be readily implemented, but retain the novel aspects in ordering of the parameter 15 data.

Referring to Table III, the 171 bits of full rate frame data are packed into a primary traffic packet.

Bit 170 is the first primary traffic bit in the primary traffic packet with bit 0 being the last.

As can be seen in Table m, the most significant bit and second-most significant bits of 20 the ten 4-bit LSP codes, are placed at the beginning of the packet These first 20 bits of the data packet are bits that are among the group of bits that are the most perceptually significant.

Following these first 20 most perceptually significant bits in the data packet are the lesser significant bits of the LSP codes.

Following the lesser significant bits of the LSP 25 codes in the data packet are the remaining parameter codes, with the exception of the most significant bit of the eight codebook gain codes and the parity check bits.

The most significant bit of the eight codebook gain codes and the parity check bits are also considered as bits of the group of most percepl~lally significant bits.

Interleaved within the 30 lesser significant bits of the LSP codes and the following parameter codes in the data packet, every eighth bit, are these remaining most percepl,lally significant bits.

The bit interleaving in the packet is done because the errors are bursts of an average length of 8 bits.

In interleaving important bits 35 throughout the packet on average, a single burst will hit only one of the interleaved bits .

Since parity check bits are used for single error correction in full rate likely packet, the interleaving implies that correction can be made to errors in the imporlant bits in a length 8 burst.

M,~ENDED SI~EET wo 93/15502 Pcr/US93/00703 2~.J~7~ 16 As mentioned previously, in the ~referred ordering scheme data from each pitch subframe and collesl,onding codebook subframe, as set forth in Figure 2a, are provided.

The data from the first pitch subframe is followed respectively by the data from the corles~onding first and second 5 codebook subframes.

Simil~r is the ordering for the following pitch subframe data and col~es~onding codebook subframe data through the rest of the coded speech frame.

TABLE m Bit Code Bit Code Bit Code Bit Code 170 LSPl 2, 146 LSP3,1 122 PLAGl 4 98 CBGAIN2,2 169 LSPl 3 145 LSP3,0 121 PLAGl 3 97 CBGAIN2,0 168 LSP2 2 144 LSP4 1 120 PLAGl 2, 96 PGAIN2[2 167 LSP2 3 143 CBGA~l[l] 119 CBGAI~4[1] 95 CBGAIN7 1] 166 LSP3 2 142 LSP4-,0' 118 PLAGl,l 94 PGA~2-1 165 LSP3 3 141 LSP5,1 117 PLAGl 0, 93 PGAIN2 0, 164 LSP4 2 140 LSP5 0 116 CBINDEXl'6- 92 PLAG2,6 163 LSP4-3 139 LSP6,1 115 CB~DEXl 5 91 PLAG2 5 162 LSP5 2 138 LSP6 0 114 CBINDEXl 4 90 PLAG24 161 LSP53 137 LSP7 1 113 CBINDEX1~3 89 PLAG2 3 160 LSP6-,2 136 LSP70 112 CBINDEXl 2 88 PLAG2 2, 159 LSP63 135 CBGAN2[1] 111 CBGAIN5['] 87 CBGAI~ [1] 158 LSP72 134 LSP8-,1 110 CBINDEXl-l- 86 PLAG2-1157 LSP7 3 133 L~P8 0 109 CBINDEXl 0, 85 PLAG2 0 156 LSP8 2 132 LSP9,1 108 CBGAINl'2' 84 CBIND~X3-6' 155 LSP8 3 131 LSP9 0 107 CBGAINl,0, 83 CBINDEX3,5 154 LSP92 130 LSP10- - 106 CBINDEX,-6 82 CBINDEX3 4, 153 15P93 129 LSP100 105 CB~DEX2 5 81 CBINDEX3 3 152 15Pl~-2- 128 PGAI~' [2' 104 CBINDEX2 4 80 CBINDEX3 2 151 LSP103, 127 CBGAIN3,11 103 CBGAIN6[ ] 79 PCB[10] 150 LSPl :' 126 PGAINl l 102 CBINDEX2-3, 78 CBINDEX3 1149 LSPl 0 125 PGAINl,0, 101 CBINDEX2,2 77 CBINDEX3 0, 148 LSP2 1 124 PLAG1~6, 100 CBINDEX2,1 76 CBGAIN3-,' 147 LSP2,0, 123 PLAG1,5, 99 CBINDEX2,0, 75 CBGAIN3,0, W O 93/15502 ~ l s.r~ 3 8 PC~r/US93/00703 T A BLE m (con~nued) Bit Code Bit Code Bit Code Bit Code 74 C BLNn~EX4 6' 55 PC B~ 36 C Br~n~EX6'1- 17 CBr~n~EX7 3 73 C Br~n~EX4 5 54 PLA G3-1- 35 C Br~n)EX6,0 16 CBnNn)EX7,2, ~ 72 C BIN D EX4 4 53 PL A G3,0 34 C B G ArN6-,' 15 PCB[2] 71 PCB[9] 52 CBr~n~:~X5-6- 33 C B G AIN6.0 14 C Br~n)EX7-170 C BDNn~EX4'3- 51 C Bn~n)EX5 5 32 P G Ar~412, 13 CBnNn)EX7,0, 69 C Bl~n)EX4,2 50 CBr~n)EX5 4 31 PCB[4] 12 C BG~IN7-.' 68 C BL~n~EX4,1 49 C BrNn~EX5 3 30 P G Arr~4-1' 11 C BG ArN7 0 67 C BI~n~EX4 0 48 C Br~n~EX5 2 29 P G ArN4,0, 10 CBrNn)EX ~ 66 C B G AIN4',- 47 PCB[6] 28 PL A G4-,6 9 C BDNn)EX8 5 65 C B G ArN4 0 46 C Br~n)EX5-1- 27 PL A G4 5 8 C Bn!n~EX8 4, 64 P G~rM3[2 45 C BrNn~EX5,0, 26 PL A G4 4 7 PCB[l] 63 PC B[8] 44 C B G AI~5-. 25 PL A G4 3, 6 CBrNn~EX8-,362 P G~ 3-1- 43 C B G ArN5,0 24 PL A G4,2, 5 CBDNn~EX8 2 61 P G Ar~3 0 42 C Br~n~EX~-~- 23 PC B[3] 4 C Br~n~EX8 1 60 PLAG3-6 41 CBr~n~EX6,5, 22 PLAG4-1- 3 CBDNn)EX8,0, 59 PLAG3 5 40 CBrNDEO~6 4 21 PLAG4 0, 2 CBGAIN8,,, 58 PLAG3 4 39 PCB[5] 20 CBrND3Y7-,6 1 CBGAIN8,0, 57 PLAG3'3 38 CBrNDr;X~'3- 19 CBrNDr;,X75 0 PCB[0] 56 PLAG3,2 37 CBr~JDr;X6,2 18 CBrNDr;X7,4 The full rate primary traffic packet is then organized by 5 microprocessor 18 into a transmission packet which also includes a signaling bit, frame quality indicator bits and end of frame bits (encoder tail bits).

The frame quality indicator bits are in essence cyclic redundancy check (CRC) bits generated from the full rate primary traffic packet bits by a CRC and Tail Bit generator circuit (not shown) following 10 microprocessor 18.

Referring to Figure 5a, for full rate the tra~mi~sion packet is co~ rised of 192 bits in which the first bit is a signaling bit.

The signaling bit is followed by the 171 bits of the primary traffic packet which is then followed by the 12 CRC bits.

Pollowing the CRC bits in the transmission packet are the 8 tail bits, which are all zeros.

The 15 tra~cmission packet is encoded for trar ~mi~sion in a traI-smi~sion frame which spans a 20 ms. tirne period so as to realize a data rate of 9.6 kbps.

The 80 bits of half rate frame data are also packed into a prirnary traffic packet as illustrated in Table IV.

Bit 79 is the first primary traffic bit in the primary traffic packet with bit 0 again being the last.

As can be seen 20 in Table IV the bits of the ten 2-bit LSP codes, are placed at the beginning of the packet as a matter of convenience and consistency.

Following these WO 93/15502 PCr/US93/00703 ~12S ~ 18 first 20 bits are the bits of the remaining significant parameter codes as was for full rate data, with again some interleaving of the codebook gain bits.

TABLE IV Bit I Code Bit I Code Bit Code Bit Code 79 ~,1 59 PGAIN1 2 39 CBINDEX2,6 19 CBINDEX3,6 78 ~,0 58 PGAIN1,1 38 _B1NDEX2 5 18 CBINDEX3,5 77 ~2,1 57 PGAIN1 0 37 CB1NDEX2,4 17 CBINDEX3 4 76 ~2,0 56 PLAG1-6 36 _BINDEX23 16 CBINDEX3 3 75 ~3,1 55 PLAG1 5 35 _BINDEX2,2 15 CBINDEX3 2 74 ~3,0 54 PLAG1 4 34 CB~DEX2,1 14 CBINDEX3~1 73 ~1?4 1 53 PLAG1 3 33 -B1NDEX2,0 13 CBINDEX3 0 72 ~SP4,0 52 PLAG1 2 32 CBGAIN2:, 12 CBGAIN3-,71 ~P5,1 51 PLAG1,1 31 CBGAIN2,1 11 CBGArN3 1 70 LSP5,0 50 PT AG1 0 30 CBGAIN2,0, 10 CBGAIN3 0 69 ~6 1 49 _BIND~1-6' 29 PGAIN2 2 9 CBINDEX"-~ 68 'ISP6,0 48 _BINDEX1,5 28 PGAIN2,1 8 CBINDEX4 5 67 ~7,1 47 _BINDEX1 4 27 PGAIN2 0 7 CBINDEX4 4 66 ~7,0 46 -B~DEX1,3 26 PLAG2',6 6 CBINDEX4 3 65 ~8,1 45 -BINDEX1,2 25 PLAG2 5 5 CB~DEX4 2, 64 ~8,0 44 _BINDEX1,1 24 PLAG24 4 CB1NDEX4 1 63 ~5~9,1 43 _B~DEX1 0 23 ~LAG23 3 CBIN~EX4,0.

62 ~9,0, 42 _BGAIN1-,- 22 PLAG2 2 2 CBGArN4-.61 LSPl~' ~ 41 _BGAIN1,1 21 PLAG2,1 1 CBGAIN4 1 60 'IsPlo O 40 _BGAIN1,0, 20 PLAG2,0, 0 CBGA~N4.0, The half rate primary traffic packet is then organized by microprocessor 18 into a trarlcmi.ssion packet which also includes frame quality indicator bits and encoder tail bits.

The frame quality indicator bits 10 are again cyclic redundancy check (CRC) bits generated from the half rate primary traffic packet bits by the CRC circuit.

Referring to Figure 5f, for half rate the tra~smicsion packet is comprised of 96 bits which begir~c with - the 80 bits of the primary traffic packet.

The bits of the primary traffic packet are followed by the 8 CRC bits which are then followed by the 8 tail 15 bits.

The tra~cmi.csion packet is again encoded for transmission in a transmicsion frame which spans a 20 msec. time period to realize an effective data rate of 4.8 kbps.

It should be understood that half rate data may be transfelled in the tra~cmicsion packet along with other data such as signaling data, signaling 20 traffic, (Figure 5b) or data from sources other than the vocoder, secondary traffic, (Figure 5c) at the 9.6 kbps data rate.

It should further be understood WO 93/15502 PCr/US93/00703 ~ 2~7 ~8 19 that full rate vocoder data may be blanked, not generated, and other data inserted into the trar~cmicsion packet as illustrated in Figures 5d - 5e.

The 40 bits of quarter rate frame dah are packed into a primary traffic packet as illuslraled in Table V.

Bit 39 is the first primary traffic bit 5 in the primary traffic packet with bit 0 again being the last.

As can be seen in Table V, the single bit of the ten 1-bit LSP codes, are placed at the beginning of the packet.

Following these first 10 bits are the bits of the remaining parameter codes, with again some interleaving of the codebook 10 gain bits.

TABLE V Bit Code Bit Code BitCode Bit Code 39 LSPl,0 29 PGAINl 2 19CBINDEX1,6 9CBINDEX2,6 38 LSP2,0 28 PGAIN1,1, 18CB~DEX1 5 8CBINDEX2,5 37 LSP3,0 27 PGAIN1 0 17CBINDEX1,4 7CBINDEX2 4 36 LSP4,0 26 PLAG1-6 16CBINDEX1,3 6CBINDEX2 3 LSP5~0 25 PLAG1,5 15 ,CB~DEX1 2 5CBINDEX2 2 34 LSP6,0 24 PLAG1,4 14CBINDEX1,1 4CBINDEX2,1 33 LSP7,0 23 PLAG1 3 13CBlNDEXl 0 3CBINDEX2 0 32 LSP8,0 22 PLAGl 2 12CBGAINl-. 2 CBGA~2-231 LSP9,0 21 PLAGl,1 11CBGArN1,1 1CBGAIN2,1 LSPl~[~] 20 PLAG1,0, 10CBGAIN1 0 0CBGAIN2,0 The quarter rate primary traffic packet is then organized by 15 microprocessor 18 into a tr~ncmission packet which also includes only the 8 encoder tail bits.

Referring to Figure 5g, for quarter rate the tra~smicsion packet is thus comprised of 48 bits which begins with the 40 bits of the primary traffic packet and ends in the 8 tail bits.

The trar~cmicsion packet is again encoded for kan~-nicsion in a tr~ncmission frame which spanc a 20 20 ms. time period to realize an eC~-Lve data rate of 2.4 kbps.

The 16 bits of eighth rate frame data are packed into a primary traffic packet as illustrated in Table VI.

Bit 15 is the first primary traffic bit in the primary traffic packet with bit 0 again being the last.

As can be seen in Table VI, the single bit of the ten 1-bit LSP codes, are placed at the 25 beginning of the packet with an interleaving of the codebook seed therein.

Following these bits are the bits of the remaining parameter code.

2 ~ ~108 20 PF~93 /00703 TABLE VI . IPE.4US 15 SEP lX~ Bit Code Bit Code Bit Code Bit Code ~ L~[3] 11 CBSEED[2] 7 ~ ,L~[1] 3 ( ~:kL~[0] 14 LSP1,0' 10 LSP4,0' 6 LSP~0- 2 LSP10[0] 13 LSP2,0 9 LSP5,0 5 LSP8,0 1 CBGAIN1'1' 12 LSP3 0 8 LSP6 0, 4 LSP9.0 0 CBGA~1,0, The eighth rate primary traffic packet is then organized by microprocessor 18 into a transmission packet which also includes only the 8 encoder tail bits.

Referring to Figure 5h, for eighth rate the transmission packet is thus comprised of 24 bits which begins with the 16 bits of the primary traffic packet and ends in the 8 tail bits.

The transmission packet is again encoded for transmission in a tra~mission frame which spans a 20 ms. time period to realize an effective data rate of 1.2 kbps.

Referring again to Figure 3, the primary traffic packets are transferred from vocoder 16 in response to a data output cornm~nd from microprocessor 18.

In response to this command, which is processed by microprocessor interface logic 40, logic 40 provides a transfer command to buffer 36.

Buffer 36 in response to the transfer command outputs the formatted packet in bytes to microprocessor 18 as discussed with rererel~e to Figure 3.

In the vocoding system of Figure 1 received vocoded speech frames are also reconstructed into the speech frame samples.

At the receiver the communication of data between miclo,t)rocessor 18 and vocoder 16 is similar to that for tra~ siQn.

In this mode of operation vocoder 16 receives and unpacks data packets from mi~roprocessor 18 for ~leco~ing and spee~:h sample reconstruction.

The primary traffic packets are transferred from microprocessor 18 to vocoder 16 along with a dah input comm~nd from micfo~r~essor 18.

Mi~oprocessor 18 which also determines the rate of the data packets for vocoder decoding purposes and provides an indication of the determined rate to vocoder 16.

Micro~rocessor 18 also determines the quality of the received data.

If the received packet is corrupted to an extent that is unco~recldble using the error correction techniques (in~llfficient frame quality) an erasure indication is sent to vocoder 16 as a rate indication.

In this case although microprocessor 18 may send the data packet to vocoder 16, these values are not used in the decoding process.

Furthermore should microprocessor 18 ~ENDED 9HET 2128108 21 PCTIUS 9 ~ / 007 03 IPE.WS 15 SEP 1994 determine that the data packet is a full rate packet with a detected error in the received transmission packet data, based upon a check of the CRC, an indication that the packet is a full rate packet with probable bit error is provided to vocoder 16.

Since the CRC is computed from the 5 data packet bits, one or more errors occurring within the data packet bits will be detected.

In vocoder 16 the corrupted data packet bits, if correctable, are corrected and the corrected data packet used by vocoder 16.

Another possibility for the received tral-~...icsion packet is that it contains data other than vocoder data, such as signaling or secondary traffic data.

For example, in transmission the vocoder data shares the transmission frame with other digital data (Figures 5b - 5c) or is exclusively non-vocoder dah (Figures 5d - 5e).

In this case the mode data in the transmission packet in-lit Ates the packet type as containing vocoder data only or one which contains other data, such as a combination of vocoder and non-vocoder data, or non-vocoder data only. A burst format bit further indicates whether the packet is a combination of vocoder and non-vocoder data, or is non-vocoder data only.

When the transmission packet is received and detected as containing non-vocoder data only, a blank frame indication is provided from microprocessor 18 to vocoder 16.

Although data may be transferred from microprocessor 18 to vocoder 16 it is not used.

Instead vocoder 16 uses data stored intemally to update the state of the vocoder.

Referring to Figures 1 and 4, in all cases vocoder 16 is responsive to a data input commAnd from microp~ocessor 18, which is processe-l by mi~oproc?ssor in~e~ce logic 40 and provides a ~ansfer commAnd to buffer 36.

Buffer 36 in response to the transfer commAlld receives the fo~mAtte~i packet in bytes frorn mi~oprocessor 18 as ~ cse~l with refef~e to Figure 3.

Logic 40 also transfers rate indications between vocoder 16 and microprocessor 18.

The transferred data packet is input to packet buffer 42 where temporarily stored.

In coordination with the data packet trallsfer, the rate indication for the determ--led rate of the dah packet is provided to unpacking logic 44 via logic 40.

In general, unpacking logic 44 is responsive to the rate indication for controlling the output of packet data from buffer 42 to frame buffer 46.

The unpacked parameter dah is then stored in buffer 46 for providing to vocoder engine 30.

Vocoder engine 30 JW~NDED S~IEE~ wo 93/15502 Pcr/US93/00703 . .

~1~V~7~ 22 receives the rate indication from microprocessor 18 in addition to the co~re~onding unpacked parameter data for decoding at the indicated rate.

It should be understood that in an alternative configuration buffer 46 may be eliminated and the data be provided directly from buffer 42 to vocoder 5 engine 30 under the control of logic 44.

In the unpacking of full rate vocoder data packet, as for all rate vocoder data packets, logic 44 coordinates the output of data from buffer 42 for storage in buffer 46.

For parameter data in which the parameter bits were split apart in the packing process, the bit portions are recombined to 10 form a corresponding complete bit value.

For example, for a full rate vocoder data packet the most significant and second-most significant bits of each LSP code is combined with the cG~res~onding lesser significant bits of the LSP code.

Thus the ten LSP codes are reconstructed as 4-bit values as stored in buffer 46.

Furthermore, parameter data interleaved within the 15 packet is grouped with cGlres~onding parameter data.

For example, for a full rate vocoder data packet the parity check bits are grouped together as stored in buffer 46.

Parameter data may further be organized according to sample frame and subframe for input to the vocoder.

It should be reAli7e~1 that may other schemes may be readily used in and for the organiz~tion of 20 parameter data for input to the vocoder.

In the unpacking of a full rate data packet, buffer 42 provides an output of the parameter data to buffer 46 in accordance with signals from logic 44.

Parameters having their data bits separated in the packet are organized to form complete parameter bit values.

For example as 25 mentioned above, the most and second-most significant data bits for each LSP parameter are combined with the next-to-least and least significant bits for the LSP parameter to form a respective 4-bit value.

Parameter values may also be organized to provide a grouping of simil~r parameter data, or by analysis subframe, or any other organization scheme.

The 30 arranged and organized parameter values are stored within buffer 46 under the control of logic 44.

Once the parameter values are unpacked, parity check bits are computed as was discussed with rererence to logic 38, and compared with the received packet parity check bits.

Parity check bit check logic 48 35 receives the a~pio~riate bits from buffer 46 under the comm~nd of logic 44 so as to compute the parity check for the packet.

Logic 48 is enabled for wo 93/15502 ~ Pcr/uss3/oo7o3 23 computing and comparison purposes in res~onse to a full rate indication, and a full rate with probable error as discussed later.

Furthermore the received parity check bits are also output from buffer 46 to logic 48 for comparison with the computed parity check bits.

In an alternative 5 configuration the received parity check bits, or the parameter bits used to compute the comparison parity check bits, may be extracted directly from the data packet output of microprocessor 18 as input to buffer 42.

In yet another alternative configuration the received parity check bits or the parameter bits used to compute the comparison parity may be extracted 10 from the output of buffer 42.

For the full rate frame, should no errors be detected in the received parity check bits in comparison with the computed parity check bits a full rate parity check pass indication is provided from logic 48 to logic 44 and vocoder engine 30.

Logic 44 in response provides an output commAnd to 15 buffer 46 which responds by outputting the parameter data to vocoder engine 30 where used in reconstructing the speech frame samples.

However should an error be ~lPtecte~l in the parity check bits by logic 48, logic 48 generates an insllffi~iPnt frame quality indication that is also provided to logic 44 and vocoder engine 30.

In response to the insufficient 20 frame quality indication, logic 44 may provide an output command to buffer 46 which outputs the data to vocoder engine 30.

In this event vocoder engine 30 ignores the received dah in res~onse to the insllffi~i~nt frame quality indication also provided thereto from logic 48.

In an alternative implementation the data may not be output from buffer 46 to 25 vocoder engine 30.

Vocoder engine 30 operates to reconstruct a frame of speech samples from the previous state of the vocoder.

In the event that microprocessor 18 provides a full rate with probable error (also refelled to as full rate likely) indication to logic 40 thedata packet is also transferred to buffer 42. A full rate likely indication is 30 generated by microprocessor 18 when for a full rate tra~cmissiQn packet an error is detected in the CRC even though the trar~mission packet had frame quality metrics provided by the decoder which are indicative of a good packet.

The frame quality metrics are used in microprocessor 18 to determine the symbol error rate of the received frames. A low symbol 35 error rate indicates that the received data frames are likely to contain good data.

wo 93/15502 - PCr/US93/00703 2 1 2 ~ 8 24 Before the data packet in buffer 42 is unpacked by logic 44 for transfer to buffer 46, a check of the parity check bits are first made.

As was done for a full rate packet, logic 48 computes the parity check bits for the received data packet and compares these with the recehed parity check bits from the packet itself.

Should logic 48 detect a single error, the error is corrected using well known parity check bit correction techniques with the corrected bit provided to buffer 42 in place of the incorrect bit.

Logic 48 also provides a full rate likely parity check pass indication to logic 44 and vocoder engine 30.

Logic 44 in response controls the reorganization of the parameter bits and storage in buffer 46.

Logic 44 also provides an output comm~nd to buffer 46 which responds by outputting the parameter data to vocoder engine 30 where used in reconstructing the speech frame samples.

However should more than one error be detected in the parity check bits by logic 48, logic 48 generates an insufficient frame quality indication that is also provided to logic 44 and vocoder engine 30.

In response to the insllffici~nt frame quality indication, logic 44 does not unpack the data packet since the data is not used by vocoder engine 30.

The data in buffer 42 may be output to buffer 46 where ignored when transferred to vocoder engine 30.

Again vocoder engine 30 ignores the received data in res~onse to the insllffit i~nt &ame quality indication.

As before, vocoder engine 30 operates to reconstruct a frame of speech samples from the previous state of the vocoder.

For half, quarter and eighth rates, the rate indication from microprocessor 18 is provided through logic 40 to logic 44 and vocoder engine 30.

Microprocessor 18 also provides the data packet to buffer 42.

Logic 44 controls the unpacking of the 80, 40 and 16 bits, respectively for half, quarter and eighth rate, as transferred from buffer 42 to buffer 46.

However for eighth rate, should the packet conPin all logical ones ("1"), as detected by detection logic 50, an insllfficient frame quality indication is generated by logic 50 and provided to logic 44 and vocoder engine 30.

Logic 44 and vocoder engine 30 function as discussed just above with respect to the full rate likely condition with multiple errors detected in the parity check bits.

On occasion microprocessor 18 will generate the insufficient frame quality indication as a rate determination indication when the wo93/15502 .f. ~ Pcr/uss3/oo7o3 transmission packet CRC check fails and a high symbol error rate is determined from the decoder frame quality metrics.

The insufficient frame quality indication is provided through logic 40 to logic 44 and vocoder engine 30.

Logic 44 and vocoder engine 30 function as discussed 5 above with respect to the full rate likely condition with multiple errors detected in the parity check bits.

Purthermore on occasion the received transmission packet may contain data other than vocoder data.

The trarlcmicsion packet may be all other data, or have vocoder data and other data togther as discussed 10 above with reference to Figures 5b - 5e.

Microprocessor 18 recognizes this type of transmission data packet based upon signaling bits col~lained in the packet.

In the event that less than the entire trar cmicsion packet data portion contains the entire data as signaling or secondary traffic (Figures 5d - 5e) a blank indication is provided from microprocessor 18 15 through logic 40 to logic 44, vocoder engine 30, and memory 52.

Memory 52 is provided for storing the previous data output from buffer 42.

Logic 44 instructs mem-~ry 52 to provide data from memory 52 to buffer 46 in place of the output from buffer 42.

In particular, the pitch lag and pitch gain for the last pitch subframe of the previous frame of data 20 along with the LSP frequency data for the previous frame are provided from memory 52 to buffer 46.

This data is then provided from memory 52 to vocoder engine 30.

In the alternative, the particular data may be provided directly from memory 52 to vocoder engine 30.

In yet another alternative implementation all data in m~mory 52 may be provided to 25 buffer 46.

From the previous frame data, vocoder engine 30 generates a current frame of estimated speech samples.

It should be understood from the above that various - implementations may be devised to achieve the packing and unpacking of parameter data.

Many of the functions for the elements described above 30 can be implemented in various forms, such as in a processor, or distinct logic and memory elements, or a combination of both.

It should be understood that the additional protection described with reference to the highest rate encoded data may easily be provided to the lower rate data.

The previous description of the ~rerelred embodiments is provided 35 to enable any person skilled in the art to make or use the present invention.

The various modifications to these embodiments will be Wo 93/15502 PCI/US93/00703 ~ 1 ~ S 7 ~ ~ 26 readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the inventive faculty.

Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest 5 scope consistent with the principles and novel features disdosed herein.

WE CLAIM: