Multiple accumulator fractional n synthesis with series recombination

wn 93i»sz~ ~criu~~zi~ ~ ~7:~ 1 Multiple Accumulator Fractianal IV Synthesis with Series Recombination Field of the Invention This invention relates generally to frequency synthesizers and more particularly to a fractional N frequency synthesizer employing multiple accumulators in a latched configuration 1 0 with series recombination.

The latched configuration operates synchronously and enables the system to operate at higher frequencies than a simple ripple system, thereby, reducing the spurious signals.

1 5 Background of 'the Invention Phase-locked loop (PLL) frequency synthesis is a well known technique for generating one of many related signals from a voltage controlled oscillator (VCO).

In a single loop PLL, 2 0 an output signal from the VC0 is coupled to a programmable frequency divider.

The programmable frequency divider divides by a selected integer number, providing a frequency divided signal to a phase detector.

The phase detector compares the frequency divided signal to a reference signal from another fixed 2 5 frequency oscillator. any diffexence in phase between the frequency divided signal and the reference signal is output from the phase detector, coupled through a loop filter, and applied to the VCO.

The phase difference signal causes the output signal from the VC0 to change in frequency such that the phase error 3 0 between the frequency divided signal and the reference signal is minimized.

Since the programmable divider divides by integers only, the output frequency step size is constrained to be equal to WO 93/16523 PCT/US92/11173 2 ,:-....

the reference signal frequency.

With the single loop PLL, an engineering compromise must be struck between 'the competing requirements of loop lock time, step size, noise performance, and spurious signal generation.

Z.n order to overcome the limitations of the single loop PLL, programmable frequency dividers capable of dividing by nonintegere have been developed.

Output frequency step sizes which are fractions of the reference signal frequency are obtained whale maintaining a high reference frequency and wide loop 1 0 bandwidth. A discussion of fractional-N synthesis may be found in U.S.

Patent No. 4,816,774.

As described therein, two accumulators are employed to simulate the performance of fractional synthesis.

The simulation switches between different integer values of divisors without the attendant spurious signals 1 5 generated by such switching.

The two accumulator technique acts to reduce the unwanted spurious signals by cancellation and loop filter rejection.

The reference signal frequency for the fractional-N frequency synthesizer is, therefore, determined by the step size of 2 0 the VCO output frequency multiplied by the denominator of the programmable divider divisor. li'ractional-N synthesis allows the use of a reference frequency which is much higher than the actual channel spacing and allows designs to use wider bandwidths due to the reduction of low frequency spurious 2 5 outputs.

Wider bandwidths allow fast lock times and the possibility of wideband modulation applied to the reference input or the fractional division scheme.

2Tnfortunately, the system is not perfect and generates some spurious signals output at a frequency equal to the channel 3 0 spacing.

The desired signal output purity is better than the nonfractional system, but by itself may still be insufficient for some high quality systems.

WO 93/15523 PCTT/U~92/11173 3 In order to minimize 'the effects of this spurious output, multiple accunnulator fractional-N synthesis systems have been developed.

These systems spread out 'the spurious signals to frequencies at which filtering is inexpensive and simple.

By using systems with more than two accumulators this benefit can be dramatically increased.

Some of the present multiple accumulator systems require the accumulators to "ripple" the data.

Specifically, on every clock pulse the data must act on the entixe digital network.

This 1 0 results in a relatively low upper frequency limit of operation for a multiple accumulator system due to propagation delays in the digital circuitry used to build the system. finally, some current multiple accumulator systems still maintain a residual noise term which may cause spurious noise signals.

These spurious 1 5 noise signals must be diminished fox proper operation of many systems.

WO 93/I6523 P~T/US92/11173 4 Summary of the Invention The present invention encompasses a variable frequency synthesizer including at least -two latched accatmulator networks which axe recombined in series.

The latched accumulator networks accept a digital number which is used to ~orm a variable divisor.

The frequency of a variable frequency oscillator is 1 0 controlled by dividing the output signal frequency with the variable divisor in a divider network, forming an intermediate signal.

The intermediate signal is compaxed with a reference signal, generating a first error signal indicative of a phase difference between the two signals.

Thie first error signal is 1 5 input the variable frequency oscillator as a control signal to the variable frequency oscillator.

The first accumulator network generates a latched output signal and a first carry output signal representing an integral of the digital number .

2 0 The second accumulator network generates a second latched output signal and a second carry output signal representing an integral of the first latched output signal.

The tizird latched accumulator network generates a third latched output signal and a third carry output signal which ~ 5 represents an integral of the second latched output signal.

The three carry output signals are then combined to form the variable divisor signal.

The third carry output signal is differentiated and combined with the second carry output signal forming a fifth output signal.

This fifth output signal is 3 0 then differentiated and combined with the first carry output signal forming the variable divisor signal.

This variable divisor signal is input into the divider network.

WO 93/1523 PCI~/U~92/71973 ~~~~~r~~ Brief Description of the Drawings FIG. 1 is a block diagram of a variable frequency 5 synthesizer.

FIG. Z is a general block diagram of an accumulator network in ~ (with series recombination) fractional N synthesize: ~ ; z accordance with the present invention.

FIG. 3 :~ .an illustration of a latched accumulator network 1 0 in accordance with the present invention.

FIG. 4 is an illustration of a double delayed latched accumulator network in accordance with the present invention.

FIG. ~ is an illustration of a d~-uble delayed latched 1 5 netwoxk in accordance with the present invention.

FIG. 6 is an illustration of a single delayed latched accumulator network in accordance with the present invention.

FIG. 7 is an illustra~ ~n of a double delayed latched 2 0 accumulator -network w h. residual error correction in accordance with the pr ent invention.

FIG. ~. is an illustration of a single delayed latched accumulator network shown in an alternative form in accordance with the present invention.

2 5 FIG. 9 is a block diagram of a radio transceiver which may employ the present invention.

FIG. 10 is an illustration of a typical latched accumulator in accordance with the present invention.

FIG. 1~ is a graph of curves illrxstrating the frequency 3 0 versus attenuation of each term of the system transfer function in accordance with the present invention.

WO 93/16523 PCT/US92/11173 Detailed Description of a Preferred Embodiment Generally, the preferred embodiment encompasses the use of a synthesizer in a radio transceiver.

The synthesizer is of a fractional-N type.

The synthesizer utilizes multiple latched accumulators, within an accumulator network, to perform multiple integrals of an input signal. 'rhe outputs of the accumulators are combined in series to form a data output signal which used as a variable divisor within the synthesizer.

1 0 A basic block diagram of a radiotelephone 901 including a radio tr ansceiver which may employ the present invention is shown in FIG. 9.

Such a radiotelephone 901, preferably, is a digital radiotelephone useful in a digital radiotelephone system.

The output of the synthesizer 903 is used by the 1 5 receiver 905 and the transmitter 90? to produce a local oscillator and a transmit signal, respectively.

Control over functions of the transceiver 900, such as channel of operation frequency is provided by control logic 909 and is input to the first accumulator of a fractional N synthesizer contained 2 0 within a synthesizer 905.

FIG. 1 is a generic block diagram of a fractional N variable frequency synthesizer.

The variable oscillator, or VCO 113 provides a desired output frequency signal 119 and feeds the input to a variable digital frequency divider circuit 111.

The 2 5 variable frequency divider circuit output signal 125 is input into a phase comparator 109. A second input of the phase comparator 109 is the reference oscillator signal 115.

The phase comparator output signal 121 is fed into the control input of the VCO 113, such that the VCO 113 will adjust its 3 0 output frequency signal 119 divided by the digital division ratio, N, of the frequency divider circuit 111, to equal the frequency of the reference oscillator 107.

wo ~3i ~ bsz~ Pcri us~zn a ~ ~~ 7 In the preferred embodiment, the division ratio, I~, of the frequency divider circuit 111 is varied with a periodic sequence such that the output frequency signal 119 of the VCO 113 may be adjusted in frequency steps equal to a fraction of the frequency of the reference oscillator 10?.

This periodic sequence is generated by a multiple acc~unulator network 101 and controlled by the data input signal 103.

In the preferred embodiment, a latched accumulator configuration as illustrated an FIG. 10 is employed in all of the 1 0 accumulator networks.

Other equally sufficient accumulator configurations may be implemented by one of average skill in the art.

Here, the data out signal 1001 of each accumulator is the latched output from the conventional latch circuit 1003. A cascade of such accumulators will have a single adder delay 1 5 upon each clock cycle of the clock signal 1005.

This arrangement results in each accumulator carry output sequence from adder 100? being delayed by one clock cycle from the output sequence of the ne~rt lower order accumulator.

It may be noted that other equally suffioient embodiments may 2 0 employ latched accumulators which latch the carry output signal 1011 and the data output signal 1001.

FIG. 2 is an illustration of the type of accumulator network employed in the present system.

This network utilizes multiple latched accumulators and series recombination 2 5 allowing for a simple design and DC frequency offsets to be directly added to the data output (DO) 229.

The frequency offset iraput signal, or data input (DI) 215 is input from the frequency selection carcuitxy contained within the control logic 909 of FIG. 9 and is applied to the first 3 0 accumulator 201 in FIG. 2.

The first accumulator 201 generates output signals 21?, 235 which represent the integral of the data input signal 215.

The data output signal 21? is WO 93/16523 PCI~/US92/t 117:

8 z~o~~~~ input into the second accumulator 203.

The carry output signal 235 is added directly to the differentiator 213, resulting in the data output signal 229.

This carry output signal 235 allows DC phase olEl'sets to be directly passod to the data output signal 229.

The data output signal 219 of tho second accumulator 203 is input into the third accumulator 205, likewise, the data output signal 221 of tlxe third accumulator 205 is input into the fourth accumulator 20?.

The carry output signal 223 of the fourth accumulator 207 1 0 is differentiated and combined with the carry output signal 231 from the third accumulator 205 resulting in the signal 225.

Signal 225 is input to a second differentiator 211 this resulting signal is combined with the second carry output signal 233, from the second accumulator 203.

The xesulting signal 22? is 1 5 input into the third diff'erentiator 213.

The illustration of FIG. 2 is used as a generic description of the fractional N synthesis with series recombination, specific implementations of this general method are illustrated in subsequent FIGS. 3, 4, 5, 6, ? and 8. FIG. 2 as 2 0 shown without latched output signals or digital delays will dramatically limit its practical utility.

FIG. 3 is an inzplementataon of the fractional N synthesis with series recombination illustrated in FIG. 2.

The implementation includes signal delays and latched 2 S accumulators.

It is an important feature of the invention that the data presented from one accumulator to the next accumulator only occurs during one clock cycle.

The data never goes from a first accumulator to a third accumulator during one clock cycle, thereby, avoiding the problem of 3 0 "rippling" through all the accumulators during one clock pulse.

The latched accumWators render the network 101 synchronized.

The "ripple" effect is the accumulation of WO 93/16523 PC.'C/US92/11173 delays inherent in the design of the circuit used to implement the design.

Ripple accumulators limit the number of accumulators possible in a given accumulator network given a fixed clocking frequency and the digital delays o.f the ci.rcuutry.

S Vfith a synchronized system, each function has a fixed delay of one clock period.

The synchro:niaed system latches the data at each function, so the data is delayed by one function during each clock period.

In this manner, a system of many accumulators can operate as fast as a system with only one accumulator.

In the network illustrated in FIG. 3, the total system delay would equal flares clock cycles plus the cumulative delay of the three adders 309, 311, 313, due to the internal digital delays.

The cumulative delay of the three adders 509, 311, 313 is not 1 5 present in the implementations of FIGS. 5 and 6, because of the addition of the fixed delays between the adders.

In. the preferred embodiment, the clock signal is generated from the output signal 125 of the divisor network 111, alternatively, the clock signal could be generated from the output of the 2 0 reference oscillator 107.

Note, in the preferred embodiment, latched accumulators are used in the implementation because the system is digital.

However, an analog equivalent system could be developed in accordance with the present invention which would include 2 5 analog integrators.

The first accumulator 301 performs a digital integration of the data input signal 333.

The output signal 335 is latched at the first occurrence of a clock signal.

The second accumulator 303 performs a digital integration of the contents of the first 3 0 latched accumulator 301, effectively creating a double integral of the data input 333.

At the second occurrence of said clock signal, the output of the second accumulator 303 is latched. A WO 93/16523 PCT/US92/11173 r' r~ ~.~ ~ 1 third accumulator 305 performs a digital integration of the contents on the latched output of the second accumulator 303, effectively performing a triple integral of tho data input 333.

Tho fourth latched accumulator 307 performs a digital integration of the contents of the latched accumulator output of the third accumulator 305, effectively creating a quadruple integral of the input data 333.

The carry output signal 351 of the first accumulator 301 represents that the output frequency (FO) of the VCO 113 has 1 0 acquired 360 degrees of phase error relative to the frequency of the signal output from the reference oscillator 1.07.

In order to correct this, the data output signal 229 is increased by one integer for the next clock interval and the internal contents o~ the first accumulator 303 is reduced by it's own capacity.

This 1 5 action effectively removes one cycle from the freduency of the phase comparator input signal 125, thus, resulting in a phase correction of 360 degrees at the VCO output signal (FO)119.

The derivatives 209, 211 and 213 of FIG. 2 are represented in FIG. 3 by the combination of a digital delay and an adder 2 0 such as 315 and 309. A derivative is digitally implemented by holding a previous sample of the signal and subtracting it from a present value of the signal.

The adder 309 also functions to combine the carry output of the third latched accumulator 347 with the output of the derivative of the fourth 2 5 latched accumulator.

The resulting signal 343 is sent through two subsequent derivations.

The digital delays allow the carry output signals recombined to be synchronized into the proper clock cycle.

The carry output signal 351 is delayed for three subsequent clock 3 0 cycles before it reaches the adder 313.

The carry output signal of the second latched accumulator 349 is delayed two clock cycles before reaching the adder 311.

Including the one clock WO 93/16523 PCT/US92/11173 11 cycle delay incurred from the brat latched accumulator 301, the carry output signal reaches the adder 311 at the third clock cycle.

The carry output of the third latched accumulator 347 is delayed ono clock cycle from its creation befare it is added to the adder 309.

This one delays occurs after the two delays from the first and second latched accwonulators, thereby reaching the adder at the third clock cycle.

So the variable divisor signal 229 has a three clock cycle delay plus the ripple effect from the output of the latched accumulator 307 and the three adders 1 0 309, 311, 313.

This synchronized system allows operation at a much faster clack speed, s- oaequently a much faster variance of the periodic sequence using the data input signal 333.

Recombining the carxy output signals of the accumulators in series reduces 'the numbe. .~f differentiatora needed in the 1 5 accumulator network.

Note that additional fixed delays, beyond those shown in FIG. 4, may b~ added to the system without any inherent problems, however, these additional delays would not add any effective benefits to the accumulator system.

2 0 FIG. 4 is a block diagram of a fractioaial N synthesis with latched accumulators and aeries recombination.

This implementation of the synthesizer accumulator network is similar tm that of FIG. 3 with the exception of the added delays 423, 429, 437 which are attached to the first three latched 2 5 accumulators carry output signals 45~, 457, 4~9.

These additional delay elements axe added to the lower order accumulators in order to obtain an all pass response to the input data and to obtain a residual noise correction term.

The residual noise term may be easily reconstructed iax digital form 3 0 for D to A conversion and application to the loop filter.

One example residual error correction circuitry is illustrated in FIG. 7.

WO 93/16523 PCT/US92/1117~ iz ~ ~. ~ '~ ~l'~ ~.

FIG. ? is a block diagram of a four accumulator system, such as that shown izx FIG. 4, in which the internal contents of the highest order latched accumulator 407 and the second highest order latched accumulator 405 are utilized in the subtraction of the residual noise term at the loop .filter 711.

The internal contents of latched accumulator 405 is delayed once by the delay element ?25 and then subtracted from the internal contents of the highest order latched accumulator 407 in the conventional add function 723.

This results in a term equal to 1 0 2-1624 at the output of adder 723.

Where Q4 is the quantization noise term.

Delay elements 721 and adder 719 form a digital derivative network.

The output of adder 719 will be -2-1(1-Z1)f14.

Delay element 717 and the adder 715 form a second digital derivative network.

The output of adder 715 will be -Z1 5 1(1-Z-1~Q4. A conventional digital to analog converter 713 then converts this output signal 735 to an analog form and scales the amplitude.

The analog output signal 733 is input to the loop filter via a capacitor 729.

The capacitor 729 is used as an analog derivative network to convert the voltage output of the D 2 0 to t~ converter 713 to a current suitable for application to the loop filter 711 in which the phase comparator drive is a current source. (The currents through a capacitor is the time derivative of the voltage) The correction term 733 has an additional delay as compared to the data output signal 453.

z 5 This delay is compensated by adding a delay 707 to the data output path to the variable frequency divider 703.

Thus, the data sequence at the input of the variable frequency divider ?03 is:

DO ~ z-5DI -~ z-1(1-z-1)'1Q4 3 0 where:

Dt) is Data ~ut signal DI is Data In signal ~O 93/16523 PCf/U~92111173 13 N~~r~~~r z-x represents x clock period delays in the z-transform domain.

Since the phase detector 705 compares phase curl not frequency the signal is effectively integrated upon passing through the phase detector 705.

Thus, the phase term of the phase detector output can be represented in the Z transfoxm domain as:

~corr = ~efDTz"5/(1-z-1) + Q4 z-1 (1-z-1) 3 } where K~ is the phase detector conversion gain.

The phase 1 0 correction term generated by the D to A converter 713 and the capacitor 729 can be represented in the Z transform domain as:

~corr = -AD/A C ~4 z-1 (1- z-1) 3 where AD/A is the D to A converter gain and C is the capacitance of the capacitor 729.

If the value of the capacitor 1 5 729 is chosen to be equal to the phase detector gain divided by the D\A conversion gain, then a cancelation of any residual noise terms is achieved.

The additional delay elements 423, 429, 437 are added in the carry output signals from the first three accwmulators 401, 403, 405 in order that the data output 2 0 sequence noise term will depend only on the fourth accumulator 407.

This allows the noise sequence to be easily reconstructed for use in a D to A converter which provides errar correction at the loop filter input.

Without these delay elements, the output noise term would involve factors from all 2 5 accumulators.

It would be difficult to derive a correction waveform from this type of output.

Note that capacitor 729 may be substituted with another form of derivation.

For example, an extra digital delay and an adder placed before the D1A converter such as those used at the 3 0 owtput of the series recombination, namely, digital delay 717 and adder ?15.

For cancellation of the gains, the gain of the ~'O 93/15523 PCT/US92/11 ~7:~ 14 D\A converter 713 must equal the gain of the phase detector 105.

FIG. 5 is an alternative implementation of the correction and synthesis accumulator network illustrated in FIG. 4.

Here, additional delays 523, 521 are added at the outputs of adders 5U9, 511 respectively.

The purpose of the additional delays is to remove the "ripple" effect caused by the digital delays within the string of adders.

As discussed previously, the output of the fourth latched accumulator 507 is input into 1 0 the addex 509, without the digital delays 523 and 521, there would be a ripple effect on the variable divisor signal 557.

By adding the delays we eliminate the ripple effect.

During the fifth clock, cycle, the data w4uld transition fr om the adder 509 to the adder 511.

During the sixth clock cycle, the data would 1 5 transition from adder 511 to adder 513.

Thereby only one digital delay is encountered during each clock cycle.

This modification allows a faster clock cycle.

FIG. 6 is an alternative embodiment including the additional delays between the adders but only minimal delays 2 0 at the outputs of the first three latched accumulators.

The embodiment illustrated in FIG. 6 is similar to that of the embodiment of FIG. 3, with the addition of a synchronous series recombination.

In the preferred embodiment, modulation information is 2 5 applied to the multiple accumulator digital network 400 of the fractional N synthesizer.

The modulation information is the 16 least significant bits of a 24 bit number coupled to the data input 439.

Since a transceiver which employs the present invention may be effectively utilized in a GSM Pan European 3 0 Digital R.a.diotelephone System, rapid frequency changes, modulation, and low spurious and noise levels are realized with a fractional N synthesizer.

For modulation, the WO 93/16523 PCT/LJS92/11173 fractional N synthesizer employs a look-up 'table to convert the data stream to be transmitted into frequency offsets for the fractional N synthesizer.

The loop division of the synthesizer is adjusted in accordance with the input data stream to follow 5 the instantaneous frequency offset required for the GMSK modulated signal.

This can be at the offset frequency or directly at the main frequency.

The latched accumulator fractional N synthesizer configuration is operated upon with large accumulators to 1 0 eliminate spurious signals, to provide D\A correction to reduce discrete spurious sigzlals and to provide direct digital modulation to the PLL.

In the GSM system, the data rate is 2~0.8333kb with a BT product of 0.3.

Where T is the bit period, equal to 1/ 270.8333kHz; and B is the baseband bandwidth of the 1 5 Guassian filter used to shape the baseband data.

This results in a baseband bandwidth of approximately 8lkHz which must be passed with low distortion through the PLL as modulation.

The actual frequency offset components of the GMSK signal range from lOHz to about ?OkHz.

This range 2 0 determines the length of the accumulators as it will be necessary to synthesize steps of less than lOHz in the preferred embodiment of the GSM system. A reference frequency of 26MHz, requires an accumulator of at least 22 bits, we chose 24 bits for 6implicity of using commercially available parts.

2 5 ~bviously, the desired instantaneous frequency offsets due to the modulation are well below the cut-off of the loop filter.

Therefore, the frequency synthesizer loop does not attenuate any of the fundamental frequency cha~elization spurious signals due to the modulation.

However, with a multiple 3 0 accumulator system this problem is overcome.

An overall transfer function for the system was previously defined as follows:

WO 93116523 PCT/US92/11 l,~'i 1s DO = z-5DI + z-1(1-z-1~Q4 This expression may be converted back to the frequency domain by the substitution of elm = z.

This results in the following expression for DO. (Note that this is a term-by-term magnitude expression.) DO = DI -h (2-2cos~cv~~ In the preceding expression, v is the frequency normalized to the folding frequency.

The folding frequency is equal to one h<zlf the rate at which the accumulator clocks operate.

1 0 The frequency versus attenuation curve.illustrated in FIG.

11 shows the output of each term of this expression.

Note that DI is passed with no distortion to the DO and each of the quantization noise terms (~) are high pass filtered.

It is possible and preferable to increase the 1 5 fractionalization such that all spurious outputs are moved to very low frequencies.

The combined effects of using many accumulators at a high rate of clock speed results in a large attenuation of the quantization noise of the fractional process.

Thus, a large denominator effectively reduces the frequency of 2 0 the spurious signals such that they fall well below the 3 db corner of the digital high pass filter formed by the multiple accumulator structure.

Using many accumulators increases the slope of the high pass filtering action increasing the rate of operation moves the corner frequency of the high pass filter up 2 5 in frequency.

In general the accumulator network 101 generates a time varying division ratio, N.

Ciive.n a Nth order fractional N system, the accumulators may be latched resulting in a synchronous system in which data does not need to ripple 3 0 through more than one accumulator during one clock cycle.

In a single delay system, the first, or lowest order accumulator output to the variable loop divider is delayed by N-1 clock units, PCT/US92/11173 '~~O 93/1623 17 2~~'~'~'~1 the next lowest level accumulator or the second accumulator is delayed by N-2 and so on until the next last accumulator is delayed by one clock unit and the last, or highest level accumulator is not delayed.

In a double delay system one additional delay unit is added to the output of all the accumulators except the last, or highest level accumulator.

Because of the synchronous nature of the system, it is able to operate at higher frequencies and thus allow the PBI bandwidth to be larger.

This allows faster lock times and 1 0 wideband digital modulation through the fractional divider while maintaining superior and predictable spurious performance. A digital representation of the remaining error is obtained in a form suitable to be used in a digital analog converter scheme.

The analog output of this conversion is 1 5 applied to the phass detector output to cancel any residual noise.

The series recombination within the latched accumulator network 101 allows for DC phase correciaons to be directly applied to the data output signal.

Additionally, the series 2 0 recombination reduces the number of components necessary in the recombination e~'ort as compared to Pascal triangle systems and the like.

FIG. 8 is an illustration of an implementation of fractional leT accumulator network as illustrated in FIG. 3.

The layout of 2 5 the network in the illustration is used to simplify description.

For example, accumulator network 849 contains the accumulator 833, the latch 841, the digital delay 825, 827, the combin.er 809 and the di.~erentiator 813.

These can be mapped onto the block diagram of FIG. 3.

Additional accumulator 3 0 networks can be added beyond each accumulator network 849 to make a IVth order accumulator network.

With the number of delays in a minimal delay system between the first WO 93/16523 ~'C'T/US92/1117~ 1$ accumulator 831 and the adder 807 equal to N-1, and the first accumulator network having N-1, the second accumulator network having N-2, and the third having N-3, and so on until there are no delays as illustrated in FIG. 8.

In a double delay system each accumulator netevork would have one additional delay except for the last, or highest order accumulator network.

What is claimed is: