Interfacing device for a computer games system

CA 02018165 1998-10-29 INTERFACING DEVICE FOR A COMPUTER GAMES SYSTEM BACKGROUND OF THE INVENTION FIELD OF THE INVENTION This invention relates to computer games systems and it relates particularly to an interfacing device for modifying the manner in which a computer game is played.

DESCRIPTION OF THE PRIOR ART A conventional computer games system typically includes a computer containing the main processing unit, a visual display unit (VDU) on which a game is displayed and which may constitute a part of the computer, some form of interactive unit (e. g. a keyboard or joystick) enabling a player or players to react to and influence events during the course of a game, and an external data storage medium (e.g. a game cartridge) that can be plugged into or otherwise connected to the main processing unit and that contains data defining the characteristics (e. g. the rules) of the particular game being played.

In general terms, the main processing unit is programmed to address different storage locations in the external data storage medium, whereby to access the stored data as it is needed.

To that end, the main processing unit generates an address identifying a respective storage location in the storage medium, and this address is routed to the storage medium on an address bus.

When the stored data is required, the processing unit sends a request signal to the storage medium, whereupon the data in the addressed storage location is accessed and then routed to the processing unit on a data bus.

The data stored in an external data storage medium determines the characteristics of the game stored therein and typically defines such game parameters as the number of playing units (e. g. cars, planes, etc. ), the number of lives ascribed -2 CA 02018165 1998-10-29 to individual players, the duration of particular events, time limits and speed settings, color and so on.

Generally, computer games require the players to complete various tasks (e.g. to complete a fixed number of laps of a track), and failure to complete a task satisfactorily results in some cases in the elimination of a player from the game.

In marry games, the players may be ascribed more than one "life", and this can affect the difficulty, or ease, with which the game is played.

With existing systems, the characteristics of a game, and in particular its degree of difficulty, are to a large extent predetermined by the data stored in the external data storage medium.

Consequently, existing computer games tend to lose their appeal and present less of a challenge to the player the more times they are played - that is to say the games have limited "playability" OBJECTS AND SUMMARY OF THE INVENTION It is an object of the present invention to alleviate the aforementioned shortcomings of existing computer game systems that can use an external data storage medium such as a cartridge with a read-only memory (ROM) and the like.

Another object of the invention is to provide an interfacing device for connecting a processing unit of a computer games system to an external data storage medium, the interfacing device being capable of operating in various ways, either user-selected or preset, for modifying the rules of the game, thereby enhancing the playability of the game.

The foregoing and other objects of the invention are attained by the provision of an interfacing device for connecting a processing unit of a computer games system to an external data storage medium so as to enable the processing unit to address, and receive data from, different storage locations in the external data storage medium, the interfacing device comprising means responsive to the processing unit for recognition of a selected address and means for modification of data processed by the processing unit in response to such recognition.

With an interfacing device constructed in accordance with the invention, the user has the capability to substitute his own, user-generated data for -3 CA 02018165 1998-10-29 that which would otherwise be supplied to the processor by the external data storage medium, and in this way the user can control and radically change the parameters of the game normally defined by the data stored in the external data storage medium and thereby enhance the "playability" of the game.

In a particular embodiment of the invention, the modification means comprises user-operable means for generating a first signal and a second signal representing the selected addresses and user-selected data respectively, means for comparing the selected address represented by the first signal with an address from the processor, and means for supplying the user-selected data to the processor, in substitution for the data in the addressed storage location of the external data storage medium if the compared addresses are the same.

The supplying means may be a semiconductor switching device responsive to an output from the comparing means.

In accordance with another aspect of the invention, there is provided a computer games system comprising a main processing unit, an external data storage medium and an interfacing device, in accordance with the first aspect of the invention, for interconnecting the main processing unit and the external data storage medium.

According to a yet further aspect of the invention there is provided a method of playing a computer game using a computer games system having a processing unit and an external data storage medium, including the steps of comparing an address from the processing unit with a selected address and modifying data supplied to the processing unit whenever the compared addresses are the same.

In accordance with another aspect of the invention, the modifying of the data takes place only if the data from the external data storage medium matches data set by user-operable input means (which may be switches, keypad, joystick, etc.).

In other words, the data is modified only if it is what the interface expects to find there.

Some large programs have "bank switching", which means that several banks of data are stored at each address.

This "data compare" feature of the invention ensures that only data at the correct address and the correct bank is modified.

-4 CA 02018165 1998-10-29 BRIEF DESCRIPTION OF THE DRAWINGS Interfacing devices embodying the present invention are now described, by way of example only, with reference to the accompanying drawings, in which:

Figs. la, lb and lc are respectively top plan, side and perspective views of an interfacing device in accordance with the invention;

Fig. 2 is a block diagram of circuitry used in the interfacing device of Figs. la, lb and lc;

Fig. 3 shows the circuitry of Fig. 2 in more detail;

Figs. 4a, 4b and 4c are respectively top plan, side and perspective views of another interfacing device in accordance with the invention;

Fig. 5 is a block diagram of circuitry used in the interfacing device of Fig. 4;

Fig. 6 is a block diagram of an alternative embodiment of the invention;

Figs. 7a, 7b, and 7c are respectively top plan, side and perspective views of another embodiment of an interfacing device according to the invention;

Fig. 7d is a perspective view showing an embodiment of the present invention just prior to its connection to a game cartridge;

Fig. 7e is a perspective view showing apparatus in accordance with the invention after it has been connected with a game cartridge to form an assembly;

Fig. 7f is a perspective view showing the assembly of Fig. 7e just prior to insertion in a games machine;

Fig. 7g is a side elevation showing the apparatus after the insertion of the assembly of Fig. 7e in a games machine;

Figs. 8a and 8b collectively form a block diagram of circuitry used in the interfacing device of Figs. 7a, 7b and 7c;

Fig. 8c is a more detailed block diagram of a portion of the circuitry of Fig. 8a;

Fig. 8d is a more detailed block diagram of a portion of the circuitry of Fig. 8b;

-5 CA 02018165 1998-10-29 Fig. 8e is a schematic diagram showing 16 character cell definitions achievable in a cell measuring 8 x 8 pixels wherein only each group of 4 x 4 pixels is selectable on or off;

Fig. 8f is a truth table relating the inputs and outputs of Fig. 8d to each other and to the 16 character cell definitions of Fig. 8e; and Figs. 9a, 9b and 9c when taken together form a flow chart showing the steps of a process performed with the aid of the circuitry of Figs. 8a - 8d.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The interfacing device shown generally in Figs. la, 1b and lc comprises a shallow case 1 of which one end 2 is intended to fit into a receiving port of a computer games console such as the well-known Nintendo console and the opposite end 3 is intended to receive an external data storage medium (hereinafter referred to as a memory), such as a cartridge having a read-only memory (ROM).

The case contains a printed circuit board 4 that carries interfacing circuitry, the board 4 being provided at each end thereof with suitable end connectors enabling the interfacing circuit to detachably interconnect the main processing unit of the games console and the external memory.

As will become clear hereinafter, in this embodiment of the invention user-adjustable switches 5 set into the upper wall 6 of case 1 may be utilized to modify the manner in which a game stored in the memory is played.

In the illustrated example, six 16- position rotary switches are provided.

As Fig. 2 shows, the interfacing circuitry comprises a main address bus 11 for interconnecting the address bus 11' of the main processing unit and the address bus 11" of the external memory, whereby addresses can pass from the main processing unit to the memory.

Similarly, the interfacing circuit has a main data bus 12 that interconnects the data bus 12' of the main processing unit and the data bus 12" of the external memory, whereby data can pass from the external memory to the main processing unit in response to received addresses, provided such data has not been blocked by circuitry (to be described) in the interfacing device.

-6 CA 02018165 1998-10-29 The interfacing device has a user-operable selection unit 13 by which the user can generate a user-selectable address (A,~ and user-selectable data (D,~.

The user-selectable address (A,~ is routed on a subsidiary address bus 14 to one input h of an address comparison circuit 15, and the user-selectable data (D,~ is routed on a subsidiary data bus 16 to an input of a data switching device 17.

As Fig. 2 shows, addresses on the main address bus 11 (which are, of course, generated in the main processing unit) are routed to a second input IZ of the address comparison circuit 15 for comparison with the user-selectable address (A,~ at the first input h.

If the compared addresses are different, data from the external memory is routed, via the switching device 17, onto the main data bus 12 for onward transmission to the main processing unit.

If, however, the compared addresses are the same, the address comparison circuit 15 generates an actuation signal on line L causing the data switching device 17 to change its switching condition, blocking the transmission of data from the external memory and routing the user-selected data D" onto the main data bus 12 for onward transmission to the main processing unit.

By this means, the user-selected data generated by selection unit 13 is substituted for data from the respective storage location of the memory upon recognition of an address selected by the user.

This substitution may be illustrated by the following simple example.

It will be assumed that the user has set the user-selectable address A" at a value 1002 (which location contains "7") and the user-selectable data D" at a value "3".

In fact, as will be described hereinafter, the selected address and data are normally encoded in accordance with a hexadecimal coding format, though of course this is not a requirement.

If the current address from the processing unit is 1001, say, it is not recognized by the address comparison circuit 15 and so the data held on the addressed storage location of the external memory (i.e. that corresponding to address 1001) is routed to the main processing unit on the main data bus 12.

The stored data supplied to the processing unit in this way might have the value "9", say, different from the value of the user-selected data.

CA 02018165 1998-10-29 If, on the other hand, the current address from the processing unit is the same as that selected by the user, then the user-selected data, having the value "3", is supplied to the processing unit in substitution for the data stored in the addressed storage location of the external memory.

The alternative data values ("3" and "7") may represent the number of lives ascribed to a player and so, by changing the value from "7" (the value stored in the external memory) to a different value ("3" in this example), the user has the capability to modify (increase in this example) the difficulty of the game to a desired extent.

Fig. 3 shows the interfacing circuit in somewhat more detail.

The main address and data buses, which interconnect the main processing unit and the external memory, are again referenced at 11 and 12 respectively, and a data request bus is shown at 18.

The user-controllable selection unit 13 comprises two banks 21, 22 of user-selectable switches, one 21 of the banks comprising switches Ao. . . . .

A 14 for setting the user-selectable address A" and the other 22 of the banks comprising switches Dra. . . . . D7 for setting the user-selectable data D".

The switching arrangement shown is appropriate to generate binary address and data signals encoded in accordance with the hexadecimal coding format and can in practice be embodied as respectively four and two 16-position rotary, or alternatively configured, switches.

Alternatively, a preset plug-in pin connection package can be substituted for the arrangement of switches.

The user-selectable address and data signals can alternatively be held in latches.

In this case many types of data entry system (e. g. , keypad, voice input) can be used to set the latches.

The data switching device 17 comprises three identical integratedcircuit data switches 23(1), 23(2), 23(3) (Ref.

No. 74HC4053P) which are connected, as shown, to the external memory and to the bank of switches 22 by the main and subsidiary data buses 12 and 16, respectively.

The address comparison circuit 15 comprises two identical integrated circuits 24(1), 24(2) (Ref.

No. 74L,S684N) that are connected, as shown, to the main processing unit and the bank of switches 21 by the main and subsidiary address buses _g_ CA 02018165 1998-10-29 11, 14 respectively, and an integrated OR gate 25 (Ref.

No. 74LS32) is provided to effect a change in the switching condition of the device 17 in response to recognition by the address comparison circuit 15 of an address selected by the user.

While the described embodiment enables recognition of a single address and substitution of data corresponding thereto, the invention also embraces recognition of two or more different addresses and substitution of the respective data corresponding thereto.

In another embodiment of the invention, shown in Figs. 4 and 5, the interfacing device utilizes preselected addresses and preselected data.

The embodiment shown in Figs. 4 and 5 is similar to that shown in Figs. 1 to 3, and common components are given like reference numerals.

However, in this embodiment, the user operable switch (shown at 13 Figs. 2 and 3) is replaced by an internal memory in the form of a read-only memory (ROM) 40.

The subsidiary address bus 14 connects the address output address output of the ROM 40 to a 24-bit address comparison circuit 15 via two address latches 41 and 42 that are connected in parallel, and the subsidiary data bus 16 connects the data output from the ROM 40 to the input of an 8-bit buffer 43 via a further latch 44.

The output of the buffer 43 is connected to the main data bus 12, which, as shown, also incorporates an 8-bit buffer 45.

Both buffers 43 and 45 are controlled by an address comparison signal L generated by the address comparison circuit 15, whereby data is selectively routed to the processing unit either on the main data bus 12 or on the subsidiary data bus 16, depending on the result of a comparison carried out in the address comparison circuit.

Latches 41 and 42 are set to hold the high and low bytes respectively of a preselected, two-byte (16-bit) address AP transmitted thereto from the ROM 40 over the subsidiary address bus 14.

Similarly, the latch 44 is set to hold pre-selected data Dp (corresponding to the preselected address Ap in the latches 41 and 42) transmitted thereto from the ROM 40 over the subsidiary data bus 16.

-9 CA 02018165 1998-10-29 The preselected address Ap held in the latches 41 and 42 is compared with the current addresses transmitted from the processing unit over the main address bus 11.

If the compared addresses are different, the address comparison signal L goes high, thereby maintaining the buffer 43 (which is supplied via an invertor 43a) closed and the buffer 34 (which is supplied via a logical AND gate 46) open and allowing data to pass directly from the external memory to the processing unit over the main data bus 12.

However, if the compared addresses are the same, the address comparison signal L goes low, thereby maintaining the buffer 43 open and the buffer 43 open and the buffer 45 closed and enabling the preselected data Dp held in the latch 44 to pass to the processing unit in the substitution for the data in the external memory.

In this embodiment, the interfacing device has the capability to modify data received from any one of a range of different external data storage media (containing different computer games) that can be plugged into the device.

To that end, the ROM 40 stores a plurality of different pre-selected addresses together with a corresponding plurality of different preselected data, and each preselected address is utilized in conjunction with the corresponding preselected data to modify the data from a respective external memory.

Clearly, in order to access the correct preselected address (and data) to the latches, to enable address comparison and (possible) data substitution to take place, the interfacing device must be capable of identifying which external memory has been plugged into its receiving port.

To that end, additional control circuitry is provided that, in effect, enables the interfacing device to interrogate two data bytes of the external memory.

These data bytes carry sufficient information to unambiguously identify the external memory and thereby enable the correct preselected address and the corresponding preselected data to be accessed to latches 41, 42 and 44 to facilitate the desired data substitution, as described hereinbefore.

-10 CA 02018165 1998-10-29 The identification procedure is controlled by means of a controller 50 that is clocked by a counter 51 operating in conjunction with a clock circuit 52 and a "power-on" timing circuit 53.

When the external memory is first plugged into the interfacing device and power is supplied to the processing unit, the counter 51 is initialized and the external memory is isolated from the processing unit (by setting input A of the AND gate 46 low).

The controller 50 then transmits successive control signals to the ROM 40 on a control bus 54, causing the high and low bytes of the first address stored in the ROM 40 (corresponding to the first data byte for identification in the external memory) to be routed to the latches 55 and 56 respectively.

In this way, the latches 55 and 56, which are connected to the external memory via the main address bus 12, are set to hold the first address (corresponding to the first data byte in the external memory).

In response to this address, the first data byte is transferred from the external memory to an encoder 57 (the main data bus 12 being blocked by the buffer 46), where it is latched.

This procedure is repeated for the second data byte for identification in the external memory, which is also transferred to, and latched in, the encoder 57.

The encoder 57 then performs preset, logical operations on the first and second latched data bytes and generates an output that uniquely identifies the external memory.

This output is held in a ROM latch 58 (which had previously held a zero data field), and the encoder 57 is then disabled.

The controller 50 selects from the ROM 40 the pre-selected address (and the preselected data) appropriate for the external memory represented by the output held in the ROM latch 58 and causes the high and low bytes of this preselected address to be transferred to the latches 41 and 42 respectively and the required preselected data to be transferred to the latch 44.

As described hereinbefore, the address comparison circuit 15 compares the latched, preselected address with the current addresses from the processing unit.

However, the address comparison circuit 15 also compares current data transmitted from the external memory over the main data bus with data held in a fourth latch 47.

The latched data (which is also derived from the ROM 40) is chosen to be the same as the data (from the external memory) which is to be replaced by the preselected -11 CA 02018165 1998-10-29 data held in the latch 44.

This additional comparison ensures substitution of the correct data and prevents errors which could arise as a result of an ambiguity in the process of comparing addresses.

The ROM 40 have a number of different data banks, and so the data and address associated with each external memory may have a number of alternative values.

In these circumstances, a user-operable switch 59 may be provided, enabling the user to select a desired data bank from the ROM 40 and thereby select a desired effect, e.g. a desired degree of di$'lculty (hard, medium or easy, say) with which the game is to be played.

In the described embodiment, each preselected address is allocated to a respective external memory.

Alternatively, however, more than one of the preselected addresses can be allocated to the same external memory, thereby enabling more than one aspect of a game to be changed.

In another embodiment of the invention, illustrated in Fig. 6, an interfacing device for a computer games machine connects to the external program cartridge and the computer games machine allows the program cartridge to function normally except for one or more modifications performed by the interface.

These modifications affect one or more aspects of the game and can be either user selected or preset in the interface.

In this respect, the embodiment of Fig. 6 is the same as the other embodiments.

However, in the embodiment of Fig. 6, the interface allows the program to execute normally but interrupts the processor at a particular point or points (user-selected or preset) in the program.

When this interrupt occurs, the game is temporarily suspended while the interface banks its own ROM into the processor's memory and executes a piece of code.

This code is such that a modification is effected on the games computer's internal memory.

This interface then banks its own ROM out and allows the computer to continue executing the game as if nothing had happened.

This process allows a user or a preset ROM to change many of the variables that control aspects of a game, modifying the game in countless different ways.

-12 CA 02018165 1998-10-29 The effect of this is very similar to the effect of the previous embodiments.

The manner of operation is, however, different.

Instead of changing the way the computer interprets or accesses external memory, this method changes the computer's internal memory itself in such a way that very similar results can be achieved: e. g. , extra lives, skipped levels, increased or decreased car speed, etc.

Conventional devices that interrupt a program perform a designated function and then pass control back to original program.

The purpose is normally to perform additional tasks rather than to change the way the existing program works.

Also, the conventional devices are normally "stand-alone units" that do the same thing regardless of the program that is running.

In contrast, the apparatus of the present invention produces its visible and audible effects in a manner that is intrinsically dependent on the "host" program.

Moreover, it acts as an interface between the computer and the external memory in order to prevent access to the external memory when it wants to present its own program to the computer instead.

Conventional interrupt-controlled devices are activated entirely independently of the program that is running.

In contrast, apparatus constructed in accordance with the present invention is activated upon detection of the exact address of a particular piece of program being accessed.

It then makes changes to the computer's internal memory to affect the way the program works.

This is not needed in conventional usage because it is easier for the original programmer to make the change before the external memory is produced.

In Fig. 6, the device 70 is an interface between a games computer (via edge connector 71) and a plug-in game cartridge external memory (via connector 72).

The address comparator circuit 73 compares the value on the address bus 74 with a preset value, in this case a value supplied on a bus 75 from registers 1 and 2.

When the compared values are different (i. e. normally), the computer accesses the external memory unhindered.

When the compared values are equal (i.e. the program is at the correct stage for the device to interrupt), an output signal is sent on control line A to a switch circuit 76, which in a practical embodiment may be a semiconductor device.

-13 CA 02018165 1998-10-29 This has the effect of connecting the output enable line 80 from the computer through the switch 76 and alternative output enable line 81 to the device's internal ROM 77 instead of connecting the output enable line 80 to the external memory edge connector 72 through the extension 80a.

At this point, the computer starts addressing the ROM 77 instead of the external memory.

The ROM 77 can then make changes to the RAM and other registers housed in the computer (or in the interface 70) to effect changes in the way the program operates.

The switch 76 then reverses and re-enables the external memory by switching the output enable line 80 back to connect from the computer to the external memory through the extension 80a.

In this example, this is done by way of register 3, which controls control line B.

The program then continues where it left off but operating differently because of the changes that have been made.

When the external memory programs (games) are running on a computer, they constantly use the computer's internal RAM as a temporary scratchpad for storing values that change.

These values are typically used for parameters such as number of lives remaining, current level number, counters for timing loops (speed), number of cars, etc.

In accordance with the present invention, the user - or the programmer of the ROM 77 - can change these values in response to reaching a particular point in the program.

Figs. 7a, 7b and 7c are respectively top plan, side and perspective views of another embodiment of an interfacing device according to the invention.

These figures show the best mode contemplated by the inventors for putting the invention into practice.

The device comprises, as in the embodiments described above, a case 1 of which one end 2 is intended to fit within a receiving port of a computer games console and the opposite end 3 is intended to receive an external data storage medium or memory, such as a cartridge having a read-only memory or ROM.

The case contains, as in the embodiments described above, a printed circuit board 4 that carries interfacing circuitry, the board 4 being provided at each end thereof with suitable end connectors enabling the interfacing circuit to detachably interconnect the main processing unit of the games console and the external memory.

-14 CA 02018165 1998-10-29 A handle portion H of generally triangular construction (as viewed from above) has an inclined portion I, a stop S and a concave thumb rest TR provided with ridges R.

The external data storage medium is connectable to the interfacing device in such a manner as to be positioned underneath the handle portion H.

By virtue of the concave thumb rest TR formed on the upper surface of the handle portion H, an assembly of the interfacing device and the external data storage medium can conveniently be grasped with a thumb engaging the thumb rest TR and fingers engaging the external data storage medium for connection of the assembly to the processing unit of a computer games system.

Moreover, the protruding thumb rest TR, and particularly the stop S thereof, prevents inadvertent insertion of the assembly of the interfacing device and game cartridge into the computer games machine in an upside-down relation, since the stop S will in case of such an attempted erroneous insertion latch on the lower rim of the cartridge-receiving opening into the games machine.

Fig. 7d is a perspective view showing a "game X", which can be any conventional game cartridge, about to be assembled with the device according to the invention.

Fig. 7e shows the game cartridge and the device according to the invention in assembled relation, and Fig. 7f shows the assembly about to be inserted into a games machine, for example a Nintendo machine.

As noted above, the assembly is corneniently grasped with the thumb of the user in the thumb rest TR and the fingers of the user below the game cartridge.

The assembly is inserted and appears then as in Fig. 7g, with the lid of the games machine resting on the thumb rest TR.

The printed circuit board 4 is thicker than normal, to allow the edge connector to make good contact with the games machine connector without the need for the interface to be pushed down fully in the normal way.

That is, the printed circuit board 4 has sufficient thickness that the connection of the assembly of the interfacing device and game cartridge to the processing unit of the computer games machine can be effected with a movement that is rectilinear.

This enables the unit to be made smaller overall and more elegant than it would otherwise be.

The circuitry incorporated in the device of Figs. 7a - 7g is illustrated in Figs. 8a - 8c.

The circuitry shown in these figures has two modes of operation.

Mode 1 is a latch-setting mode, wherein values for the address comparison, data -15 CA 02018165 1998-10-29 comparison, and data replacement functions are set by the user.

Mode 2 is an active mode, very similar to the operation of the embodiments described above, wherein the address comparators (as well as data comparators) send a signal to a data replacement unit to effect a replacement of the data when the conditions for data replacement are met.

The selection of mode 1 or mode 2 is made by an output signal from a control latch 103 on a mode select line 102. A CE line 92 that comes from the computer edge connector 71 (for example, from a video games machine made by Nintendo) is connected to the CE selector 90, which is controlled by the signal on the line 102.

In conventional structures, the line 92 would normally connect directly to the external memory, allowing it to respond to data read/write requests from the video games machine.

In the circuit of Fig. 8a, the signal on the line 92 is passed either to the external memory 93 via a CE' line 94 or to an interface ROM 96 via a CE" line 98, depending on the state of the line 102.

In this way, either the external memory 93 or the interface ROM 98 is made active.

The circuitry also has a poweron circuit 100, which ensures that the line 102 from the control latch 103 is set to the latch setting mode when the power is first turned on.

MODE I: LATCH-SETTING MODE The purpose of this mode is to allow the user to select the address comparison data and replacement data.

The program in the ROM 96 is designed in such a way that it will accept input from the normal game control pad, operated by the user, and use it to move an on-screen pointer around the screen.

Also on the screen there are 16 different letters (which represent values).

The user can move the pointer to any of these letters and select them using a button on the game control pad.

By repeating this process the user can enter this data to represent addresses, comparison data bytes and replacement data bytes, as well as function enable/disable information.

When the user presses the start button on the game controller, the software scores the data entered by the user in the latches in each of the comparison/replacement units 1, 2 and 3 as well as in a control latch 103.

-16 CA 02018165 1998-10-29 It then sets a particular bit "0" in the control latch 103, which alters the state of the mode select line 102, thereby switching the device to its active mode by changing the state of the CE selector 90 to its other position.

This has the effect of conditionally enabling the comparison/replacement units 1, 2 and 3.

MODE II: ACTIVE MODE In this mode, the external memory has control of the CPU and the game will function normally, with the exception of any data replacement operations performed by the interface.

The comparison/replacement units are now active, provided that the appropriate bit in the control latch has been set to enable them.

The structure illustrated in Figs. 8a, 8b and 8c includes an address bus 104 connected to comparison/replacement units 1, 2 and 3 and a data bus 105 connected to the same units.

At the left of Fig. 8a, the address and data buses connect to the games machine, and at the right of the game cartridge that is currently in use.

In addition, a read/write line 106 is connected to the comparison/replacement units 1, 2 and 3, to the ROM 96 and to the video games machine and the particular game cartridge in use.

The chip enable line 92 is connected to the chip enable or CE selector 90 as described before and also to the comparison/replacement units 1, 2 and 3.

The address and data buses 104, 105 are also connected to the ROM 96, and the address bus 104 is connected to a register address decoder 107.

The latter produces three outputs which go respectively to inputs R. SELO. . . 3 of each of the comparison/replacement units 1, 2 and 3.

As Fig. 8c shows, the latter input goes to a replacement data latch 0-7, a comparison data latch 0-7, a comparison address latch 0-7, and a comparison address latch 8-14.

The data bus 105 also connects to the control latch 103, which produces the output on the line 102 to the CE selector, as noted above.

The output on the line 102 also goes to the register address decoder 107 and to an output to Fig.

8b labelled G.CONT (graphics control).

-17 CA 02018165 1998-10-29 The control latch 103 produces an output to an input labelled R. EN on each of the comparison/replacement units 1, 2, and 3 and an output to an input labelled DC.EN on each of the comparison/replacement units 1, 2 and 3.

Each of the comparison/replacement units 1, 2 and 3 produces an output on a terminal labelled REP ("replace") which is supplied to the CE selector 90.

In Fig. 8b, the graphics address 0-12 bus is connected to a graphics generator 110, which produces an output to a graphic output buffer 111. A device selector 112 receives inputs from the G. CONT terminal and from a G CE terminal and produces outputs to the graphic output buffer 111 and the G CE terminal of the game cartridge.

The graphics lines GWE and GOE connect through Fig. 8b from the games machine to the game cartridge in use, and the latter line connects also to the graphic output buffer 111.

In Fig. 8c, the replacement data latch 0-7 connects to an 8 bit buffer 115.

An 8-bit comparator 116 receives comparison inputs from the data line DO7 and the comparison data latch 0-7 and produces an output signal to a control 117 when the inputs are equal. A fifteen bit comparator 118 receives at one input an output from the comparison address latch 0-7 and an output from the comparison address latch 8-14 and at the other input data from the address line 0-14.

It produces a control output to the control 117 when the inputs are equal.

The control 117 also receives signals from the R.EN, read/write, chip enable, DC.EN and F EN terminals.

Its output controls the 8-bit buffer 115 and is also supplied to the output terminal REP The Graphics Generator Certain computer games devices, for example, one made by Nintendo, normally generate a screen display by reading data from a graphics ROM.

This data defines the bit patterns that make up the letters and graphical shapes that appear on the screen.

The screen is made up of many character- or letter-sized squares (or rectangles), called character cells, which are 8 by 8 pixels (picture elements, or dots) -18 CA 02018165 1998-10-29 in size.

Each pixel is defined by 2 bits in memory, representing one of four colors.

Usually, the graphics ROM is a minimum of 8K bytes in size, giving 512 different character cell definitions, as is needed for a normal game.

This allows the system to produce colorful, detailed and varied graphics displays.

When in its latch setting mode, the device of Figs. 8a - 8d needs to use the screen for display purposes.

Specifically, it needs to display the 16 letters for the user to choose from, the selected letters, and the product name at the top of the screen.

It has been found it is not necessary to use the full capability of the normal graphics system, and that the complexity, size and cost of the device can be reduced by eliminating the graphics ROM chip normally required.

In accordance with the invention as embodied in the circuitry of Fig.

8d, a simple circuit emulates a graphics ROM containing the 16 character cell definitions (Fig. lOb).

Even though the graphics produced with this system are cruder (only each group of 4 by 4 pixels is selectable on or off, instead of each pixel being individual selectable) it is perfectly adequate for the purpose of displaying the 16 letters, selected letters and product name.

In Fig. 8d, a small circuit is added to the circuitry needed for the rest of the device.

The circuit of Fig. 8d has a negligible cost and size, in contrast to the substantial cost and size of the separate ROM which would otherwise be required.

The graphics generator and the graphic output buffer of Fig. 8d together function as a graphics ROM emulator circuit.

A cornentional computer games device such as one made by Nintendo is designed specifically to get its graphics data from external memory (ROM or RAM).

The structure of Fig. 8d eliminates the need to have any external memory for graphics generation.

In Fig. 8d, the graphic generator 110 and graphic buffer output 111 are of course the same as the units shown schematically in Fig. 8b.

Fig. 8d shows the inputs to the graphic generator 110 on lines GA 2, GA 4, GA 5, GA 6 and GA 7 and outputs on lines GD 0, GD 1, GD 2, GD 3, GD 4, GD 5, GD 6 and GD 7 plus a select input G. OE and C. CE' .

The graphic generator 110 includes four AND gates 201, 202, 203, 204, two OR gates 205, 206 and an invertor 207.

If the input GA 2 is high, the OR -19 CA 02018165 1998-10-29 gate 205 is high only if the input GA 4 is high and the OR gate 206 is high only if the input GA 4 is high and the OR gate 206 is high only if the input GA 5 is high.

On the other hand, if GA 2 is low, then the OR gate 205 is high only if GA 6 is high and the OR gate 206 is high only if GA 7 is high.

The object of the circuitry in Fig. 8d is to produce the 16 character bit patterns of Fig. 8e, these patterns being numbered respectively 0-15.

Since 4 x 4 pixels are addressed as a unit, there is a sacrifice of resolution, as indicated above, but, for reasons also indicated above, it is of no particular consequence.

In Fig. 8e, (and also in the output portion of Fig. 8f), a space that is not blackened corresponds to "0", and a space that is blackened corresponds to "1".

There is, of course, only one combination of all "0's" and similarly only one combination of all " 1's" .

These two possibilities correspond to "0" and "15", respectively, in Fig. 8e.

There are four different ways in which one darkened space can be arranged, corresponding to boxes 1, 2, 4 and 8 in Fig. 8e.

Similarly, there are four ways in which 3 darkened spaces (i.e., one space that is not darkened) can be arranged, namely those corresponding to 7, 11, 13 and 14 in Fig. 8e.

Finally, there are 6 ways in which 2 darkened spaces (corresponding to 2 spaces that are not darkened) can be arranged:

these correspond to 3, 5, 6, 9, 10 and 12 in Fig. 8e.

Fig. 8f is a truth table showing the address lines in a logical order and the data values they produce to make the 16 character shapes.

In Fig. 8e, all address line combinations are shown in binary order.

Of course, the order can be changed and is not critical.

The character bit patterns produced can be viewed with the left side of Fig. 8f up to see the character shapes from the same perspective as in Fig. 8e.

When the input line GA 2 is set to "0" it designates the top half of the pattern and when set to "1" designates the bottom half.

The OR gate 205 produces an output which is supplied to the four input terminals of the buffer 111 that relates to the output lines GD 4 - GD 7, and the OR gate 206 produces an output which is supplied to the four input terminals of the buffer 111 that relate to the outputs GD 0 - GD 3.

Accordingly, in Fig. 8f, in the case of pattern " 1 ", for example, the inputs GA 4 - GA 7 of respectively " 1 ", "0" , "0" , "0" correspond to no shading in the third quadrant of the output; but when GA 2 changes to " 1 ", the same inputs GA 4 - GA 7 of " 1 ", "0" , "0" , "0" correspond to shading -20 CA 02018165 1998-10-29 in the third quadrant.

In a similar way, the inputs GA 2 and GA 4 - GA 7 shown in Fig. 8f produce the outputs on GD 0 - GD 7 shown in Fig. lOf to form all of the bit patterns "0" through "15".

These patterns are shown more pictorially in Fig.

8e.

The operation of the circuitry of Figs. 8a - 8d will now be described in connection with the flow chart of Fig. 9.

Figs. 9a, 9b and 9c when taken together form a flowchart showing the process performed with the aid of the circuitry of Figs. 8a - 8d.

In Figs. 9a 9c, steps 201 and 202 are performed by the power-on circuit, steps 203-213 by the interfacing ROM, steps 214 and 215 by the program in the internal memory of the games machine, and steps 217-227 by the interfacing ASIC.

When power is turned on as indicated at step 201 in Fig. 9a, the process moves to step 202, wherein the control latch defaults to a value which sets the CE selector 90 so as to enable the ROM 96 on line CE" 98.

The process then moves to step 203, wherein the ROM 96 begins execution and the screen in accordance with the invention appears on the display screen on which the game is displayed.

At step 204, the program in the ROM determines whether the user has pressed a button on the control pad.

If the user has not pressed such a button, the program loops back and makes the determination repeatedly until it is found that user has pressed a button on the control pad.

When an affirmative determination is made, the program moves to step 205, wherein a determination is made whether a movement button has been pressed by the user.

If so, then at step 206 the program moves the cursor to a new letter and then reverts to step 204.

If no movement button has been pressed, the program determines whether a fire button has been pressed by the user.

If so, the program causes display of the letter under the cursor on the screen as a selected letter and then loops back to step 204.

If the fire button is not found to have been pressed, the program determines at step 209 whether the start button has been pressed.

If not, the program loops back to step 204.

When the start button has been pressed, then, as Fig. 9b shows, the program converts the selected letters (if any) to hexadecimal values which represent data to be stored in the latches.

At step 211, the program then stores hexadecimal values in latches corresponding to the addresses, data replacement values, and data -21 CA 02018165 1998-10-29 compare values (if any).

Then, at step 212, a program is transferred to the control deck's internal RAM.

At step 213, control is passed to the program in the RAM.

At step 214, the program in internal memory stores a value in the control latch with the CE selector bit set so as to enable the external memory on the line CE' 94 (Fig. 8a) and conditionally enable the comparison/replacement units 1, 2, 3 and disable graphic emulation.

At step 215, control is passed to the reset address of the external memory and, at step 216, the game program begins execution.

At step 217, the device determines whether the game control is requesting a read from the external memory.

If not, it loops back until an affirmative determination is made.

When an affirmative determination is made, the device determines whether the value of the address bus corresponds to the address stored in one of the comparison/replacement units 1, 2 and 3.

If not, the process loops back to step 217.

When an affirmative determination is made, the process advances to step 219 (Fig. 9c).

At step 219, a determination is made whether the corresponding comparison/replacement function is enabled.

If not, the process loops back to step 217.

When it is found at step 219 that the corresponding comparison/replacement function is enabled, then, at step 220, a determination is made whether the corresponding data comparison function is enabled.

If it is determined that the function has been enabled, the process advances to step 221, where a determination is made whether the value of the data bus corresponds to the comparison data stored in the corresponding address/comparison unit.

If no such correspondence is found, the process loops back to step 217.

If at step 220 the corresponding data comparison function is not enabled, or if at step 221 the value of the data bus is found to correspond to the comparison data stored in the corresponding data and comparison latch, the process moves to step 222.

At step 222, the external memory is prevented from outputting data by setting the CE selector to disable the line CE' 94 (Fig. 8a) via the terminal REF.

Then, at step 223, the corresponding comparison/replacement unit is set to output the data stored in its data replacement latch to the data bus.

At step 225, a determination is made whether the read cycle is finished.

If not, the process stays in the loop at step 225 until it is determined that the read -22 CA 02018165 1998-10-29 cycle is finished.

When the read cycle is finished, the process advances to step 226.

AT step 226, the corresponding comparison/replacement unit is prevented from outputting data.

Then, at step 227, the external memory is re-enabled by enabling the line CE' 94 (Fig. 8a).

The process then loops back to step 217 in Fig. 9b.

The versatility of the described interfacing devices is demonstrated by short extracts from typical computer games programs given in Examples I and II below.

In these examples, the four-digit numbers (e. g. 3000) appearing in the left-hand column are coded addresses; they are followed by coded instructions (e. g.

DEC1000) from the addressed storage location of the external memory.

In fact, in the examples given, each instruction consists of two or three bytes.

An explanation of the function of each instruction is given in the right-hand column.

~Y A ll~tDT ~ T This section of the program causes a unit, e. g. a plane or car, to move at a particular speed.

ADDRESS INSTRUCTION EXPLANATION 3000 DEC 1000 This reduces the content of address 1000 by 1 (e. g. a value 28 changes to 27).

3003 BNE 300D If the value of the last step is not zero the program returns to address 3000.

3005 LDA 50 This puts value 50 (from the storage location corresponding to address 3006) into a variable "A" .

3007 STA 1000 This puts the value of variable A (i. e. 50) into address 1000.

300A JSR "MOVE UNIT" This calls up subroutine "MOVE UNIT" which causes the unit to move.

300D JMP 3000 The section of the program set out above is repeated.

-23 CA 02018165 1998-10-29 This section of the program causes the subroutine "MOVE UNIT" to be executed when the program steps corresponding to addresses 3000 to 3003 have been executed 50 times.

If, therefore, the interfacing device sets the selected address at 3006 and sets the selected data value at 10, then the value 50 in variable "A" in the processor (the value in the corresponding storage location of the memory) is replaced by the user-selected value (10 in this example).

This causes the subroutine "MOVE UNIT" to be executed when the program steps corresponding to addresses 3000 to 3003 have been executed 10 times instead of 50 times.

Consequently the playing unit is caused to move more quickly.

EXAMPLE II In this game, a player is required to complete a given number of laps of a track.

ADDRESS INSTRUCTION EXPLANATION 2000 INC 1200 This increments the content of address (LAP COUNT) 1200 by one (increasing the lap count by one every time a player completes a lap).

2002 LDA 1200 This puts the content of address 1200 into variable A (i.e. it puts the current lap count into variable A).

2004 CMP 3 (LAP 3?) This compares the last value of the lap count with 3 (the value derived from the storage location corresponding to address 2005).

2006 BNE 200A If the answer is no (i. e. , the comparison shows an inequality), then the program goes to 200A; otherwise it continues on.

2008 JMP "RACE This causes a jump to the "RACE COMPLETE" COMPLETE" part of the program.

-24 CA 02018165 1998-10-29 This number of laps required to be completed by the player is set at the value 3 derived from the addressed storage location of the memory.

If, therefore, the interfacing device sets the selected address at 2005 and sets the selected data value at 7, say, then the value 3 in variable A in the processor (the value derived from the memory) is replaced by the designated value, 7 in this example.

This requires the player to complete 7 instead of 3 laps, thereby increasing the difficulty of the game.

Clearly, these examples are merely illustrative of the many different modifications that can be effected using the interfacing device of the invention.

The examples given effect a change of a single byte in a data table so as to change selected game variables such as screen color, sound volume, number of players, number of laps, time intervals, etc.

However, changes can alternatively, or additionally, be made to the instructions themselves, e. g. to change an instruction to increase a value to an instruction, to decrease a value, to change an instruction to perform a particular task to one that requires no action, to change a branch instruction (BEQ to BNE, say), and so on.

Although the described embodiments enable recognition of a single address and substitution of data corresponding thereto, the invention also embraces recognition of two or more different addresses and substitution of the respective data corresponding thereto.

Also, although the specific embodiments relate to a detachable interfacing device, the device can alternatively be incorporated into the processing sunit as an integral part thereof.

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