Self-synchronising descrambler

--1- A SELF-SYNCHRONISING DESCRAMBLER The invention relates to a self-synchronising descrambler.

In digital signal transmission, pulse patterns can occur which exhibit a distorting d.c. component or whose energy component is particularly high at specific discrete frequencies.

In order to avoid these pulse patterns, the digital signal which is to be transmitted is scrambled at the transmitting end by modulo-2-addition with a pseudo-random sequence.

At the receiving end, descrambling is effected by a further modulo-2-addition with the pseudo-random sequence already used at the transmitting end.

The necessary synchronisation of the pseudorandom generators used at the transmitting and receiving ends can be avoided by the use of free-running, so-called multiplicative or self-synchronising scramblers and descramblers.

The continued development of digital telecommunications networks has necessitated, between central points of such a network, transmission devices for signals with a very high transmission speed.

This results in the ';

-2~ need to construct scramblers and descramblers for digital signals with a very high clock pulse frequency.

In Siemens Research and Development Reports, Vol. 6 (1977) No. 1, pages 1 to 5, there has already been disclosed the possibility of constructing descramblers for digital signals with a high clock pulse frequency.

The digital signals are scrambled in a plurality of parallel channels each with a correspondingly reduced bit repetition frequency, and the signals which are formed are combined by multiplexers.

The receiving end is of similar construction, where following a demultiplexer, parallel descrambling in a plurality of channels takes place.

In addition to the high outlay, this results in the necessity to synchronise multiplexer and demultiplexer with one another.

The postal authorities have standardised scrambling for the individual hierarchy stages of a digital long range network.

Thus for example, in the CCITT recommendations under V27b the international postal authorities have prescribed a scrambler having a scrambler period of 127 bits, and a corresponding descrambler.

It is an aim of the present invention to provide a self-synchronising descrambler which is suitable for transmitting digital signals of a high bit repetition frequency and which, for a comparatively low outlay, can dispense with a demultiplexer, and whose period can be selected to be independent of the operating speed, and where it is also to be possible to suppress undesirable ~3~ 20365-2506 short periods for a tolerable outlay.

Accordlng to this invention, there is provided a selfsynehronising descrambler comprising n cloeked shift register stages for descrambling a signal having a period of 2n 1 bits with p descrambler stages each of which is connected to one of p parallel inputs and having p parallel outputs and contains a series connection of two modulo-2 adders as well as shift register stages, whereby the p parallel inputs for respectively one of said p parallel bits of the signal to be descrambled are ordered aecord ing to the sequenee of the incoming bits and are respectively connected to the input of a shift register stage and to the input of that modulo-2 adder whose output represents the output of a descrambler stage characterized in that the individual deserambler stages eomprise not more than two elocked shift register stages; in that the plurality p of parallel inputs is at least one less than the number n of the clock pulse eontrolled shift register stages contained in the descrambler stages, that considered in the direetion of shift n-p descrambler stages each having two clock pulse eontrolled shift register stages are followed by 2 p-n deserambler stages eaeh having only one eloek pulse eontrolled shift register stage, the deserambler stages eontain a first and a seeond modulo-2-adder, the output of the first modulo-2adder is eonneeted to the first input of the second modulo-2-adder whose other input is connected to one of the p parallel inputs for the signal whieh is to be descrambled, and the descrambled signal can be obtained from the output of the second modulo-2-adder, -4- 20365-2506 the input for the scrambled signal is also connected to the input of a first clock pulse controlled shift register stage at whose output can be obtained the scrambled digital signal (Ds x P) delayed by one clock pulse period, and is further connected to the input of a further clock pulse controlled shift register stage whose clock pulse input is connected in parallel wlth the clock pulse input of the first shift register stage and at whose output there can be obtained a scrambled, digital signal (Ds x 2 delayed by two clock pulse periods, the clock pulse frequency of the clock pulse signal (T) which is supplied to the shift register stages corresponds to the clock frequency of the digital signals which are to be descrambled, divided by the number p of the descrambler stages, and that the first input of the first modulo-2-adder is connected to the output of a descrambler stage in which the n-th preceding bit of the descrambled digital signal occurs, and the other input of the first modulo-2-adder is connected to a descrambler stage in which the m-th, preceding bit of the scrambled digital signal occurs, and my n and and n are each whole numbers.

Embodiments of this invention will now be described, by way of example, with reference to the accompanying drawings in which: --5 Fig. 1 is a schematic block circuit diagram of an individual descrambler stage embodying this invention;

Fig. 2 is a block circuit diagram of a first form of descrambler having four parallel descrambler stages and embodying this invention;

Figs. 3a and 3b are block circuit diagrams of respective portions of a descramber having five parallel descrambler stages and embodying this invention.

The stage shown in Fig. 1 forms part of an n shift register stage descrambler (Fig. 2) which comprises p descrambler stages for the descrambling of p bits in parallel of a digital signal where pun.

The descrambler stage includes a first and second modulo-2-adder Al,A2 and first and second shift register stages SRl,SR2 (the latter stage SR2 may be emitted).

The descrambler stage serves to descramble the x-th bit (Ds x) of the digital signal Ds so that output signal of the descrambler stage can be obtained from the output Do of the second modulo2-adder A2.

One clock period later, a scrambled bit Ds x P is emitted from the output of the first shift register stage SRl, and a corresponding scrambled bit Ds x 2p is emitted one further clock period later (relative to the bit Ds x P) from the output of the second shift register stage SR2.

Thus, in relation to the signal Ds, the first - 25 shift register stage SRl corresponds to the p-th shift register stage of the overall descrambler~ --6- Each descrambler stage has two inputs arranged for receiving respective output signals from outputC of the last preceding and penultimate preceding (relative to the direction of shift) shift register stages respec S tively and the arrangement is cyclic.

Thus, where x =p, the relevant descrambler stage has inputs arranged for receiving respective output signals Ds x n, Ds x m of the n-th and m-th shift register stages (m being less than n).

Both the inputs are the inputs of the first modulo-2-adder Al, whose output is connected to a first input of the second modulo-2-adder A2 whose other input is connected to an input for the received signal Ds which is to be descrambled in this stage.

The output Do of the second modulo-2-adder A2 provides an output terminal for the output signal of this descrambler stage.

Input Ds is arranged to provide signal Ds x and is connected to the input of the first shift register stage SRl which, in the same way as the second shift register stage, consists of a clock-pulse-controlled D-flip-flop, and whose output is connected to the D-input of the second shift register stage SR2.

The clock (T) frequency of the shift register stages here corresponds to the parallel~bit-clock rate, thus to the bit clock rate of the serial digital signal, divided by the number p of parallel inputs of the descrambler.

In a known self-synchronising, serial descrambler, it i5 known to connect the outputs of the m-th and n-th --7- shift register stagPs via at least one modulo-2-adder to the input of the first shift register stages.

In the embodiments of descramblers described below, the descrambler stages are arranged in parallel with either one or two shift register stages, where each of the p descrambler stages has one respective input at its disposal, connected for example to a respective one of the parallel outputs of a series-parallel converter acting as source of the digital signal having p parallel bits.

In order to construct a descrambler having n shift register stages, n-p descrambler stages each having two shift register stages, and 2p-n descrambler stages each having one shift register stage are required.

Considered in the direction of shift, the n-p descrambler stages each having two shift register stages, are followed by the 2p-n descrambler stages each having only one shift register stage. where the direction of shift is from left to right, the first preceding descrambler stage to the left of the descrambler stage already under consideration (with outputs Ds x, Ds x P, DS x 2p) then has the output signals Ds x 1, DS x 1 P and DS x 1 p, where the descrambler stage has two shift register stages, and correspondingly the first following descrambler stage on the right of the descrambler stage under consideration has the output signals Ds x 1, Ds x 1 P and Ds x 1 2p Similarly, the second descrambler stage on the left of a stage under consideration has the output signals Ds -8 x 2 Ds x 2 P and Ds x 2 2p whereas the second descrambler stage on the right of the stage under consideration has the output signals Ds x ,Ds x P and Ds x P.

In Fig. 2 there is shown a descrambler formed by the interconnection of four of the descrambler stages shown in Fig. 1, the descrambler comprising seven shift register stages with feedbacks from the sixth and seventh shift register stages and with four parallel inputs at its disposal.

Thus in accordance with the considerations outlined above p = 4, n = 7 and m = 6, where there are four parallel inputs for signals Ds and four parallel outputs for signals Do.

Thus for serial transmission the descrambler is to be preceded by a four-stage seriesparallel converter and is to be followed by a four-stage p æallel-series converter.

Using appropriate storage properties of the converters, the series-parallel conversions and parallel-series conversions need not take place in bit-synchronous fashion, and neither is word synchronisation necessary between the transmitting-end descrambler and the receiving-end descrambler.

The descrambler shown in Fig. 2 has four descrambler stages ESl to ES4 which have inputs Dsl to Ds4 respectively for the parallel reception of four bits of the digital signal which is to be scrambled, and respective outputs Dol to Do4.

With a total of n = 7 shift register stages, a period of 2 -1 = 127 bits results.

In accordance with the above-described rule, considered in the direction _ 9 _ of shift n - p = 3 descrambler stages having two shift registers are followed by 2p - n = 1 descrambler stage having only one shift register stage, and consequently the first descrambler stage ESl from the right has only one shift register stage SRl.

Accordingly the other descrambler stages ES2, ES3, ES4 each have two shift register stages SR2.1, SR2.2, SR3.1, SR4.1, SR4.2 which, in accordance with Fig. 1 are connected to each other and to the relevant descrambler stage input and are also connected to a common clock pulse source T.

The second inputs of the first modulo-2-adders A1.1, A2.1, A3.1 of the first to the third descrambler stages are each connected to the output of the second shift register stage of the preceding descrambler stage, thus respectively to the shift register stages SR2.2, SR3.2, SR4.2.

The corresponding input of the first modulo-2-adder A4.1 of the fourth descrambler stage ES4 is connected to the output of the only shift register stage SR1 of the first descrambler stage ESl.

The first inputs of the first modulo-2-adders Al.l, A2.1 of the first and second descrambler stages ESl, ES2 are respectively connected to the autputs of the second shift register stage SR3.2, SR4.2 of the respective second preceding descrambler stages ES3, ES4.

Thus the first input of the modulo-2-adder Al.1 is connected to the output of the shift register stage SR3.2, whereas the first input of the modulo-2-adder A2.L is connected -10 to the output of the shift register stage SR4.2.

A difference exists in respect of the third and fourth descrambler stages ES3, ES4 since, in accordance with cyclic arrangement of the descrambler stages, the two first inputs of the first modulo-2-adders A3.1, A4.1 are connected to one another and to the output of the only shift register stage SRl of the first descrambler stage.

The descrambled signal is derived from the input signal Ds x for the relevant stage and from the output signals from the last preceding and penultimate preceding descrambler stages, i.e. the signals Ds x 6 and Ds x where x = 4) from the sixth and seventh shift register stages on the right-hand side of the descrambler under consideration.

In known descramblers, in dependence upon the input signal pattern it is possible that in the case of specific input signal patterns specific states of the descrambler period can be skipped and that periodic output signal sequences of comparatively short duration can occur.

For this reason, descramblers used in practice additionally include further shift register stages.

For example, the CCITT recommendations V27 and V27b describe a 7-stage scrambler and a corrsponding descrambler which, in order to avoid short periods, are supplemented by a further five shift register stages to make a total of 12 shift register stages.

In the case of a descrambler corresponding to recommendation V27b, the contents of shift register stages 8,9 and 12 are then compared with the logic state prevailing at the input of the shift register chain.

If one of the compared pairs continuously exhibits identical states for a period of at least 33 bits, the next input bit is inverted so that shorter period output signal sequences of 1,2,3,4,6,8,9 and 12 bit period duration are suppressed.

Thus, with the described additional outlay, it is not possible, for example, to suppress periodic output signal sequencies 10 of 5,7,10 and 11 bit periodic duration, and the additional suppression of these short periods would require a further increase in outlay so that the development of descramblers of this type necessitates an application-related compromise.

This compromise is also necessary in respect of the use of the descramblers at higher transmission speeds since the lengthening of the shift register chains limits the possibilities of use at higher transmission speeds.

In the case of the parallel descramblers shown in Fig. 2 and also in the case of other descramblers which use the descrambler stage shown in Fig. 1 in parallel operation, it is necessary to monitor all the descrambler stages by means for short period suppression in order to establish and terminate the occurrence of short periods, if the descrambler is to be compatible with known series descramblers which include the shift register stages in a series arrangement.

d.

-12 The suppression of undesirable short periods is fundamentally carried out by means of a counting device, connected to the actual descrambler, for counting indèntical bits which occur at intervals corresponding to a short period which is to be suppressed.

When a preset number of identical bits is exceeded, the counting device emits a pulse which is forwarded to the descrambl0r stages.

the counting device thus forms the main component of the short period suppression means and in order that the de scrambler stages may be connected to the counting device,the descrambler stages, as shown in Figs. 3a and 3b, are supplemented by one further modulo-2-adder 5~,44,34,24,14.

This adder is interposed between the first and second modulo-2-adders Al,A2 shown in Fig. l in such manner that the first input of the third modulo-2-adder (e.g. 54) is connected to the output of the first modulo-2-adder (e.g. 55), that the second input of the third modulo2-adder is connected to an assigned output of the short period suppression means, and that the output of the third modulo-2-adder is connected to that input of the second modulo-2-adder (e.g. 53) which has been previously connected to the output of the first modulo-2-adder (e.g. 55).

In Figs. 3a and 3b there is shown a descrambler consisting of five descrambler stages El to E5 which has been extended in this way, where the left-hand side of the arrangement comprising scrambler stages E3,E4,ES has been shown in Fig. 3a and the right-hand side comprising -13- ~?~ the scrambler stages El,E2 has been shown in Fig. 3b.

The two circuit portions have a common boundary indicated by lines Sl,S2 in Figs. 3a,3b respectively.

The descrambler shown in Figs. 3a,3b has five parallel inputs so that p = 5, and in order to produce a shift period of 27-1 = 127 bits, n s 7 shift register stages have been used, where feedback takes place following the m = 6th and n = 7th stages.

Therefore in accordance with the already described rule, there are basically provided n - p = 7 - 5 = 2 descrambler stages E5 and E4 each having two shift register stages Sl,S2 and 41,42 which are connected to 2p-n = 10-7 = 3 descrambler stages E3,E2,El each having one shift register stage 32,22,12.

Conse$uently, further shift register stages 31,21,11 which are additionally provided in the descrambler stages El,E2,E3 are not essen tial to the function of the descrambler but form part of the short period suppression means.

The latter includes five groups each consisting of three modulo-2-adders whose outputs are combined via 20 a respective NAND-gate 114,214,314,414,514.

Each of these three-member groups is assigned to a descrambler stage, where the first inputs of each of the modu~o-2-adders 111,112,113;211,212,213;311,312,313;

411,412,413;511,512,513 are connected to one another and to the D-input of the first shift register stage of the assigned descrambler stage. -14 The second inputs of the modulo-2-adders of the five groups are connected to the outputs of the individual shift register stages in such manner that in each three-member group the bit occurring at the input of the first shift register stage of a descrambler stage is compared with the 8th,9th and 12th stored bits.

As the descrambler stages contain a total of only 10 shift register stages and thus only 10 bits can be stored, D-flip-flops 118 and 218 (Fig. 3b) have been additionally provided, where said D-flip-flops are connected prior to the second inputs of the first modulo-2-adders 113,213 of the first and second three-member groups, are connected to the same clock pulse source T as the shift register stages of the descrambler stages, and their D-inputs are connected to the outputs of the second shift register stages of the fourth and fifth descrambler stages.

When the bit occurring at the input of the first shift register stage of a k-th descrambler stage is identical to one of the stored bits ~,9 and 12, the logic l-level occurs at the output of the corresponding k-th NAN~-gate 114,214,314,414,514 and is emitted via an inverting input to NAND-gate 60, so that the latter enables divider chain 61,62,63,64 via its inverting output.

The divider chain is connected via inverter 65 to the source for the word clock pulse train T of the digital signals and contains first and second dividers 61 and 62 having the divider ratio 2:1, and 2 subsequently connected JKflip-flops 63,64.

~2~ --15- The short period suppression means also contains five AND-gates 115,215,315,415,515 each having a first group of five inputs (which are respectively connected to the outputs of the NAND-gates 114,214,314,414,514) and a second group of four inputs.

Each of these four inputs of the second group is connected to the inverting output of one of D-flip-flops 116,216,316,~16,516 whose D-inputs are connected to the outputs of one of the nineinput AND-gates 115 to 515.

The inverting outputs of these D-flip-flops are each connected to an input of the gates whose gate output is not connected to the D-flip-flop.

The non-inverting outputs of the D-flip-flops are connected via a further AND-gate 117,217,317,417,517 to the second inputs of the third modulo-2-adders of the descrambler stages El to E5.

The second inputs of the AND-gates 117 to 517 in the third to the fifth descrambler stages E3to E5, are connected in common to the output of the JK-flip-flop 63 in the divider chain and which is followed by the JK-flip flop 64 whose output is connected to the second inputs of the AND-gates 117,217 which have their outputs connected into the first and second descra~bler stages El and E2.

The enabling of the divider chain 61 to 64 leads to the fact that via one of the enabled AND-gates 117,217, 317,417,517 and the additional third modulo-2-adder in one of the descrambler stages El to E5, one bit is inverted and thus an occurring short period is ended.

From the -16 very first recognition of the pulse pattern corresponding to a short period, the periodicity for each following bit is recognised for such time as the input pattern is retained, and thus at the latest following one parallel 5 clock pulse period of five bits, all the NAND-gates 114,214, 314,414,514 carry the logic level 1.

The AND-gates 115, 215,315,415,515 together with the following D-flip-flops 116,216,316,416,516, now serve to store the information as to that bit which was present at the input of the first shift register of a descrambler stage on the first occasion when a short period was recognised.

The change in the logic value of a bit occurring at the input of a shift register stage of a descrambler stage does not take place directly following the first recognition of the short period criterion.In the present example the outputs of the gates 114,214,314,414,514 have been assigned to the inputs of the AND-gates 115,215, 315,415,515 in such manner that only the 33rd bit following the first recognition is inverted.

If, in the present example, the first recognition takes place, for example, in that the output of the NANDgate 114, which is assigned to the first descrambler stage, assumes the logic value 1, then following 6 x 5 = 30 bit timing periods, one bit is inverted via the AND-gate 315 assigned to the third descrambler stageO the following D-flip-flop 316, and the connected AND-gate 317 in the third modulo-2-adder 34 of the third descrambler stage E3.

-17~ a The inputs of the NAND-gate 60 can be connected to the non-inverting outputs of the D-flip-flops 116 to 516 instead of the outputs of the ~AND-gates 114 to 514.

In this case, as a result of the additional divider effect S of these D-flip-flops, the divider ratio of the frequency divider 61 is to be reduced from 5:1 to 4:1, resulting in a suppression of undesired pulse peaks on the connection line between the output of the NAND-gate 60 and the reset inputs of the divider stages 61 and 62.

Thus the embodiments described above provide a self-synchronising descrambler having n clock pulse controlled shift register stages for the production of a signal with a period of 2 -1 bits, where the output of at least one of the shift register stages is connected to the input of a modulo-2-adder, p parallel inputs being respectively provided to p descrambler stages for p parallel bits of each sequence of a scrambled digital signal which is to be descrambled, the inputs being sequentially arranged for receiving the incoming bits in accordance with said sequence, with the first input relative to the direction of shift being arranged for receiving the p-th bit and the subsequent inputs for receiving the bits p-l to 1 respectively, each descrambler stage including at least one shift register s~ase and at least one ~odulo 2-adder, the number p of the parallel inputs being at least one smaller than the number n, the descrambler stages being arranged so that, considered in the direction , -18 of shift, n - p descrambler stages each having at least two clock pulse controlled shift register stages are followed by 2p - n descrambler stages each having at least one clock pulse controlled shift register stage, the S descrambler stages each including a first and a second modulo-2-adder, where the output of the first modulo-2adder is connected to a first input of the second modulo2-adder which has a second input connected to a respective one of the p parallel inputs for the scrambled signal which is to be descrambled, an output for the descrambled signal being provided by the output of the second modulo-2adder, the relevant input of the descrambler stage being connected to the input of a first clock-pulse controlled shift register stage whose output is arranged for supplying the scrambled digital signal delayed by one clock pulse period, and further being connected to the input of a further clock pulse controlled shift register stage whose clock pulse input is connected in parallel with the clock pulse input of the first shift register stage and at whose output there can be obtained a scrambled, digital signal delayed by two clock pulse periods, the clock pulse freguency of the clock pulse signal which is supplied to the shift register stages being arranged to correspond to the bit frequency of the digital signal which is to be descrambled, divided by the number p of the descrambler stages, and in each descrambler stage one input of the first modulo-2-adder being connected to a descrambler --19- stage in which the j-th preceding bit of the descrambled digital signal occurs, the other input of the first modulo2-adder being connected to a descrambler stage in which the k-th, preceding bit of the descrambled digital signal occurs, and that k~j~p.

A particularly advantageous feature of the embodiments described above results from their construction from purely digital components which considerably simplifies integration and which is readily accessible even in the case of longer period scramblers.