Wide band integrated services local communication system

~23~ -- 2 - The present invention concerns integrated services telecommunications networks and more particularly a local-area wideband integrated services comunicatioD system.

The term "local" means that the system is to interconnect users distributed over distances varying from some hundred meters to some ten hm5.

Local area networks were originally intended to ~nterconnect the computing resources in a firm ~local compu~er networ~s) and they have afterwords been adapted to allow voice transmission in addition to data transmission.

Nowadays local area networks are rapidly evolving as there is a trend towards an in~egration of all communications services in a : ':

~ 3 - ~ ~371 firm lnto a single network.

The resultlng network mu~t accomodate not only convenClonal volce and data services, but also new servlceg such as high resolution graphics servlces for CAD (computer-alded deslgn) or CAM (comptlter aided manufacturlng) applications,video conferencing, remote control of manufacturing, high resolution video broadcasting.

Local networks ought to have very high capacity of the order of some hundreds Mbit/s or even of the Gbit/s to be able to handle the traffic orlginated by a very high number of sources (some thousands);

besides, source requirements may be very different as to:

- transmission rate (and consequently band occupation) which may range from some kbit/s (speech services) to several Mbit/s (graphic or video services) and may be variable for a given service;

- max~mum acceptable delay ranging from few ms (services requiring real-time infor~ation processing, such as graphics facilities or remote control of manufacturing) to some hours (e.g. data files transfer, electronic mail, etc.);

- error rate;

- amount of traffic originated by the individual sources;

- switching modalities: circuit switching for communications with continuity and/or synchronism characteristics or packet switchig for the other communications.

As teleco~munications, and re particularly office automation are growing quickly, a local communication system ought to adapt itself easily to variations in the offered Eacilities 7 and to grow as the user requirements increase.

Besides, these systems are generally private systems and their connections to the future integrated services public network ought to be simple and cost-effective.

Integrated services networks are known in which processing requirements of information originated by very different sources are met by organizing the network activity into repetitive frames, compo ,, ~23~7~ -- 4 - sed of two region~ asslgned to circuit-~wltched communlcatlons (baslcally tlme dlvlslon multlplexed, ~o chat e~ch 18 allotted ~ tlme interval or channel of duration proportional to the transmi36ion r~te) and to packet switched communicatlons respectively.

These frames are generally referred to as hybrid frames.

An example is described ln Canadian Patent Application #429,916 filed on 8th June 1983, in the name of the Appllcant, which discloses a distributed variable-band switching syste~ ~or speech and data intended for a topology with "islands" with high terminal concentration connected to a unidirectional folded bus.

In this system a dlstributed bus access management is disclosed such that, for data communications ehe bus capacity is shared among the various islands according to an ordered-access protocol whereas the activity of the ter minals inside an island can be controlled by a random-access protocol.

communication~, For synchronous / constant-duration channels are provided which occur periodically for the whole call duration.

The solution described in the above-mentioned Patent Application is mainly studied for conventional low-rate speech /data services and hence cannot be satisfactorily used for the new applications: in effect contention accesses and collision possibility cause very low efficiency, taking into account the high transmission rates envisaged.

In addition, the known system reguires memorization of the activity on the bus on a frame-by-frame basis and therefore it does not allow dynamic management of services whose band requirements vary during the connection (e.g. TASI or DSI systems, variable bit-rate coding) or, in general, dynamic frame management.

An example of a system wi~h dynamic hybrid frame management is described in the papsr entitled: "A hybrid ~witching system with variable bit rate" by G.Fioretto, L.Gabrielli, N.Lotito, M.Sposini, CSELT Rapporti Tecnici, vol. XII, No. I, Februarv 1984, pages 63-73.

The solution proposed in this paper is sa~isfactory for a switching node, but cannot be used for a local area network for con ..~ ~.Z371~7 5 .

structive reasons and owing to Erame manflgement modalities~ In factthe node comprises a plurnllty of modules interconnected by a parallel bufi, which cfln be usefully used over short dlstances (some tens meters), and not over diseances of some hundreds ~eters or of kilometers as can be necessary in a local networki in fact ~or these distances a parallel bus has high installation costs and, taking into account high eransmission rates, presents risks of different transmission delays on the different wlres.

BesidesJframe control is completely distributed, i.e. the generation of the "start of ~rame" and "region boundary" flags is allotted frame by frame to the module processing the first and the last channel of the circuit region, respectively: this entails a considerable efficiency limitation, as, owing to the long dlstances considered~ the propagation delays of such signals and hence the waiting times necessary for a module to recognize whether or not it is entrusted with the emission become very long.

The efficiency is further limited by pauses between adjacent channels which over the above distances have durations equal to or longer than channel durations, and by the possibility of packet collisions.

Finally, the dynamic speech circuit management requires sending additional signalling with consequently increased circuitry complexity.

These disadvantages are overcome, within a wide-band local network, by a system where an actual services integration is achieved with high efficiency owing to an ordered-access protocol which is based on the source location, which is implemented in distributed manner and which esta~lishes at each instant the source enabled to ~ransmission, and owing to frame signal management, which is at least partly centralized or, if is not centralized, is allotted to a single unit in a frame.

~7~L~ - 5a ~ ccording to the invention there is providecl a wide band integrated communication system ~or the transmission o~ both packet switched and circuit switched data comprising a unidirectional communications transmission line on which data is organized into hybrid frames each comprising a circuit region allotted to circuit switched data and a circuit region allotted to packet switched data; a plurality of communication units, each in transmitting and receiving communication with one or more stations, and each being distributed along the unidirectional transmission line with transmission means thereto, receiving means therefrom and detection means to detect activity o~ communication units upstream on said line, said units being arranged so that data transmitted by one unit is available to all the other units; means controlling access of the units to the line for data transmission and reception on the basis of existing line activity, whereby for each frame region the communication units have access to said line in turn in separate rounds for each type o~ frame region, beginning from the most upstream unit, each unit having access to the circuit region of a single frame during a round for the transmission of circuit switchecl data, whilst the data from a round may ~e distributed over the packet regions of one or more frames for the transmission o~ packet switched data; a frame signal generator to send a start-of-frame signal to the line; mean to control the active p~riod within the circuit region of each first communication unit to a duration varying from frame to ~rame in dependence 3~ upon demand, each active period being shared among the stations associated with the communication units; and means to provide an inactive period before each active period and an additional predetermined guard inactive period indicative o~ inactivity by any first communication unit during its turn.

~Z3~7 - 5b Embodiments of the invention wil:L now be described by way of example with referencQ to the accompanying drawings, in which:

Figures 1 and 2 are samples of schematics of communication .....

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7~7 -- 6 - systems accordlng to the Inventlon i~ case of use of passive components;

- Figure 3 is a block dlagram of one of the communication unlts -Ln the system;

- Figure 4 is another exemplary system according to the invention in which active components are used;

- Figure 5 is a6 sch6ematic representation of a multilevel system;

- Figures 6,/ 7 show an example of information organization for the system of Figures 1 and 2;

- Fig. 8 is a block diagram of frame signal generator;

- Fig. 9 is a diagram of the operations of one of the circuits of the generator of Fig. 8;

- Fig. lO is a more detailed block diagra~ of logic network managing the access protocol in a unit;

- Figures ll to 16 are circuit diagrams of some blocks of Fig. 10;

- Fig. 17 is a flo~ chart of the operations of a further block of Fig. lO.

In Figures 1, 2 and 4 an integrated services local communica tion system comprises at least one wide-band unidirectional bus l, advantageously consisting of an optical fibre, along which devices ~CVl ....NCUi....NCUj....NCUn,hereinafter referred to as network communication units" are located.

One of these units, e.g. NCUj, is connected to a so-called network control center NCC, carrying out the functions which ought to be centralised (e.g. storage of tariffs, storage of the associations between subscribers and units NCU, etc.). A plurality of stations Sl(Sl-1....Sl-h), Si(Si-1....Si-k), Sn(Sn-l....Sn-m) corresponding to one or more ter~inals for the different services the network can offer, are connected to the other units NCU.

Units NCU are to control in distributed manner the bus access protocol and to organize the infor~ation emitted by the source~ into constant-durat~on hybrid frames, i.e. frames subdivided into two regions, one allotted to circuit switched communication and the other to packet switched commu .

~Lf~3~ , nlcatlons, the lnformation will be transmitted on the bus wlCh a'suttable modulatlon.

Access protocol characteristics nnd frame organization will be described hereinafter.

The bus is further connected to a device FG which generates and sends all the units at least some of the signallings necessary to communication handling, in particular at least a "Start-of-frame" flag SF.

In the scheme of Figs. 1 and 2 there Ls a single bus 1 with a writing branchlW and a reading branch lR, obtained by folding the bus at one end (Fig. 7) or by a double folding (Fig. 2).

In the latter case a "transport braneh" conneets writing branch IW and reading branch lR.

Units NCU are eonnected to the bus by passive couplers, i.e.

no regenerator i5 provided in correspondenee with the units.

In this case the signals generated by FG can consists of bursts of unmodulated carrier of different durations.

The bloek diagram of one of the units NCU, in case of the network structure shown in Figures 1 or 2 and of a passive optical fibre bus, is represented in Fi8. 3.

The unit co~prises a first part ~AU for conneceion to the bus, another part ACM managing the access and storing packet-switched and circuit-switched informaion flows, a further part PH handling the packet flow (packet-switched traffic and signalling which is transmitted in packet form), and finally an interface AIH towards the stations, which separates or recombines both kinds of traffic.

The information flow path 'has been sehe~atised by double-line arrows, and local signalling path by single-line arrows.

~ A~ comprises emitter TX for transmitting on the bus the information originated in the stations connected to the unit, and two receivers ~Yl, RY2; the first receiver is connected to wri~ing branch 1~ to detect the activity of ~he upstream units and the second is con nected to reading branch lR to extract the information addressed to the stations connected to the unit. .~W, AS, AR denote the couplers for ,, ~237~ - 8 TX, RXl, RX2; lt ls to be noted that AS i~ placed up~trea~ o~ AW, to prevent a unit from detecting lt~ own activlty.

Transmitter TX and the receivers are connected to an electrical interface IE, connected in turn to ACM. ACM comprises access protocol managing devices APH and storlng system ME which recelves from AIH the circuit-switched information flows and from PH packet-switched traffic. ACM will be shown Ln greater details in Fig. 10.

According to whether bus 1 presents two folding points or only one,units NCU transmit and receive in the same order or in inverse order~ That obviously implies variations in access modalities and in signals FG is to generate, as will be better seen hereinafter.

Topologies similar to those of Figures 1 and 2 can also be used in case signal regeneration takes place in correspondence with units NCU.

In this case the units are connected by a receiver and a transmitter to both the writing and the reading branches of the bus and devices are provided to insulate From the bus a NCU in case of ~ailure.

The remaining structure of ~CU is identical to that of Fig.

3.

A double ring structure like that of Fig. 4 is also possible, in which transmission occurs in opposite directions on the two rings.

Vnits NCUl....~CUn are connected point-to-point by two lines lA, 18 beginning and ending in correspondence with the two generators FGA, FGB.

In each line the trunk upstream of a station (or of a generator) forms the reading branch, the one downstream the writing branch.

In correspondence with the different units, the buses enter a receiver and exit fro~ a transmitter; the units transmit on one or the other of the two buses, according to whether the destination unit is more upstream or ~ore downstream with respect to one of the generators FGA, FGB.

This structure basically allows a double network capacity, but entails the duplication of devices MAU, APH and the necessity for each station to '~now the mutual position of the others.

Obviously it is to be predetermined which of the two buses is to be used in case of ~23~ _ 9 _ lnformation intended for ano~her station connected to the same unit ~CU .

From what already mentioned Lt derives that, whatever the scheme adopted, units NCU are arranged In ordered sequence along the bus, for both transmission and reception. That immedlately suggests the choice of an ordered protocol, in particular a Round Robin protocol.

Here, a number of "rounds" are establishedandin every "round the units having information to be transmitted are allowed to Lntevene at least once but only once; the unit more distant from the bus Eolding point, i.e. the unit farthest upstreaml can intervene First and the other stations can follo~ in downstream succession. Once the most dowstream unit has completed transmission, a new round can begin.

This protocol is very efficient and is not critically dependent on the network size and hence on the propagation time.

Moreover it limits the transmission delay of a packet (sum of the bus access time, the transmission time and the propagation time) to a maximum predeter~ined value.

In opposition to what descrlbed in the above clted Patent Application No. ~29,~16, where the ordered access protocol concerned only data (asynchronous~ communications, in the present system the access in rounds concerns both circuit-switched and packet-switched communications; in this way a better services integration is obtained and the structure of the communication control devices is highly simplified.

As to circuit-switched communications the frame will contain just one round during which each unit occupied a channel which is allo~ted the band actually required in ~hat frame by the information to be transmitted (circuit region); for packet-switched communications, a frame ~ill comprise a variable and even non-integer number of rounds and the rounds possibly interrupted by the beginning of the circuit region of a new frame are resumed in the subsequent frame from the interruption point.

Besides, to increase the system efficiency, the protocol ~37~1~ -- ~o establishes at each lnstant whlch station ls to access the bus, ln order to avold colllstons; to thls alm unlts NCU are numbered in the same order as that used to schedule thelr access to the ~8 for transmission and each unlt, knowing its serial number, ~tarts transmittirl~ only after recognizlng the transmisslon end or the absence of transmisslon by the preceding unit.

By a communication management of this kind, signals are to be provided indicating the start of frame (SF), the region boundary (RB) and the start of packe~ rounds (SR), as well as guard times to ~ecognize the inactivity phases.

Signal SF is always emitted by generator FG (or FGA, FGB) whatever the topology adopted.

In case of Figures 1 and 4, devlces FG, FGA, FGB are to generate also signals RB and SR, and hence they are connected to writing and reading branches of the bus.

The connection to reading branch is necessary because only by surveying the activity on such a branch, generator FG (FGA, FGB) can recognize the instants at which to emit signals RB, SR.

As to FG it ls connected to the two branches upstream (for writlng) and downstream of NCUl (for reading) through lines 3~, 3R respectively.

In case of Fig. 2, units ~CU can be entrusted with generation of RB, SR.

This clearly entails a simplified structure of FG, which merely becomes a clock generator, since the frames are constant. In this case FG can be connected only to the writing branch.

If RB or SR are generated by FG, FG is connected to both the writing and the reading branch upstream of NCl, as shown in Fig. 2.

However, even in case of a centralized generation of RB and SR, the seructure of FG is quite simple, as shown, so that it can be easily duplicated to avoid reliability problems.

Beyond a certain number of stations, and hence of units connected to the system (e.g. 500-1000 stations) problems arise to assure the access to all the stations while keeping the losses within the limits admitted for the service, as well as reliability problems.

Hence ;

~;237~7 lt becomes convenlent to lneerconnect a plurallty of networks as those described with reference to Figures 1, 2 and 4 so as to obtain a hlerarchic structure with a plurality of low-level networks (collecting networks) and a high level network (or connection network).

The hierarchic structure 18 also convenient to a modular growth for future expansions, and is in particular convenient when the distances among the users are high or when ehe users are dispersed in a plurality of buildings.

An example~hlerarchic structure is shown in Fig. S, supposing that the connection network C is of the double-ring type and is connected to two collecting networks Rl, R2 of the type shown in Fig.2 and Fig. 1 respectively.

One of the collecting networks, e.g.

Rl, is in addition connected to the public network through an interface GTW.

The individual networks are connected as already described iD Figures 1 to 4, the only difference being that certain units ~CU (e.g. NCU3 and NCUn) of the connection network are connected through "bridges" Bl, B~ to a respective unit (NCUi-l, NCUn-2) of the collecting network.

The "bridges" are interfaces having essentially to synchronise the information outgoing from a network with the flows of the network into whlch ehis information is to be entered.

Of course, the Erames on dlfferent networks ought to have equal duration.

By a hierarchic system of this kind, the collecting networks are seen by the connection network as stations connected to units ~CU of ehe network itself; hence the information transferred from and/or to one of such networks are processed exactly alike the information transferred from and/or to a station within the network.

The system described is asynchronous, in case of a passivebus topology, or plesiochronous in case of active network, that is why units ~CU are to transmit on the bus the clock information in conjunceion with the data, i.e. a self-synchronising code is to be used. ~uring the transmission phase each unit will transmit ~ith the rate established by its clock generator ~even if nominally the transmission ~L237~7 - 12 rate i8 equal for all stations) and durlng the recelvlng pha~e each statlon will become synchronised with the clock signal assoclated with the received information flow.

In case of active networks as that of Fig. 4, where the transmission is carried out as point-to-point connections between successive units, each unit is to accomplish, when necessary, a "stuffing" to compensate for possible phase shifts between Its cloclc and that of the preceding unit.

Self-synchronising codes are well known. Considering as an example code CMI, bits 0 are coded by 01, and 00 and 11 alternate in coding bits l; the pair 10 in steady state is interdicted and is used, as will be seen hereinafter, for particular aims.

An example of organizatlon of the bus activity, and hence of round and frame organisation, is shown in ~F~gs. 6A,/for two subsequent frames whose circuit and packet regions are denoted by RCl, RC2, RPl, RP2; SFl, SF2, SF3, SR1, SR2, SR3 denote signals SF and SR relating to the different frames; RB denotes the Region Boundary; Ci, Pi (i = 1, 2..... n) denote the circuit and packet activity of unit ~CUi.

For the packet region, it has been supposed that the frame comprises a complete round and a portion of a second round.

The latter is interrupted by the arrival of signal SF2 of frame 2 during the activity of station NCUj, which could transmit just a portion Pj' of its information; therefore, in frame ~, af~er the arrival of signal RB, the activity ls resumed by sending on the line the remaining part Pj" of the information to be transmitted by NCUj; once completed the second round, a third round can begin (SR3) which in turn can terminate in frame 2 or be interrupted by signal SF3, and so on.

~ ere a passive network like that of Figures 1 and 2, has been considered under the hypothesis that the modulated carrier is always present during the whole station activity.

In this case frame signals SF, RB, SR can be represented by bursts of unmodulated carrier with different durations.

Frame development on the bus is followed by the ~37~ - 13 various units NCU thanks to such ~lgnals, to the beglnnlng and end of carrier and to sultable carrler latency tl~er~ More pnrttcularly, the beginning of the .3ctivity of the generlc 6tatlon NCUi ls separated ~rom the end of activity of station NCU (i-1) by a carrler latency time tal, which depends on the position of the unit with respect to the bus (i.e. on the lenght of branches 2R, 2S, 2W, Fig. 3) and which is given by the sum of propagation times on such branches and of the time necessary to logic circuits of the unit to recognize the end of carrier and the access right of the unit.

The lack of activity of a station is recognized because the carrier latency time exceeds che guard time Ta equal to the maximum of all times Tai.

For instance in case of transmission rate on the bus of 140 Mblt/s and of branches of the order of ten meters, at most the guardtimeTa i9 of the order of some tens of nanoseconds.

In Fig. 6 it has been supposed a lack of activlty of ~CU3 in the circuic region and of NCU2 in the packet region; activities C4, P3 wlll then begin after a time period Ta+Ta4 or Ta+Ta3, respectively, has elapsed after the end of activity of C2, Pl.

The "Start of Frame" flag SF ~ust be longer than guard time Ta to avoid overlapping between a packet being trasmitted and the beginning of circuit activity of the Eirst active unit.

The end of the circuit round, with consequent need to e~it RB, is recognized when the number of end-of-carrier signals and of intervals with duration Ta is equal to the number n of units NCU.

Between the end of a circuit round and the emiqsion of RB and between the end of a packet round and the emission of signal SR relating to the subsequent round there is a time of inactivity Tb due to propagation delay; such time is twice the propagation time on the writing branch in case of the topology (of Fig. 1, it is the sum of the propagation time on the writing and transport branches in case of Fig. 2, and is equal to the propagation time along one of the rings in the case of Fig. 4.

The end or the packet rounds is recognized like the end of the circuit round.

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~237~ - 14 Although in Flg. 6 also slgnals RB, SR have been represented, it i8 to be taken in mlnd that their expllclt transmi~aion i9 unnecessary in case o~ the system structure o~ Fig. 2, as the varlous units recognlze the events on the line ~n the same order Ln which they obtain the access right.

As to the organization of circuit activity of a unit, different aspects are to be taken Lnto account.

First, generally a plurality of stations are connected to unit N~V, and hence each activity period C comprises a plurality of circuits, which are llOt necessarily all actives in each ~rame.

Besides a number of circuits (more particularly those assigned to speech communications) can be dynamically managed, e.g. to take into account procedures like DSI, so that a circuit is assigned to a communication only when this one is active; other circuits on the contrary (data circuits, denoting by this term those relevant to non-speech services, i.e. graphics services, videoconferencing, etc.) require permanent allotment to che respective co~munication and are active for the whole duration thereof.

It is hence necessary not only to identify the various circuits in the same activity period, but also to make a distinction between active and non active circuits and between circuits with dynamic or rigid management.

For the identificat~on of ind~vidual circuits, each of them can be assigned a pair of numbers, one indicating the number o~ the unit and the other the circuit position inside the activity period.

These numbers will be communicated by the calling station to the called station upon establishment of the connection and are maintained for the whole duration of same, what allows in a very simple way a distributed management of circuit identiEication in receiving phase.

ceiving phase.

As to dynamically-controlled circuits, to ensure a service quality convenient to both speech and data circuit-switched communications, for speech communications a blocking strategy is adopted which, according to the invention, concentrates the losses on units ~CU with ~Læ3~ - 15 hlgher serlal nu~ber~ This simpllfies the ~ccess, in fact in each ErsAme it 18 sufflcient for an NCU to count the speech clrcults already exlsting and only if thelr number has not reached a predetermlned maxlmum number, a new speech circuit can be transmltted.

The counting i6 simplified by the use of an odd-even arrangement for both circuit types.

In the example of organisation depicted in Fig. 7, it is supposed that speech communlcations are assigned odd circuits and the others even circuits.

Such a Figure shows the case of a unlt handling seven circuits; circuits Vj (j-1,3,5,7) are assigned to speech communications, circuits Dk (k=2,4,6) are allotted to data communicatLons. SY denotes a synchronism word containing clock information and, as mentioned, has to be transmitted by each station.

With the above assumption that the modulated carrier is present for the whole duration of the activity of a station and that code CMI is used for transmission, out-of-code bit pair lO can be used to indicate both the end and the lack of an event during the activity of a unit.

The term event refers to both the synchronism word, and the information relating to a circuit.

Such bit pair ~ill be repeated a number of times (e.g. 4) for reliability reasons.

In the Figure the delimiting sequence is denoted by CD supposing that ~n the period represented circuits D2 and V5 are not active, two delimiting sequences will be transmitted between Vl and V3, and between D4 and D6 one sequence indicating the end of circuits Vl or D4 and the other the lack of V2 or D5, respectively.

Delimiting sequences CD are recognized by the decoder of devices MAU (Fig. 3) of the unit; by counting such sequences the station can immediately recognize when it has processed all communications.

The same organization can be used for packet activity with the only difference that all the packets emitted by a unit are grouped together; i.e. the lack of activity ls ~ot to be signalled.

In case of interruption due to the beginning of a frame, the station activity will be resumed by transmitting first the synchronism word and then ~Z37~L~ - 16 the packet possibly lnterrupted by the ~rrlv~l of S~.

In case of a network with regeneratlon, a~ a rule, the modulated carrler wlll be always present and frame ~ignals and lnactivlty times can be then represented by sultable bit conflgurations; ~ore particularly the lnactivlty times will be represented by synchronism information; in addition the beginning and the end of activity of a station are to be suitably encoded,.

Fig. 8 shows frame signal generator FG for a passive network, in the most general case in which all the signals are actually transmitted.

The generator comprises three circuits SFH, RBH, SR~ for processing "start of frame" signal SF "region boundary" signal RB and "start of packet round" signal SR; the last two circuits are connected to a circuit FRR for frame and round recognition.

All these circuits are connected to a device Fl, which has basically the same functions as block MAU in Fig. 3, except for the detection of the activity on writing channel.

Signals SF, RB, SR emltted by circuits of FG are then com~ands for suitable generators of unmodulated carrier present in Fl, which generators in turn will send on the bus the homonymous frame signals.

That stated, circuit SFH basically consists of a counter of the pulses of a clock signal CK, having a Erequency equal to the transmission rate on the line: SFH counts up to a pre-determined number corresponding to a Erame duration and, at the counting end, emits signal SF.

Detector FRR operates on the ground of the activity on the bus reading branch, and receives from Fl signals BUR, EVR indicating the beginning and the end of unmodulated carrier on such a branch, and clock signal CKS associated to data; FRR generates a signal SFR indi caCing the beginning of a frame on the reading branch (signal ~hich issent eO both ~BH and SRH), and signals RBR, SRR indicating the region boundary and the beginning of a pacXet round on said branch: both these signals are supplied to SHR.

Detector FRR can be a counting system ~'~3'7~ - 17 counting the pulses of CKS occurring between BUR and FUR and emlts s1gnal SFR or RBR or SRR when the number of pulses recelved reaches one of three predetermined values correspondlng to the duratlon~ of the three frame slgnals.

Clrcuit RBH is to generate signal RB at the end of the circuit region.

It exploits start of ~rame signal SFR, supplied by FRR, and slgna~ BAR, EAR supplled by Fl and indlcating the beglnnlng and end of clrcult actlvity of a unit NCU; as said, circuit region end i9 detected when the number of actlve unlts NCU, added to the number of time in which guard time Ta is reached, is equal to number n of the units asociated with the system.

Thus RBH can be a counter which is reset at each frame and is advanced by one step either by the pa1r of signals BAR, EAR or by a slgnal indicatlng the end of guard t~me Ta, up to the attainement of number n.

Circult SRH i8 to generate signal SR, when all unlts NCU with packets to trans~it have accessed the bus.

Even SRH will basically consist of a counting system which, for every packet round, counts the number of active units or the number of times guard time Ta is exceeded, and emits signal SR when maxi~um value n is attained.

This counting system is to take into account that the duration of packet rounds is independent of that of the packet region and hence a frame may comprise a plurality of rounds or a round may extend over a plurality of frames. A flow chart of the operation of SRH is shown in Fig. 9.

Implementation of a circuit operating according to such flow chart presents no problem.

As mentioned, SRH operates in the packet region, and hence it leaves the initial state (wait for RP) each time it receives signal RBR or signal SRR.

In the latter case a counter ~CUIP of the number of units accessing the bus during the round is reset.

The arrival of si gnal RBR indicates on the contrary that a round already initiated in a p~eceding ~rame has not been terminated and hence the counter is not to be reset.

,:

~L;Z3~ - 18 After the arrival of RBR or SRR, the countlng of guard time Ta i8 started (STARTA) and a beginnlng of actlvity slgnal (BAR) i8 waited for.

The start-of-frame slgn~l SFR can arrive before BAR thereby causing the return to the lnltlal state, on the guard time Ta can elapse (TIMOTA).

The arrival of signQl TIMOTA lndicates the lack of activity of a unit and causes counter NCUIP to advance.

After the arrlval of slgnal BAR, SRH walts for the end of paclcet activity of the unit and, when the end is detected (EAR), it increments counter NCVIP.

Instead of EAR the start-of-frame SFR can appear again, and as before causes the return to the initial state.

The described operations are obviously repeated up to the attainment of the termlnal count of NCUIP, which causes emission of SR.

Flgures 10-17 show in greater detail the structure of devices ACM of a unit NCU, in case of a network which uses only passive components.

For this description it is supposed that FG explicitly generates all the frame signals and hence lt has the structure of Flg.8.

In these Flgures, signals representing the events on the two branches lR, lW of the bus have been denoted by symbols ending with letters R, W respectively.

As shown, both devices APH handling the access protocol, and storing devices M~ comprise two portions assigned to packets and circuits, respectively; besides)APH comprises a device MB nitoring the activity on the bus.

As to devices ME, the portion concerning the packets comprises for instance two FIFO memories, one for packets to be transmitted and the other for pac~ets received.

The two memories are schematized with their control devices by block MPX; 4a, 4b indicate the wires conveying packets to be forwarded on the bus and packets received; line 6 schematises the connection with PH ~Fig. 3) both for information and for local signalling.

~ s to the part concerning the circuits, ~E comprises a plurality of buffers MTl....MTh, MRl....MRk for the information to be tran 37~ - 19 smltted or received. eacll buffer ls assoclated wlth its own controller for read and write operations; for simpllcity sake there are shown only devices CTXl~ CRX1 relating to MTl and MR1.

The memories are connected on one side to a switchlng matrix SM connected through llnes 7a, 7b, to AIH (Fig. 3); on the opposite side they are connected to wires 5a (buffers MT) and 5b (buffers MR) through multiplexlngdemultiplexing and parallel-to-series/series-to-parallel converting devices, not shown. ~he controllers are Ln turn connected to a control logic network CC for the circuits and to devices of APH.

As an alternative, when a high number of lines 7 is present, 50 that a great number of buffers MT, MR would be necessary, a single RAM memory could be used, in which the addressing devices signal the beginning and end of memory region allotted to a channel.

That makes it easier to implement units NCU in integrated ~orm.

Logic CC is to enable or disable controllers CTX, CRX, to set up the connections between lines 7 and memories MT, MR through ~atrix SM on the basis of lnformation received from PH through a line 8, and to supply the devices of APH with signals enabling or disabling the reception, ~ith information on the number of circuits to be received and, in case of dynamic speech circuit management, on the state of emission/pause of an active circuit in transmission phase.

In devices APH, circuit ~B has tasks analogous to circuit FRR of Fig. 8, yet with relation to both bus branches; thus it will comprise a pair of circuits like FRR; the only difference is that the element associated with the reading branch is not to emit signal SRR, wich is not used inside unit NCU.

The portion of AP~ assigned to packets consis~ of two different parts designed to control packet transmission towards and recep tion fro~ the bus.

The transmission part is composed of two logic ne~works PAR, PTC. The first recognizes the right of access to the bus during the packet region by the unit it belongs to, on the basis of the Erame signals concerning the bus wTiting branch (SFW, RBW, SR~), ~23~17 - 20 supplied by MB and of the events on such a branch (beglnning- and endof-actlvity signals BAW, EAW, ~upplied by MAU).

The second network exchanges with MAU and MPK the signAIs necessary to control packet transfer from MPK to the bus wlth the already described modalitles.

The receiving part PRC recognizes the packets to be forwarded to the station lt belongs to~on the basis of the address coded in the packet heading, and exchanges with MAU and MPK the signals necessary to forward to and to temporarily store in MPK the packets correctly received (i.e. packets which have not undergone collisions).

For its operations PRC is then connected to wire 4b and in addition it receives from MB ~he frame signals relevant to the reading branch.

Even the part of APH relevant to the circuits is subdlvided into two device groups handling transmission and reception.

Transmission handling,devices comprise, in addition to logic networks CAR, CTC for access right recognition and for transmission control (whlch have functions e~ual to PAR and PTC) a further logic network DSI which~ in case of circuit-switched speech communications to be dynamically processed, enables or not the transmission of the relevant information according to band availability on the bus.

The receiving part (circuit CRC~ enables receiving controll~rs CRX to control the transfer, from wire 5b to ~e~ories MR, of the information flo~s relevant to circuit communications addressed to the unit they belong to, on the basis of the signals supplied by CC, of frame signals and of activity signals on the reading branch.

If a network with regeneration in each unit NCU is considered instead of a passive network, handler APH will not comprise circuit ~B; in fact, as reported, the various frame signals and the beginning and end of activity of a station are represented by suitable bit patterns: unit ~AU then comprises a number of decoders recognizing the various events and directly sends frame signals and the beginningand end-of-activity signals to the various circuits of APH.

3~7~1~37 - 21 ~ lgures 11-16 show a possible circult tmplementatlon of blocks PAR, PTC, PRC, CAR, CTC, DSI and CRC; as to CC, a flow chart of this operation is given.

The meaning of the various signals indlcat~d in Fig. 10 will beco~e apparent from the descriptlon of these Flgures.

In Fig.10 the clock signals are denoted by CKS, without making any dl stinction becween transmission and reception, as possible phase-shlfts between transmission and reception have no interest to the descrlption purposes.

Signal CKS normally has the same frequency as CK (Fig. 8);

yet a different symbol has been uOEed as ln case of a centralized generator of the only signal SF, block FG will have its own oscillator, With reference to Fig. 11, logic PAR is to communicQte to PTC (Fig. 10) the right of access to the bus for packet transmission (signal PACRIG)J to interrupt the packet round at the start of a new frame (signal STOPTX) and to resume in the subsequent frame the interrupted round (signal RESPTX).

To this aim, the logic comprises a counter CNl which is started and reset at each round by signal SRW and counts the pulses present at the output of an AND gate Pl~ Gate Pl is enabled by the output of a set-resec Elip-flop SRl which is set by signal RBW and reset by signal SFW, i.e.

Pl is enabled during the packet region.

Gate Pl supplies CNl either with the end-ofactivity signal (EAW) or with signal TIMOTAW, indicating that guard ti~e Ta is elapsed.

These signals are supplied to Pl through an ~R gate P2.

Signal TIMOTAW is for instance the carry out of a second counter CN2 which is reset and started by signals SRW or RBW or EAW (supplied to CN2 through an OR gate P3) and which counts clock signals CKS up to the arrival of a signal BAW.

The start of CN2 by EAW is the usual start of the counting of che time separating the activities of two units; the start by SRW or RBW takes into account the possibility that the first unit(s) are not active in that round, or that a unit cannot resume trans~isslon after stopping packet activity.

The current count of CNl is supplied to a comparator CMl which stores the serial number of the unit it belongs to and emits si ~lZ371~ - 22 gnal PACRIG when the current count of CNl ls identlcal to such a number.

Slgnal PACRIG stop~ the count of CN1 and sets a second ~t-reset flip-flop SR2, which i8 reset by fl signal PTXEND supplied by PTC (Flg.

1~) to lndlcate the end of packet actlvlty by the unit.

Output Q of SR2 is connected to two AND gates P4, P5, which, in coincidence respectively with signals SFW and RBW, send PTC signal STOPTX stopping packet transmission and signal RESPTX causing transmission restart.

A similar scheme serves also ~or circuit CAR, which yet has only to emit signal CACRI&, denoting access right recognized, towards CTC and DSI (Fig. 10), slnce a circuit round concides with the frame circuit region and cannot be interrupted.

Counter CNl of CAR will be then started by SFW, and counter CN2 will be started either by EAW or by SFW.

Of course SR2, P4, P5 will be missing.

In Fig. 12 packet transmission control circuit PTC comprises SH3 a shiEt register~, receiving a pattern of pits bits PTXSTAO....PTXSTAy.

Bit PTXSTAO is O and the other y bits, whose number is equal to the ~aximum number of packets which can be transmitted, indicate,when at 1, packets to be actually forwarded on the bus during a round.

It is to be appreciated that the bits at l are consecutives since, as mentioned, there are no lnactive "channels" inside the packet activity of a unit and such bits at 1 are the most significant bits, after PTXSTAO . SH3 receives signal PACRIG as a parallel load command and signal NE~TP, through which MAU requests new packets, as a command ~or bits shift towards the most significant positions.

The outputs of all the cells of SH3 are connected to an OR gate Pl3, whose outpllt signal is at 1 as long as there are packets to be eransmitted (i.e. as long as there are bits at l inside SH3); such an output signal is transferred to ~A~ through an AND gate P14 as signal PTXENA enabling packet Eorwarding on the bus.

In addition the most signiEicant bit of the pattern, present at a given instant on the outputs of SH3 forms a signal TYNEXP by which PTC requests MPK (Fig.

10) the sending of a packet on wire 4a.

~ :~3~ - 23 A second lnput of Pl4 is connected to .the output of a aetreset fllp-flop SR5 which ls set by ~ignals PACRIG or RESPTX ~upplied by PAR (Fig. 10) through OR gate P15 and ls reset by signal STOPTX, it too supplled by PAR. Signal STOPTX i3 al~o forwarded to MPK (signal INTPX) to block packet transmission over wire 4a.

Slgnal RESPTX controls the backward shift in S~3.

By this arrangement, as soon as logic PAR recognizes the right of access PACRIG for the unit it belongs to, if such a unit has packets to be transmitted (at least bit PTXSTAl at I), PTXENA ls emitted so that MAU is ready to request the packets; in addition, being PTXSTAO at O, signal TXNEXP is still at O.

When MAU, after having prepared the synchronism word and flag CD relevant to it, sends signal NEXTP, the shift of bits in SH3 brings PTXSTAl on the most significant output, so that TXNEXP passes to 1 and causes MPK to send the first packet to ~AU.

Supposing that the round is noe ineerrupted, operations go on in this way until the transmission of the last packet.

At the arrival of the subsequent signal NEXTP there are no more bits at 1 in SH3 and hence the output of P13 and P14 pass to O, thereby signalling the transmission end to MAU.

In case of interruption of the round, the emission of ST~PTX by PAR (Fig. lO) causes ~PK to stop packet forwarding and causes che passage to O of PTXENA, notwithstanding the output of P13 is still at 1. .

The transmission is restarted at the arrival of RESPTX,in this case, to avoid loss of a packet which has not been completely forwarded, RESPTX causes a backshift by a position of contents of SH3, so that at the arrival of NEXTP transmission can restart from the interrupt point (chis obviously requires the presence in MPK of a counter of the packets transmitted, which is blocked by INTPX).

Signals PCKTXD, ENDPCK indicating end of transmission of a packet are not shown in Fig. 12.

In effect, even if In Fig. 10 they are represented as two separate signals, PTC is transparent to PCKTXD .' ~. . . ..

., ~;237~ - 24 which can dlrectly arrive at MAU to cause emlssion of CD.

In Fig. 13, loglc PRC comprises a shift regi~ter SH4 loadlng in series the bit~ encodlng a packet destination address (wire 4b~;

once the loading is completed, the bits are supplied to a comparator CM2 where the address of the unit PRC belongs to is stored.

These bits are denoted by Qo....QN, where QN is the last address biC.

SH4 is reset at each packet by a signal BEGDAT indicating the packet start. Such signal can be generated through an AND gate P21 which receives at an input sLgnal EACR (indicating a channel end and generated by MAU by decoding flags CD) and has the other input connected to output Q of a set-reset fllp-flop SR8, set by RBR and reset by SFR.

The shift command is given by clock signal CKS, asociated with the data.

This signal ls supplied by SH4 through AND gate P16 which has a second input connected to the output of a set-reset flip-flop SR6 which is set by BEGDAT and reset through OR gate P17 either by signal SFR or by the completion of the address storage Ln SH4 (bit Q~).

The output signal of comparator CM2, indicating the equality among ehe addresses, forms a signal STOPCK enabling the packet storage in ~PK; the same signal STOPCK enables, through a set-reset flip-flop SR7, two AND gates P18, P19 which receive at the other input signals 8EGDAT and SFR.

At the outputs of such gates there are signals PACSUC and ABOPCK, which are sent to ~PK to signal whether the packet has been correctly received or not, the same two signals through OR gate P20 and SR7 disable Pl8, Pl9.

The first signal BEGDAT (emitted at the end of SYNC) has no effect on P18, which is disabled because STOPCK has not yet been emitted; analogously the last signal BE5DAT (end of the last packet) does not effect S~4, which no longer receives data.

In Fig. 14, circuit transmission control logic CTC comprises two parts, the first enabling the controllers of ~emories MTl-MTh (through signals CENATX) and the second enabling information transfer in MAU from wnre 5a to the transmissione line.

The first part comprises a shift-register SHl with h posi~ '~l23~ - 25 tions (h~number of memorie~ ~T), enabled by CACRIG and implemented iuch as to sequentially present on Its outputs a blt l, beginning from the instant o~ arrival of a shLEt command NEXTC~ sent by MAIl to request the transfer of information relevant to a channel by the corresponding memory MT.

The second section consists also of a shift register SH2 ana~ logous to SH3 (Fig. 12) and controlled by signals CACRIG and NeXTCH in the same way as SH3 is controlled by NEXTP and PACRIG. SH2 receives from CC (Fig. 10) bits CTXSTAl...CTXSTAh which, when at 1,indicate the active state of the respective channel.

The outputs of SH2 are connected to an OR gate P4t similar to P13 (Fig. 12), whose output signal forms signal CTXENA (having the same meaning and the same effects as PTXENA).

In addition the signal present at each instant at the output of SH4, corresponding to the most significant bit is sent co MAU as signal CHS, which indicates the active state of the channel to be transmieted.

In case of inactivity, the logic value O of C~S causes in MAU the emission of the only signal CD.

Of course, since the circuit activity is not interrupted ehe possibility of a back shift, as in SH3 is not provided for.

In addition, any of bits CTXSTA can be I or O, as temporarily circuits inactive can he present between the active ones.

Logic CTC i5 also to signal the end of a circuit (signal CENDTX) to MAU; this signal can be obtained e.g. as a logic OR of signals CENDTXl....CENDTXh emitted to tne same end by memory controllers.

With reference to Fig. 15, circuit DSI is to recognize during a frame the speech channels on the basis of the odd-even arrangement and disable the transmission of information of speech channels after the attainment of the maximum number.

To this aim DSI basically consists of two counters CN3, CN4.

The first is a modulo-2 counter started through an OR gate P6 by signal BAW (for recogni~ing speech channels of upstream units) or signal CACRIG (for the channels of the unit it belongs to); CN3 counts si ~2327~ gnals EACW (end of an evene on the wrltlng channel~ or signflls NAC~(inactive channel) or stlll signals NEXTCH, received through an OR gate P7.

Signals EACW, NACW (relevant to the actlvlty of upstres~ unlts) are supplied by MAU on the basis of detection of flags C~.

The lnitial counting value of CN3 will be established so as not to take into account signal EACW corresponding to ehe end of synchronism word.

Signal NEXTC~ refers on the contrary to the station activity.

Supposing, as before, that speech communications are assigned to odd channels within a station actlvity, the outpu~ slgnal of CN3 corresponding to count "1" forms the clock signal for CN4.

Such signal is transferred to CN4 through an AND gate P8.

The transfer is enabled by the output signal of a D-type flip-flop FF2 (controlled by a suitable clock signal ICK), which stores either signal EACW or request NEXTCH for another channel, provided such a channel is active (signal CHS), as schematised by OR gate P9 and by AND gate P10.

Signal NEXTCH is to be delayed to allow the arrival of CHS; the delay is schematised by inverter Il.

Counter CN4 is reset at each frame by SFW and emits as carryout signal VTCXD disabling controllers CTX. According to the value preset in CN4, VTCXD can indicate either the last channel ~hich can be transmitted, or a channel which c~n no longer be transmitted.

In ~hat second case, reading commands for memories ~r must be delaye~ so as to allow generation of VTCXD; in the first case, on the contrary it will be sufficient to memorize ~TCXD into a register, which keeps it present from ehe instant of its generation up to the beginning of the subquent frame.

With reference to Fig. 16, logic CRC is to enable the storage in memories ~Rl...MRk of the information present on wire 5b and relating to different communications, CRC will then comprise k elements (one for each memory), which are enabled and disabled by signals ENARXl....~NARXk, DIRXl....DIRXk supplied by logic CC (Fig. 10) handling the association between memories and communications, and which ~3~ - 27 emit an enabling signal OE NARXl....CENARXk for controller CRX of the respective memory.

Each element comprises a register RCBi (i=1....k) which, upon command of the relevant signal ENARXi, stores a bit pattern NCRX, supplied by CC and representing a pair of numbers nl, n2 identifylng the individual communications.

This bit pattern is supplied by RCBi to a respective comparator CPi, which compares it with the values supplied by a pair of counters CN5, CN6 and emits an output signal when the two pairs of numbers are equal.

The first of these counters is desgined to supply number nl of the unit which is active at a given instant of the circuit region;

hence CN5 is started by signal SFR (start-of-frame on the reading branch) and stopped by signal RBR, and it counts signals TIMOTAR (guard time elapsed on the reading branch) or EAR supplied eo it through an OR gate Pll.

Signal TIMOTAR is generated as signal TIMOTAW used in circuit CAR.

The second counter is to count number n2 of the channels inside th~ activity period, and hence it is started by signal ~AR, and stopped by signal EAR and it counts signals EACR or NACR it received from gate an OR P12. What stated for EACW holds true also ~or the counting of EACR.

The signal outgoing from comparators CP1....CPk can be emitted during circuit region as signals OENARXl....k, through AND gates PAl....PAk, as long as the relevant channel is enabled.

Hence a gate PAi will receive as enabling signals the signal present at output O of a set-reset flip-flop SR4, set by SFR and rese~ by RBR, and the signal present at the output of a set~reset flip-flop FSi (i=l....k), set by ENAR~i and reset by signal DIR~i indicating circuit disabling.

~ ogic CRC instead of consisting of k separate ele~ents, could comprise a single memory, addressed bv counter CN5 and storing in each posi~ion a coding of the channels to be received.

Reference will now be made to Fig. 17.

Considering first an 1~3711!3~7 - 28 outgolng communlcation, CC receives ~rom nl (Flg. 3) the lnformatlon relevant to memory MT and to line 7 interested Ln the communication (NCTl) adn as a consequence lt s.ets up the connection between ~he line and the memory through matrix SM. Once effected such a connection (SETMTX) CC sets to 1 slgnal CTXSTAl relevant to such a memory and enables controller CTXi (signal ENTBi).

For a communlcation which does not require a dynamic management, the situation remains unchanged up to the release.

For a communicatlon dynamically managed, CC recel~es, e.g. by the user, signals NACi, ACl indicating the state of pause/emission of the source ln the frame, and sets (or keeps) as a consequence to 0 or to 1 CTXSTAi, as the case ~ay be.

The actual posslbility of transmission depends then on the decisions made by DSI (Fig. 10).

The release is signalled by PH through signal ETCi which causes CC to set at O CTXSTAl and disable CTX (signal DISTBi).

For the reception, the information necessary to set up the connection between a memory ~R and a subscriber line, are again supplied by PH (signal NCRi), in conjunction with the indications relevant to the position of reception channel within the station activity;

in this case CC, besides controlling the connection through SM (SETMT2), can supply CRC with bit pattern NCRX (SETNCRX) and the register involved wlth the enabling signal eNARXi.

After the enabling of memory MR (ENRBi), CC ~aits ~or the release (ECRi), which is processed as that relevant to the transmission.

It is to be considered that for dynamically controlled communications it is necessary to interrupt the reading from memories MR during channel pause periods; that can be obtained in controller CRX by detecting and signalling to the subscriber the absence of clock signals~ which means the absence of valid data.

The operation oE the device of a ~nic for the transmission and reception of information clearly appears ~rom the above description, and funther details are unnecessary.

Only a number of remarks will be made concerning the communication set up and release.

~Z37~7 - 29 Both clrcuit-swltched and pflrket-swltched communlcatlons re~ qulre at the beginning the lnterventlon of network controller NCC; in fact only NCC stores the associat10ns between subscribers and NCUs, and then NCC is to supply the calling party with the data nece~sary to reach the called party. In addition, band availabillty for the new communication i5 to be ascertained.

In case of a packet-switched communication the possible unavailability at the request instant causes solely a delay in the set up of the communication which is always accepted.

In case of circuit-switched communications, the band unavailability, at the request lnstant, renders the set up of the com~unicatlon impossible. A band negociation could even be possible, that is the subscriber can begin the communication with a reduced band and subsequently obtain the complet band. An example can be videotelephony: in case of initial unavailability of the whole band required, the phone communicatlon can be immediately set up and the video communication will be set up afterwards.

Still in case of a circuitswitched communication, once ascertained the possibility of setting up the communicaeion the calling party is still to supply the called party with the information concerning the channel used.

Once the communication has been set up, the network controller is no longer involved and the communication is exclusively controlled by the NCUs involved.

The controller must be informed of the communication end, as it cannot discriminate between the end of a com~unication and a pause in case of dynamic control.

The above description is given only by way of non limiting example and variations and modifications can be made without departing from the scope of the invention.

For example, a centralized generator FG has been considered above at least for the generation of signal SF: yet, in case of a con figuration like that o~ Fig. 2, generator FG could be associated with each unit and, as before, could explicitly generate only SF or all the slgnals.

As to generation of SF, the clocks of all units NCU synchro , ........ :............ ~ - :

1~37~ - 30 nize themselves at each fra~e with the instant of recognition of slgnal SF generated by most upstreum unit NC, and therefore, when time Z from the recognition of signal SF has elapsed, the sending of ~quch a signal onto the llne is au~omatically enabled.

Possible overlapping of more signals SF has no consequence.

Thanks to the fact that each unit counts time Z to establish the instant of emission of SF, collisions are avoided between the last packet of a frame and signal SF, because the unit can automatically interrupt packet transmlssion when time perlod z is about to elapse.

This frame signal management might give rise to problems for the activation of a unit upstream of already active units, as such a unit is to determine its Lnstant of emission of SF.

Yet this instant can be easily recognized by counting the time elapsed between the end of circuit activity and signal RB on the bus reading branch and anticipating by such a time the emission of SF with respect to the duration Z of the frame: in fact tllis time is constant for all the units, since it is given by the propagation delay from the writing point to the reading point - which delay in a twice-folded bus is equal for all the stations - plus the propagation time on branchings 2 (Fig. 3), which however is compensated by SF.

In addition, still with the explicit emission o~ all the frame signa7s, the same unit generates SF as well as RB and SR, since the unit which transmtts ~irst (and then generates SF) is also the first which recognizes the other events.

. . .