Method and apparatus for setting cache policies in a processor

(54) Title: METHOD AND EQUIPMENT TO ADJUST CACHE POLICIES IN A PROCESSOR (30) Unionist Priority: 24/01/2007 us 11 / 626,434 (73) Owner (s): Qualcomm Incorporated (72) Inventor (s): Michael William Morrow (74) Attorney (s): Montaury Pimenta, Machado & Lioce (86) International Request: pct US2008051953 of 24/01/2008 (57) Summary: method and equipment to adjust CACHE POLICIES IN A PROCESSOR. In accordance with the methods and equipment taught in the present invention, processor caching policies are determined using cache policy information associated with a target memory device accessed during a memory operation. According to a processor mode, the processor comprises at least one cache and a memory management unit. At least one cache is configured to store information local to the processor. The memory management unit is configured to adjust one or more cache policies for at least one cache. The memory management unit adjusts one or more cache policies based on cache policy information associated with one or more target memory devices configured to store information used by the processor.

(87) International Publication: wo 2008 / 092032of 07/31/2008

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PI0806756-2

METHOD AND EQUIPMENT

TO ADJUST CACHE POLICIES ON A PROCESSOR

FUNDAMENTALS

Field of the Invention

The present invention generally relates to caching operations on a processor and, particularly, refers to the determination of cache policies.

Fundamentals Processor performance is enhanced by adding one or more levels of cache locally on a processor to store information that is accessed frequently or used most recently. A processor cache is a small, fast memory that stores a copy of selection information stored in main memory such as DRAM or a hard drive. When an instruction accesses a memory location, the processor first checks whether the memory location is repeated in a local cache. In particular, the address associated with memory access is compared to all indicators in a 'cache. If the desired memory is found in the cache, a cache request occurs. On the other hand, a loss of cache occurs.

When a cache request occurs, the processor immediately reads or writes information such as data or instructions on the identified cache line. In the event of a cache loss, the desired information is retrieved from a higher level cache or main memory. In addition, a new entry is conventionally allocated in the cache to store recently retrieved information. The new entry comprises an indicator that identifies the address that

2/15 caused the loss of cache and a copy of the information retrieved from the main memory.

To accommodate a new cache entry, an existing entry is removed from the cache. The heuristic used to choose the entry to be evicted from a cache is based on a replacement policy such as first entry, first exit or less recently used. Other cache policies (also called cache attributes) are also used to determine how a cache is accessed, used and maintained. Other cache policies include write policies, allocation policies, cache level policies and custom policies.

Write policies determine when information written to a cache block is also written to main memory. For example, the cache and main memory are updated at the same time when a direct write policy is used. When a write-back policy is employed, the main memory is updated only when the corresponding cache block is replaced. A single write policy uses a direct write policy for the first write to a specific cache block and a write back policy for subsequent writes to the same block.

A cache allocation policy determines when a cache block is written. For example, if the allocation policy associated with a specific cache block is to allocate in read-only, the block is not interrupted during writing. Conversely, the cache block is updated during both writing and reading when the allocation policy is to allocate in read and write. For processors with multiple levels of caches such as first level instruction and data caches and at least one higher level cache,

3/15 a cache level policy determines which cache level is used to store information. For example, instructions can be stored in a first-level cache instruction while other information can be stored only in a second-level cache.

Cache policies are conventionally stored in a paging table. The paging table is maintained in main memory with the most recently used or frequently accessed entries being stored locally on a processor, for example, in a Translation Lookaside Buffer (TLB), or Translation Forecasting Buffer. Each entry in the paging table maps a virtual address to a corresponding physical address. In particular, the paging table stores a list of virtual page numbers and corresponding physical page numbers. The virtual page numbers identify respective blocks of virtual memory allocated in processes that operate on a processor, while the physical page numbers identify the corresponding physical memory blocks that contain the actual information used by the processes.

When a processor accesses a specific memory location, paging table entries are searched using the virtual page number portion of the virtual address provided as part of the access. The physical page number is retrieved from the corresponding paging table entry. The physical page number and page offset form a physical address that is used to access the desired memory location.

If the desired memory location is not contained in a local processor cache, the main memory is accessed. The cache policy information stored in the paging table entry determines whether

4/15 information read or written to main memory as part of memory access is stored locally in the cache and, if this occurs, how the information is kept in the cache. In this way, cache policies are conventionally adjusted and applied to a cache on a per-page (or per-block) basis. In addition, cache policies are conventionally programmed through the operating system. As such, cache policies are generally applied to all processes that operate on a processor and can result in inefficiencies when used by a specific type of main memory device. For example, a cache allocation policy of allocating in read-only may improve the use of the cache for some processes such as graphical applications exclusively.

SUMMARY OF THE INVENTION

In accordance with the methods and apparatus taught in this document, processor caching policies are determined using cache policy information associated with a target memory device accessed during a specific memory operation. Thus, caching operations can be tailored to the specific memory device's settings instead of general cache policy settings. Processor performance is improved by determining cache policies for a current memory operation based on the cache policy information associated with the target memory device accessed during the memory operation.

According to a modality of a processor, the processor comprises at least a cache and a memory management unit. At least one cache is

5/15 configured to store local information to the processor. The memory management unit is configured to adjust one or more cache policies for at least one cache. The memory management unit adjusts one or more cache policies based on cache policy information associated with one or more target memory devices configured to store information used by the processor.

According to a system modality, the system comprises a processor that has at least one cache configured to store information local to the processor, or one or more target memory devices coupled to the processor and a memory management unit included in the processor. The one or more target memory devices are configured to store information used by the processor. The memory management unit is configured to adjust one or more cache policies for at least one cache based on cache policy information associated with one or more target memory devices.

Obviously, the present invention is not limited to the aforementioned features and advantages. Those skilled in the art will recognize additional features and advantages by reading the following detailed description and viewing the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a block diagram that illustrates a modality of a system that includes a processor that has a set of circuits to determine cache policies.

Figure 2 is a block diagram that illustrates an embodiment of an address decoder circuit for

6/15 provide cache policy information associated with a memory device.

Figure 3 is a block diagram that illustrates another modality of a system that includes a processor that has a set of circuits to determine cache policies.

Figure 4 is a block diagram that illustrates a circuitry modality for determining cache policies on a processor.

Figure 5 is a logic flow diagram that illustrates a modality of program logic for determining cache policies on a processor.

Figure 6 is a diagram that illustrates how the circuitry in Figure 4 determines the caching policies responsive to an example write operation.

Figure 7 is a diagram illustrating how the circuitry in Figure 4 determines the caching policies responsive to an exemplary read operation.

DETAILED DESCRIPTION

Figure 1 illustrates an embodiment of a system 10 that includes a bus 12 that couples a processor 14 to one or more peripheral devices 16 and the main memory such as a hard disk drive (HDD) 18 and DRAM such as Synchronous DRAM (SDRAM ) 20 and Synchronous Graphical RAM (SGRAM) 22. Processor 14 includes a processor core 24, instruction and data caches 26, 28, a second level (L2) cache 30 and a bus interface unit 32. Processor core 24 provides centralized instruction flow control and instruction execution. Data and instruction caches 26, 28 store

7/15 data and instructions, respectively. The L2 cache 30 provides a high speed memory buffer between instruction and data caches 26, 28 and the external main memory of processor 14 such as HDD 18, SDRAM 20 and SGRAM 22. The bus interface unit 32 provides a mechanism for transferring data, instructions, addresses and control signals between processor 14 and external devices in relation to processor 14 such as peripherals 16 and main memory 18, 20, 22.

Main memory 18, 20, 22 is represented as virtual memory in processes operating on processor 14. That is, the pages of physical memory are allocated as virtual memory for use in processes during program execution. A paging table 34 is maintained in main memory 18, 20, 22, for example, as shown in Figure 1, to enable the mapping between physical and virtual address spaces. A memory management unit (MMU) 36 included in processor 14 accesses paging table 34 and handles memory accesses issued by processor 14, including virtual memory management, memory protection, cache control and bus arbitration. As part of virtual memory management, MMU 36 maintains the location of the frequently or recently mentioned entries (PTEs) on processor 14, for example, in a Translation Lookaside Buffer (TLB) 38, or Translation Prediction Buffer .

When processor 14 accesses a desired memory location identified by a virtual address, MMU 36 accesses TLB 38 to determine whether TLB 38 contains a corresponding entry. If so, the virtual address is translated into a physical address using address translation information in the corresponding TLB entry. Per

8/15 On the other hand, paging table 34 is searched for a corresponding entry. In any case, MMU 36 initiates a cache search operation on one of the physically indicated caches 26, 28, 30 based on the resulting physical address. If one of the caches 26, 28, 30 contains the desired memory location, the corresponding cache line is accessed and access to memory is completed, for example, by reading or writing the cache line. On the other hand, MMU 36 initiates memory access to main memory 18, 20, 22 to access the desired memory location.

Main memory 18, 20, 22 is accessed by providing the physical address that identifies the desired memory location. The memory device containing the desired memory location is referred to in the present invention as the target memory device. According to the various modalities disclosed in this document, the target memory device can comprise any addressable memory module, device or bank included in the system. For example, a target memory device can be one of SDRAMs 20, SGRAMs 22 or another memory device (not shown) depending on the specific process to be performed by the processor 14.

In response to an external memory access, the cache policy information associated with the corresponding target memory device is provided for a cache policy tuning loop 40 included in or associated with MMU 36. The cache policy tuning loop 40 determines the cache policy settings for the current memory operation based on the cache policy information associated with the corresponding target memory device. Thus, when processor 14 accesses a specific external memory location,

9/15 cache are adapted to the corresponding target memory device that contains the desired memory location.

For example, if a memory operation is directed at one of the SGRAM 22 devices, the cache allocation policy associated with the target SGRAM device can be allocated in read-only when the target device's functions as a video frame temporary storage for a multimedia application. Processor 14 can write to the target SGRAM device frequently while running a multimedia application, but rarely read from the device. Thus, the cache allocation policy of the target SGRAM device may indicate allocating in read-only to improve processor performance. The cache policy information for the target memory device may also indicate a replacement policy, write policy, allocation policy, cache level policy and / or one or more specific custom policies.

In one embodiment, the cache policy information associated with a target memory device is provided by a memory controller 42 that provides an interface between bus 12 and the various DRAM devices 20, 22 as shown in Figure 1. According to this embodiment, the memory controller 42 includes an address decoder circuit 44 for decoding the physical memory addresses provided by the processor 14 as part of the memory accesses (for example, reads or writes). The cache policy information generated by the address decoder circuit 44 is a function of the physical memory address provided as part of a specific memory access. The physical address identifies the memory device that contains the memory location that is the target of the current memory operation.

10/15

Figure 2 illustrates an embodiment of the address decoder circuit 44. According to this embodiment, the decoder circuit 44 includes an address decoder 46, a multiplexer 48 and a table 50 that has several inputs 52 associated with the respective devices. memory 20, 22 supported by memory controller 42. Each entry in table 52 contains cache policy information associated with a corresponding memory device.

When processor 14 accesses external memory, the physical address included as part of the access identifies one of the memory devices 20, 22 supported by memory controller 42. The address decoder 46 decodes the physical address, causing multiplexer 48 to select entry 52 that contains the cache policy information associated with the target memory device identified by the physical address. The memory controller 42 provides the selected cache policy information for MMU 36 via bus 12 and bus interface unit 32 (for example, as shown by the dashed line starting from address decoder circuit 44 through MMU 36 in Figure 1). The cache policy adjustment circuit 40 uses the received cache policy information to adjust the cache policies for the current memory operation. In this way, cache policies can be adjusted on a per line cache basis as a function of the target memory device.

In another embodiment, the cache policy information is provided by an address decoder circuit 54 included in processor 14, as shown in Figure 3. According to this modality, the address decoder circuit 54 provides

11/15 cache policy information based on virtual addresses or physical addresses, for example, as previously described and according to Figure 2. In yet another modality, one or more of the memory devices 20, 22 supported by the controller 42, store their cache policy information, for example, in a device ID register or other register (not shown). When a target memory device is accessed by memory controller 42, cache policy information is provided to controller 42 and forwarded to processor 14, as previously described. Alternatively, cache policy information is provided for the request, for example, system initialization or processor restart 14. the processor 14 can store the adapted cache policy information upon receipt, thereby avoiding the need to request the same information when the corresponding target memory device is subsequently accessed. Instead, processor 14 retrieves internally and uses the adapted cache policy information.

the policy tuning circuit uses the cache policy information from the target memory device to adjust the cache policies during memory operations.

Figure 4 illustrates a modality of the cache policy tuning circuit 40 included in or associated with MMU 36. According to this modality, the cache policy tuning circuit 40 includes a selection circuit set 56 to adjust the policy policies. cache targeted to a current memory operation. In more detail, processor 14 without automatically during upon additionally,

Regardless, cache a

12/15 paging table entry (PTE) 58 that corresponds to the virtual address provided as part of a memory access is retrieved both from TLB 38 and from paging table 34 (for example, as shown by the dashed line from paging table 34 to MMU 36 in Figure 1). The virtual address is translated into a corresponding physical address based on the address translation information 60 stored in the corresponding PTE 58 where the physical address identifies the desired memory location.

If the desired memory location is not found in one of the processor caches 26, 28, 30, MMU 36 initiates an external memory access. In response to the request, memory controller 42 identifies the target memory device containing the desired memory location based on the translated physical address. Processor 14 obtains access to the target memory device via memory controller 42. The target memory device performs the desired memory operation (for example, a read or write). In addition, the cache policy information associated with the target memory device is provided to the cache policy tuning circuit 40 and stored in a storage 62 as part of the memory operation, for example, as illustrated by Step 100 in Figure 5 .

The selection circuitry 56 processes the cache policy information 64 retrieved from the corresponding PTE 58 and the cache policy information of the target memory device stored in storage 62, for example, as illustrated by Step 102 of Figure 5 The cache policy information 64 retrieved from the corresponding PTE 58 is overwritten with the target device information and

13/15 used as the current cache policy settings. However, if no cache policy information is provided for the target memory device, the cache policy information 64 retrieved from the corresponding PTE 58 is used instead.

A simply illustrative example of how the cache policy tuning loop 40 determines caching policies is illustrated in Figure

6. Processor core 24 issues a write memory request to virtual address X. MMU 36 retrieves the corresponding PTE from both TLB 38 and paging table 34 and uses this to convert virtual address X to a physical address X ' corresponding. MMU 36 then probes one or more of the physically indicated caches 26, 28, 30 using physical address X '. In this example, none of the caches 26, 28, 30 contain the desired memory location as indicated by a cache leak. Consequently, MMU 36 issues an external memory write request to memory controller 42 based on physical address X '. The memory controller 42 selects the target memory device that contains the memory location identified by the physical address X '. The target memory device performs the desired write operation and informs the controller 42 that writing is complete.

In addition, the physical address X 'is decoded and the cache policy information corresponding to the target memory device retrieved as previously described, for example, by the address decoder circuit 44 or 54. Alternatively, the target memory device provides its cache policy for memory controller 42. Regardless, MMU 36 is notified of the fact that

14/15 that the write operation is complete. In addition, the cache policy tuning circuit 40 provides the cache policy information of the target memory device. In this example, the cache policy information indicates to allocate in read-only. Thus, the write operation is completed on processor 14 and MMU 36 does not allocate a cache line in one of processor caches 26, 28, 30.

Figure 7 continues the exemplary illustration showing a subsequent read request issued by processor core 24 at the same virtual address X. Recall, the cache policy information from the target memory device indicates allocating read-only to the memory location identified by physical address X '. Therefore, no cache lines were previously allocated to physical address X '. As such, a cache loss occurs during the present read operation.

Additionally, when the target memory device completes the read operation, it is not completed on processor 14, as the cache policy information from the target device indicates that a cache line must be allocated. In this way, the cache policy tuning circuit 40 adjusts the current cache allocation policy so that MMU 36 instructs one of the processor caches 26, 28, 30 to allocate a cache line to physical address X '. In addition, a cache level policy associated with the target memory device can indicate which cache level should allocate a cache line, for example, one among first level caches 26, 28 or L2 cache 30. Other cache policies can also adjusted based on the cache policy information of the target device. Either way, the corresponding data is

15/15 also provided for processor core 24 for processing.

Bearing in mind the range of variations and applications mentioned above, it should be understood that the present invention is not limited to the description mentioned above, nor is it limited to the attached drawings. In contrast, the present invention is limited only by the following claims and their legal equivalents.