High efficiency converter

In support of the Application made by RIFALA PTY. LTD., for a Patent 26008/88 for an invention entitled:

HIGH EFFICIENCY CONVERTER

I , ROD TUSON, of RIFALA PTY. LTD., do solemnly and sincerely declare as follows:

1. I am authorized by RIFALA PTY. LTD.

the applicant for the patent 26008/88 to make this declaration on its behalf.

2. RODNEY RHYS TUSON of 54 Fox Valley Road, Wahroonga, New South Wales 2074 and ISAAC DIMANSTEIN of 9/42 Burdett Street, Hornsby, New South Wales 2077 are the actual inventor/s of the invention and the facts upon which RIFALA PTY. LTD. is entitled to make the application, are as follows:

The said RIFALA PTY. LTD.

is the assignee of the said RODNEY RHYS TUSON and ISAAC DIMANSTEIN

DECLARED this

To: THE COMMISSIONER OF PATENTS.

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(12.) PATENT ABRIDGMENT (11) Document No. AU-B-26008/83 (19) AUSTRALIAN PATENT OFFICE (10) Acceptance no. 613985 (54) (51)⁴ (21) (87) (30) (31) (43) (44) (71) (72) (74) (56) (57)

Title

HIGH EFFICIENCY CONVERTER

International Patent Classification(s)

H02M 003/337 H02M 007/519

Application No. : 26008/88

PCT Publication Number: W089/04082

Priority Data

Number (32) Date (33) Country

PI5168 29.10.87 AU AUSTRALIA

Publication Date : 23.05.89

Publication Date of Accepted Application : 15.08.91

Applicant(s)

RIFALA PTY. LTD.

Inventor(s)

RODNEY RHYS TUSON; ISAAC DIMANSTEIN

Attorney or Agent

WATERMARK PATENT &amp; TRADEMARK ATTORNEYS , Locked Bag 5, HAWTHORN VIC 3122

Prior Art Documents

US 4443840

EP 204375

Claim

H02M 007/527 (22) Application Date : 28.10.88

A zero voltage switching DC to AC inverter comprising:

transformer means having a given primary inductance , two or more switching means adjunct having capacitance, and optionally further capacitance means said switching means combined with said transformer means to form two switching paths, said adjunct capacitance means and optional further capacitance means forming a resonant circuit with said primary inductance of said transformer,

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drive signals from a circuit or signal generator for controlling said switching means resulting in substantially symmetrical switching of the said switching paths and means to ensure that the said transformer is not loaded during the time when neither of the said symmetrical switching paths is conducting, wherein the said drive signals are controlled to switch on the switching means in one of the switching paths after a period of time when t’he switching means in the other switching path is switched off, sufficient to allow the phase of the voltage across said transformer to be inverted by said resonant circuit.

I

INTERNATIONAL APPLICATION (51) International Patent Classification 4 ;

ublication Number:

WO 89/ 04082 (43) International Publication Date:

May 1989 (05.05.89)

PCT

OPI Date 23/05/89 Appln- ID 26008 / 88

AOJP Date 29/06/89

T Number PCT/AU88/00419

H02M 3/337,7/519,7/527

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Al (21) International Application Number: PCT/AU8 8/00419 (22) International Filing Date: 28 October 1988 (28.10.88) (31) Priority Application Number: PI 5168 (32) Priority Date: 29 October 1987 (29.10.87) (33) Priority Country: AU (81) Designated States: AT (European patent), AU, BE (European patent), CH (European patent), DE (European patent), DK, FI, FR (European patent), GB (European patent), HU, IT (European patent), JP, KR, LU (European patent), NL (European patent), NO, SE, SE (European patent), SU, US.

Published

With international search report.

(71) Applicant (for all designated States except US): RIFALA

PTY. LTD. [AU/AU]; 103 Hunter Street, Hornsby, NSW 2077 (AU).

(72) Inventors; and (75) Inventors/Applicants (for US only) : TUSON, Rodney, Rhys [AU/AU]; 54 Fox Valley Road, Wahroonga, NSW 2074 (AU). DIMANSTEIN, Isaac [AU/AU]; 9/42 Burdett Street, Hornsby NSW 2077 (AU).

(74) Agent: WATERMARK.; Suite 6, Floor 16, Town Hall House, 456 Kent Street, Sydney, NSW 2000 (AU).

(54) Title: HIGH EFFICIENCY CONVERTER (57) Abstract

A new principle for high efficiency power conversion at high frequencies is described. The principle provides zero voltage switching b' using the magnetising current of a transformer or parallel inductance to charge the switch adjunct capacitance and other capacitance during the dead time. The transformer is prevented from being loaded during the dead time. An embodiment of the invention is described where loading of the transformer during the dead time is prevented by directing the output inertial current to a capacitor instead of through the rectifiers to the secondary of the transformer. This can also be achieved by using synchronised rectification that provides pulse width modulated regulation on the output and ensures that the transformer secondary is separated from the inertial current of the output during the dead time. Voltage and current stresses on the switching devices and rectifiers are minimised. The principle may be applied to inverters where the load is resistive.

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WO 89/04082

PCT/AU88/00419

HIGH EFFICIENCY CONVERTER

TECHNICAL FIELD

This invention relates to electrical power conversion apparatus, and more particularly to DC-DC converters and DC-AC inverters where two or more switching devices are switched in sequence, resulting in symmetrical switching, for example push-pull, full bridge and half bridge topologies.

BACKGROUND ART

Industry demands for increased density, that is more power transferred in a given volume, have led to the use of higher switching frequencies to minimise and magnetic core sizes. These higher frequencies greater attention to switching losses, which significant proportion of conversion the losses , total losses of capacitor require a become a the power apparatus . The sum of all the losses becomes even more important, self-heats inking density is best when an apparatus is to be

In required practical application, power

The expressed amount of as :

device divided by the dimensions of the device power delivered volume , defined expressed as a by a conversion by the extreme single geometric solid, and including a heatsink appropriate for a given airflow, MTBF (mean time before failure) and ambient temperature.

For high power density, it is necessary to increase the operating frequency of a converter in order to minimise the volume of magnetic components and capacitors. Whereas these volumes can thus be quite readily reduced, that of the heatsink is determined, for a given environment, by the power losses. Thus the installed power density is principally governed by the conversion efficiency. As the frequency is increased, switching losses of the switching and rectifying devices become significant, so a method of obtaining switching at zero voltage or zero current through

WO 89/04082

PCT/AU88/00419 the switching device at the time of switching is desirable.

With apparatus in which zero current switching is utilised, the dissipation caused by the product of the voltage across the switching device and the current through it, integrated over the period of the switch transition, is eliminated, but the dissipation caused by discharging the voltage on the parasitic capacitance of the switching device remains .

In zero voltage switching (ZVS), both the voltage current product 'integral and the discharge energy of the parasitic capacitance are eliminated. At higher switching frequencies, the parasitic capacitance energy is significant, therefore zero voltage switching is to be preferred for minimum losses.

Several techniques for obtaining ZVS have been proposed :

1. A Flyback quasi-resonant converter providing isolation has the disadvantage that high voltage stresses are presented to both the switching device and the output rectifier. Furthermore, ZVS is dependent on load current. At small load currents, ZVS does not occur.

2. A quasi-resonant forward converter has been proposed which achieves ZVS by using the magnetising current of the transformer. The disadvantage is that high voltage stresses are presented to the input switching device and the rectifier.

3. Charging the parasitic capacitance of the switching device with the magnetising current and load current during the dead time _vdead time being the period in which the switching device is turned off) has been used effectively on a full bridge converter and provides for pulse width modulated regulation. A disadvantage is that an inductor in series with the transformer primary is required, and ZVS is dependent on load current.

4. A full bridge using the magnetising current and the energy stored in the primary-secondary leakage

WO 89/04082

PCT/AU88/00419 inductance of the transformer has been proposed, but does not provide ZVS on all four switches.

5. A similar configuration can be used in a half bridge topology, with an inductor in series with the primary of the transformer. A disadvantage is, again, that ZVS depends on a certain minimum load. To achieve regulation, since the dead time must be maintained constant, operation at very high frequencies is necessary.

6. A further example is the high frequency power supply device disclosed in United States Patent 4,553,199. All embodiments of this disclosure illustrated in figures 1, 3, 4, 5, 6 and 7 thereof show the use of a series inductive element and not the magnetising inductance of the transformers and various methods are proposed for regulating the output.

These six examples illustrate the fundamental conclusion that, to achieve both ZVS and regulation within a converter, an inductance other than the magnetising inductance of the transformer must be provided so as to give a ramp in the voltage of the parasitic capacitance in the dead time, during which the transformer is loaded. This conclusion gives rise to the necessary dependence on load current.

SUMMARY OF INVENTION

It is an object of the present invention to provide a zero voltage switching converter which is capable of operation at high frequencies with high efficiency at relatively low output voltage.

Line regulation within the converter is dispensed with, enabling the use of magnetising inductance to provide the necessary reactive elements, together with the adjunct capacitances of the switching devices and other parasitic capacitances for zero voltage switching under all load conditions. To achieve ZVS in such a configuration, the transformer must not be loaded during the dead time.

For DC output converters using this principle and

WO 89/04082

PCT/AU88/00419 having inertial components such as inductors in the output, closed loop regulation is possible only if synchronised rectification is used which disconnects the transformer secondary from the output inertial components during the dead time. Alternatively, regulation must be provided in a pre-regulator or post-regulator, in which case, the feedback loop could be closed around the combined converter.

There is provided according to the present invention a ze^o voltage switching DC to AC inverter comprising transformer means having a given primary inductance , two or more switching means combined to form two switching paths, capacitance means^forming a resonant circuit with said primary inductance of said transformer, drive sign-'ls from a circuit or signal generator for controlling said switching means resulting in approximately symmetrical switching of the said switching paths and means to ensure that the said transformer is not loaded during the time when neither of the said symmetrical switching paths is conducting, wherein the said drive signals are controlled to switch one of the switching paths on after a period of time when the other is switched off, sufficient to allow the phase of the voltage across said transformer to be inverted by said resonant circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows a schematic diagram of the power train of a Push-pull DC-DC Converter embodying the principles of the invention.

Figure 2 shows waveforms related to the push-pull converter embodiment of the invention.

Figure 3 shows conversion efficiency as a function of output current, and

Figure 4A and 4B show a plan and elevation of the

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WO 89/04082

PCT/AU88/00419 transfomer core of the converter.

PREFERRED EMBODIMENT OF THE INVENTION

Following is a description of a preferred embodiment of a ZVS DC-DC converter in which switching occurs independently of load current, with reference to the drawings .

Prior to tO, switch SA is on. Magnetizing current and load current are flowing through switch SA. At time tO, SA is caused to turn off. The transformer T1 has leakage inductance, which has energy associated with it. When switch SA is turned off this energy continues to flow to the output capacitor, CO, and at the same time will charge CA, the switch capacitance of SA by a small amount, and discharge CB, the capacitance of switch SB by a small amount. At the same time magnetising current will continue to flow in the same direction and charge the capacitance of SA.

Because the capacitance CA is being charged, the voltage across the transformer primary A will decrease. Because primaries A and B are wound on the same core, the voltage on B will decrease by the same amount. This means that Capacitor CB will start to discharge. Magnetising current then starts to flow between the two switches rather than between capacitor CC and SA or SB. The magnetising current flows in a positive direction into SA and a negative direction from SB. The voltage across the transformer starts to change polarity, so the same occurs on the secondary .

The voltage across the transformer secondary B starts to increase in a positive direction. At this time no current is flowing through the rectifier diodes, since the secondary voltage is less than the sum of the voltage on Vo and the forward voltage drop of the rectifier, which means that Co starts to discharge at a rate determined by the output current. At tl, the voltage across secondary B will be equal to the voltage across Co plus the voltage drop on

WO 89/04082 &lt;O

PCT/AU88/00419 the rectifier. Then current will start to flow through the rectifier B and primary B into capacitor CB, because switch SB is still open. The current does not rise immediately, but rises gradually because of the leakage inductance of the transformer.

At time t2, the voltage across CB will reach zero, and the voltage across CA will be twice the input voltage. Until this time, the load current in primary B must be smaller in magnitude than the magnetising current, otherwise, the total amount of current that flows into CB will be positive, and CB will not reach zero. At time t2, the switch SB is closed, and remains closed until time t3. During this time, current flows from SB through the transformer into the load.

In the preferred embodiment in figure 1, SA and SB are surface-mounted MOSFET switches which have integral adjunct capacitance CA and CB, and integral adjunct body diodes DA and DB. The switches chosen, for an input voltage of approximately 40V DC, are 100V types, the peak amplitude of the drain voltage being only a few volts above twice the input voltage. CC is the input filter capacitor.

Very large die MOSFETS could be employed because the output capacitance is used advantageously. The gate-source capacitance, however, must be driven by the driver circuit. Smaller types are chosen by minimising the total of drive circuit dissipation added to MOSFET conduction resistive losses. Because of the smaller voltage stress, lower resistance FETS may be selected for a given gate-source capacitance. The Miller effect capacitance is ignored because of zero voltage switching, as is the Drain Gate capacitance.

The transformer T1 is spiral wound using multilayer printed circuit board fabrication techniques, the multilayer board being a single piece, containing all the wiring and interconnections to the components and comprising 8 layers. The multilayer technique provides tight control

WO 89/04082

<img file="AU613985B2_D0006.tif" />

PCT/AU88/00419 of leakage inductance and winding resistance, while the use of 8 layers 70 microns thick provides a large cross-sectional area of copper, while minimising skin effect. The ferrite core is assembled to both sides of the board, the core centre pole passing through a centre hole in the board and the outer edge of the board routed to suit the optimum shape of the core.

The transformer core shown in Figures 4A and 4B has been designed to minimise both winding pole 1 is very The diameter losses and core losses

Because the centre short its total volume is very cross-sectional small and hence the area is reduced to about half the cross-sectional area of the rest of the core .

The flux centre density in the relatively high, loss per unit volume in because of the small volume arising twice pole of the core as high as this centre is therefore the pole average .

is quite

The core high, but from the short length of the centre pole , diameter of the the power loss centre is low.

The smaller resistance can be pole means that the winding greatly reduced , compared to a core topology which has been manufacture, because there optimised is smaller for bobbin average path wound length for each winding turn, and more area on the board between the inner pole and the outer legs for copper.

can the

Co and D_qB on each secondary are vejpy^ designed for 20V reverse vpl'€age. be used because of the^-bdw^ voltage principle of opjslation is of-^ low equivalent to ,,ρ-fovide a current path of this series

Rectifiers D A o low forward drop devices

These optimum types stress provided by converter.

Capacitor resistance and serves inertial current of tjid output inductor LF during time. The select-ί''όη of need to ensur'd that value..which ensures ,.-''' Inductor the the

LF, the size of Co capacitor does above .

fabricated by for the the dead is determined by the not discharge below a attaching cores over

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<img file="AU613985B2_D0008.tif" />

The principle of this aspect of the invention is implemented when the centre pole is deliberately reduced in diameter, preferably such that flux density in the centre core is at least 35% higher than the average flux density for the rest of the transformer core.

Rectifiers D_qA and D_oB on each secondary are very low forward drop devices designed for 20V reverse voltage. These optimum types can be used because of the low voltage stress provided by the principle of operation of this conve rte r.

Capacitor Co is of low equivalent series resistance and serves to provide a current path for the inertial current of the output inductor LF during the dead time. The selection of the size of Co is determined by the need to ensure that the capacitor does not discharge below a value which ensures the above .

Inductor LF, fabricated by attaching cores over

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<img file="AU613985B2_D0010.tif" />

WO 89/04082

PCT/AU88/00419 multiple single turn layers of the board, and capacitor CF, form a simple output ripple filter to ensure very low output ripple voltage.

At tO, switch SA is on. Just before to, load current and magnetising current is flowing into switch SA. The losses on this MOSFET switch are now simply conduction losses. There are also at this time copper losses in the transformer, rectifier conduction losses and some stray resistive losses due to interconnections.

At time tO, switch SA is caused to turn off by the driver circuit. A small loss is associated with the driver discharging the gate-source capacitance. The transformer T1 has primary to secondary leakage inductance, and this inductance has energy associated with it due to the load current. When switch SA is turned off this energy continues^- to flow to the output capacitor, CO, and at the same time will charge CA, the switch capacitance of SA by a small amount., and discharge CB, the capacitance of swich SB by a small amount. At the same time the magnetising current will continue to flow in same direction and charge CA, the capacitance of SA.

Between time tO and t2, the primary inductance of the transformer T1 resonates with the capacitances CA and CB, the curve between tO and t2 being shown in the waveforms of IMA and IMB.

Because the capacitance CA is being charged, the voltage across primary A will decrease, and because primaries A and B are wound on the same core, the voltage on primary B will decrease by the same amount. There is a very small delay and a small, well damped ringing, due to the leakage inductance between the two windings of the primaries .

This means that Capacitor CB will start to discharge. Magnetising current then starts to flow between the two switches rather than between the input capacitor CC and either switch SA or SB. The magnetising current flows !

.,-J /

*

WO 89/04082

PCT/AU88/00419 in a positive direction into SA and a negative direction from SB. The voltage across the transformer starts to change polarity, so the same occurs on the secondary.

The voltage across Secondary B starts to increase At this time no current is flowing since the secondary voltage is of the voltage on Co and the forward rectifier, which means that Co starts to determined by the output current in a positive direction, through the rectifier diodes, less that the sum voltage drop of the discharge at a rate and the size of Co.

At time

B will drop on Then current will start to flow through the because switch tl, the voltage across secondary be equal to the voltage across Co plus the voltage the rectifier, rectifier B and primary B into capacitor CB, open. The output current but rises gradually because the transformer.

SB is still imine d lately, inductance of does not rise of the leakage

<img file="AU613985B2_D0011.tif" />

CB will reach

At and the voltage on CB will not reach zero.

before

The time t2, negative conduct, the is , , that the switch time t2, the voltage across zero, and the voltage across CA will be twice the input voltage. From tl to t2, the load current in PriB must be smaller in magnitude than the magnetising current, otherwise, the net amount of current that flows into CB will be positive, voltage on CB is thus reducing, and at voltage VCB passes zero and becomes before the integral body diode starts to

SB is closed, and remains closed until time t3.

The principle of this invention does not preclude of the integral body diode of the switches, however not used for the following reasons: The dead time longer than necessary as the VCB has already passed furthermore, to continue to achieve the use this is becomes zero , magnetising current must be sufficient magnetising current to oppose the commencement of and t2. Because the dead time increased so as flows through the the load current

ZVS, the to ensure body diode between tl is longer, there is either a larger ripple voltage on Co, or a larger size Co for a given output ripple. In other words, the period between t.1 and t2 is lengthened unnecessarily.

From the time t2 until time t3, magnetising current flows from CC to CB. Because of the leakage inductance between primary A and primary B, energy is stored in this leakage inductance due to the magnetising current. This current continues to flow into capacitor CA, charging it above twice the input voltage, so a small ringing occurs between the primary-primary leakage inductance and capacitor CA. This . .. ringing gives rise to some dissipation. The loss is very low, • · · * ** since only magnetising current is involved, and the leakage *····' inductance is very low. From the time t2 to t3, current flows from SB through the transformer into the load.

J .··. Ringing shown on the waveform diagram I A and IB

.. . is due to Co resonating with the leakage inductance of the • · · * *’ transformer. If Co is increased, or the leakage inductance of the transformer increased, for example by adding an extra inductor, the output circuit can be resonated so that only a , half sine wave is present as the secondary current waveform as * ' shown in I,A' and I,B'. If this option is followed, zero

I current switching of the output devices is obtained, and the , Electro Magnetic Interference of the converter is further ί·ί ·* reduced.

The ringing shown on I₂A and IB is non-dissipative, because it occurs between the two reactive ·;*··; components, the leakage inductance of the transformer and the

I*.*’. capacitor Co. The damping of the ringing is caused by the resistance of the transformer and the rectifier, and while the peak resistive loss varies over the time t2 to t3 between greater than and less than an optimum square wave, the average for the period is virtually identical. Experimental results have proven tht resonating the secondary current as shown in I₂A' and I₂B' made negligible difference to the losses.

VCO and VCO' represent the voltage present across capacitor Co in the cases corresponding to I₂A and l₂A'

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<img file="AU613985B2_D0013.tif" />

respectively.

On the curves, note that between tl and t2 there is an apparent power loss because neither VCB nor IB are zero. However, this is not dissipative, as at this time SB is open and the current is simply charging CB, the parasitic capacitance of SB.

It will be apparent that magnetising current can be adjusted to a desired level by means of a parallel inductance. It will also be apparent that the adjunct capacitance of the switches may be likewise adjusted by the addition of parallel capacitance .

“·'··’ At t3, the process is repeated in symmetry, as it »·***· does at tO, substituting SB for SA, CB for CA, etc.

,····„ Referring to figure 3, the overall efficiency of • · · · . .. the present invention, plotted against output current is shown.

• · · **** Two variations are illustrated, one optimised for 39V DC *· output, another for 5V DC output. It will be noted by those skilled in the art that the officiency is extremely high in both cases, even for loads as small as 10% of the rated load. This results substantially from the independence on load current of zero voltage switching.

• · · · • 5 · • · · • · · • · « • · · *

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