AU552003B2

Bowling ball path indicator with rom ball path selector

Abstract

This record has no abstract on file.

AU552003B2, drawing sheet 1 — Sheet 1 of 146

Term

Term ended

Expired 11 June 2001, 25.3 years ago.

1 claim: 1 independent, 0 dependent

1
The claim defining tbs- invest sen arc ?s f ©I lews:t* bowl leg alley including a pis spotter, a pm spotter ttee bowling ©f a first tab m a bwlsag Crane„ scans ssr selecting and Ularatafiss an ©ptxnur ball path and a ban «S3 • « «C © C .·.:O plo cafta input mans corresponding cne tc earn standing pin pcsitim ace ©n a bowling alley and responsive to tot pres^ccc and e a :absence ©f standing pins at said star-nri an pcsitmrg * generate representative first ana cc c state signals, respectively? read enfiy nemy ’canu having i plurality of address input roans cerrola^ei, respective .y. with said standing pin data mput rearo and censected tfcerc« V9 & i? 9· * OS a ·a 9«0 with to receive standirc pin mfsrratisr seyrcsontcd by a corbsaatien ©f said first and second leaie state signals 9 9 C » © #» · ♦ with said ©srbinatior ©f first and seccr.d Isaiz state enly rercry ecans? s^id csrbinatirns sf caic first and second logic state signals at ©ptiesr ball path far e^-'U said corbanatien;and outputs I ;i . b predeterrined enabling output for selectively enabling a ball path arrow on sai< pin spotter cask representing said *1 optiau» ball 'path. circuit insuring a proper tine delay for stabilis 25 mg data volcages occasioned by the presence of U Li - A8 ?. The options ball path indicator aeons defined in Slain 1, which includes a power source;and wherein said plurality standing pin data input assns comprises: a channel representative of each standing pin position data and an inverted second logic state signal thereon in response t© the absence of a pin at a corresponding said standing pin «eats in presence position each said data channel and responsive t© the for intercoenectiEg said xspedance neats with said second logic state thereto©» t© provide a cent iaat ion :f inverted channels standing with said plurality of data channels for receiving said ceatination of inverted first and second logic state signals., pin inforaation ato applying tne letter t© said address input neans of said real only eaaory sears. preceding claim, wherein eaid plurality of pin dats input means and said decoding and driving scans are both enabled and driving «eons is enabled cu: cogger· st *;sn t© said pin *a*a input cease. The ©ptisun tall pata indicator ceanc iefiued in /lata 1. wrica includes a source of rawer. and wter^sr. said decoding on.'-: trivini· ceanc ccapriscc. a decoder desaltiploxer for receiving ani converting mid cutpr* ’•©dr f*os said read ©aly aeaosy sxeans t© ar enatlmg cu*pu* signal at a peculiar one ©f a known plurality ©f enabling· ©itpu* /©rrespsndins* to one of a respective plurality ©f opt taws resolved tall paths;a plurality ®f ball path leap scans associated with a corresponding ball path on said p.r. cysttar eask representative of said iC2S^3Wa* plurality of ©pti-sua resolved ball paths;and a plurality of gate controlled switch means corresponding one t® each bait path xaap seano and a corresponding peculiar one of said known plurality of enabling output o of selectively interconnecting said ball patn leap aeano with s&id Gource of power δ© illuminate a ©orrcspcnding ball pats arrow t© define on said sask ©ptisun receive© tall rath c©rrespsnd-ing t© the said peculiar ©ne of said kn@wn pl*rali*y ©f enabling outputo bearish said enabling cutpi* signal- 6. She »Xptiona ball path indicator ©cans def m< ΐ in llaia 5» wherein said plurality^ standing με data mru* aeans ©««prises: a data channel representative of eacs standing pin position and norwslly connected wits oszd power source to preride an inverted second Logic state signal thereon in response to atser.ee cf a pm at a corresponding said standing pin pssi-.mn;a logic state generating aeons in each said data channel mcmdmg iaredance scans for selective interconne©*:.ien wit® cam source;and gate controlled switch aeaas in sacs, said seta thannel and responsive tc the presenxe Gf a standing a- a corresponding standing pm resit ion for intercome©· m ’ cam lapedance steas© wits call crirp 'g renorate ar. mver-oi first logic state signal m its eerrosj .memo cam data channel and reaave said invertei second Lcgi© state signal therefre® t© provide 3 cccbinstian of inverted first and second logic state signals m said data channels representstive ©f a standing pm pattern on sail standing pm p©Gi·ions;and inverter driver eeans cmnected with said plurality of data channels for receiving said rent mat ion of i&terei reG^3**se a standing pin rssiti.cn;a logit state generating aeons an each said data channe’ isciding .spedanc^ aeans is? selective interconnectmr. wi*n caid aotmae;and tre controlled suite neano „1 eaoa said data sia-vX and ing standing pc . t ion for x.n*e senna -with said co *e iterate «everted fir;state signal i*. its sorreeponline n.t data chance 1 arc *· ** 4t W a W * ♦ # »· < ? * *««» <« «Ο * ♦ a «»·« remove said inverted secant . c;«#»**a standing pin. pattern on sai’5 otantc * z eno;and *» * a ♦ *aa a. ·: Lara^.*y cf ;a*o .twr. * •-St and £5ec©s.j iocx s*ate signals, m. -’.a. c a W · * at * e e Λ «* for» said coabinaticn ©f firs* and © t . sc.. e representative of cats standing pin unfit cati n* pj» r ί&ΛΛ -2> a *e » a * :a;OQ« sentry seana •atst z-anc ofitez either xf laiac : e. 1b :. cwt and wtcreir said -*< ’ *dv and drivit sea·./ -c . . lecoder terclti·' sere«vine and ver* xc. - caxl 3»*et • an statist·'' r^tpsst nigral at a pt resreot xve is « e> e «·« o e. ball path of optima resolved ball patho;a plurality ©f laep weans associated with a corresponding ball path ©n said pin. spatter aa.sk representative of said known plurality of ©ptias® resolved hall paths;and a plurality of gate controlled switch seans corresponding one to each tall path leap aeans said, known plural i*y interconnecting said an.» a corresponding peculiar one of of enabling outputs of selectively hall path lamp weans with said scarce ©f power t© illuainate a ©©’•responding ball path arrow t© ieflne ©n ©aid aasfc an eptiem resolved btli. path correspond ·« a enabling outputs bearing said enabling output signal. The optima» hail path one of ’lain© . ?♦ % tr further includes & • e»to .. cp©t standing pin. indicating lasy w’*'. each of a standing t© illuminate a '©rrespendsns’· me ©f call standing pin (· ? i « : 6 » ' » a spot indicators lass -·, wherein said rsn spotter aask further includes a and standing spot indicates* for each standing pin position;pin indicating leap means associated with each spot indicator and responsive to the presence of a ctanding pin at a given pin ©pct to itHuainate a standing pin ij ?] si As can be seen fro® the foregoing « *·*» * *! * » corresponding one of said standing pin epot indicators. 1?. Zbe optiaux ball path indicator weans defined in. Claie !<?,. which further includes enabling weans responsive to a pin clearing and sensing machine cycle of said pin spotter subsequent to tne howling of a first ball in a bowling frame for gating said plurality of pin data input means and said decoding and driving means to respectively transnit and receive information to and from said read only ***** . * * ** ♦ » * m memory wans. 14. Use optimum ball path indicator weans defined in Claim 1’, wherein said plurality of pin data input means and said decoding end driving weans are both enabled in a finite interval in said machine cycle and said decoding said and diving means is enabled subsequent in tise Seta input means. © ***** © * « * ♦ * ¢- « a « *# * ** « * <·«· * * *»m· * ® Beans for determining a predetermined one ®f plurality ©f fescwn ©pt Ians resolved ball pat ns for ing pinfall in. any one of the entire range ©f potential ccnbsnaticns ©f standing pins ©n the standard standing pin points ©f a bowling alley, said seam 'comprising: data neans sensing a standing pin pattern and providing first and second logic state signals representative of the presence or absence of a standing pin at each of said standing pin points;a data caannel for each standing pin point receiving a ccrresponding «me of said logic state signals fro» said sensing eeans to provide a combination af first and second IS saxiei©·· l·' i ha - 55 logic state signals thereon;a read only ®e«ory means having a plurality of input address terminals corresponding one to each of said data channels for receiving said combination of , first and second logic state signals,with said cosbination of first and second logic state signals corresponding to a discrete address in- said read only aenory scans;said read only memory mans being responsive to each received ccmbinatiott- <*f said logic state signals t© provide a coded * »·* output representative thereof;and decoding: means having a V · * plurality of enabling outputs corresponding one to· each ©f ·***# **··* said plurality of known optieua 'resolved ball paths;said > W « *··♦·* decoding means receiving and being responsive to said coded ·’* * outputs· from said read only ®s»sry means t© generate an **.... . . • *.·» enabling signal on the particular ©re cf said enabling outputs corresponding to a prcdeteraineci one of said known * optimum resold. d ball paths peculiar t© the standing pin > a ♦ T»Z pattern sensed by said data neans. * ♦ » a V* « ifi. The wans defined in Claim 21, wherein each e a Z *··» cobbinatism of first and second logic state signals correiqpOflrts t© a discrete address m said read only r-€r.«. · r * «««««J scans;w* stein each discrete address in said read miy memo, · means provides a unique coded output;and wherein said decoding mans· converts known groups of said unique codec outputs to predetermined ones of said plurality of enabling outputs t© correlate a particular group standing pin .patterns with a known opt ism® resolved ball path. 17. An optimum ’ball path indicator means for a howling alley including a pin «.potter, a pin «potter mask having selectively Msplayabl* ball path indicators thereon, pin drawing·. ί ί β ι. Hji sensing mans responsive to pins, left standing after the 'bowling of a first hall in a bowling frare, weans for DATE© this '1 » selectively displaying an cptfeu.- tail path for the newling of a second ball » said bowling franc, a plurality of standing pin data input means corresponding one to each standing pin. position on a bowling alley and responsive t© the ft- ·♦ * ft ft· * ft ft ft 4 logic state! signals, respectively;a self-contained (os *wurs.nftMef<««ew^ processor maansjhavi^r a plurality ©f address input ocans correlated, respectively, with said standing pin data input * ft ♦ ft * · »** ft ft··· • • •♦ft ft ft ft ft ft ft · ft ♦ ft ♦ a «·♦*» • ♦ •seans and connected therewith to receive standing pin • ft ft « ft a a a infcreation represented by a coKbinaticn of said firs· j • ft» ft ft» ·«* ft •·· ♦ *ft •·· * *♦ V. ft ··· second logic states signals with each said anbwatn r ©* first and second logic state signals correspond!;· ? tu discrete address in saad processor reano;said precess ft ft* ft ft ft ·*· ft ft ft® • ft ♦ ft «0 ft • ft ft ft;state signals at said address input scans to provide an eptinun call path ft ft ft ft© ft S ft ft indicator;and decoding and. driving nears receiving uro responsive enabling a ball path indicator on said pin spatter nasx representing said optimum tall path. IS. An optiMrs ball path indicator rears substantially as hereinbefore described with reference t© the accompanying u

787 paragraphs in 10 sections, as filed

I i

I it-.„

«V W7 Vest chest er Avenue, Vhite Hains, Mew Tork IG&O^, United States cf Aaerica, hochy apply for ta? nwnr c:f a Pattsw for an m»vnt»n c^mlcd

whnh κ described m the κ.βηψηηίηκ: •«pc.dtaTisin

The appfcmcn c* a (omenoon apphattraa asci ·· ter^f dr appfoajtrn nunAened to a patcnx ·: tunibi pm&tMin made cn

Waited States of ««erica m *5*h Sue.©, 198©.

Cur addrew for wrote a (ALIIN'AN ami ASSOCIATES Parcrar Annmcyr of

48-50 Brds?f Real Rnhmrnd. Scare <4 Vtom Awwata

FATfNTS ACT 1982 taiW

«I

la w

Mi Bowling Ball Path Indicator with ROM Ball Path Selector

1/We f*l David Elwin Dougherty

>4ι Μ «ft*

af« Ravenwood Avenue, Weston, CT 06883 United States of Aaerica.

9» ntaanljr aed aaanerely decbae as foUam:—

«1 MB/wWwt a—he*—d by AMF INCORPORATED dK aiqriKMK .far the pMcm/pifi »f sil In·— m auie this dtdanta— — it* behalf, t «The heair i—Ιίπηη·»> m deh—i by Scoi— HI oi the Ao esii ή United States «a 30th day af June i$ 30 by Jases H. Multner a

4Hr«#a · * o

» Written Assignment dated May 19, 1980 froa said inventor to applicant

<td> (54)</td><td colspan="4"> BOflllG SALL PATH SMOISATOR wSTH ROM SALL PATH SELECTOR</td>

<td> OU</td><td> OF IHCCRPORATEO</td><td></td><td></td><td></td>

<td> 02)</td><td> JAMES H. M'JLTMER</td><td></td><td></td><td></td>

«74) €L <56> OS 34283U

OS 3341S3J (57) Claim

1» An ©ptfws ball path indicator reas*s ftr a toiling allay ittliding a pan isz.sz*·^, a r;? agzt*«r -as^ having selectively xlldrltatef bail giet arrzas t*orcxn, pin sensing reans respsnsave ts pars Lcf* starxan? after tfca btwlsr.g nf a first tall an a ts»Unx irire, -oano far selecting and 11 teaset xrg an £μ.%_· Hi. ?iv. and s sai. path arts» cerrespcxdsrs e?.e*o*’ izs tno kvadr? :ϊ a 3·?:ΐ’: ball xs said tolsng frar®, a ts«ra.a*y it 3’3».-» -. “ata input seas* ensrcspar.dur.? xra ti earz otard.rs jecn a bswlarg alley a*i rcsgC’G.v'v · ’ tne trnsorro ar i absence cf stardang pans at sa.x starl.T s η*η gxsat.x'-.s t. generate representative t.rst ari oc^xtu state

Signals, raspertitoly s read »nly vemy seans saving a

Sts

5,11^(36)0

plurality of address inpuu mans correlated, respectively, with s/aid standing pin data input reans and connected therewith to· receive standing pin inforaation represented by a combination of 'said first and second logic state signals with said combination of first and second logic state signals corresponding to a discrete address in said read 'Ohly «eawsRory means; said read only aesBOry neats converting cosbinations of said first and second logic state signals at said address input mans to an output code peculiar to an optima» ball path for each said cosbi nation; and outputs for converting a krowr group of said coded outputs to. a predate rained enabling output for selectively enabling a ball path arrow <w said pin spotter s&sk representing old

PATENTS ACT 1N2

71645«

···*

» * ♦ «»*» *··♦».

• 3

<td> » 59 • · O a e*o</td><td> TO BE COMPLETED BY APPUCAMT AMP ΠΧ2Ρ02ΑΤΕΙ</td>

W? Westchester Awnue,. White rleins, Mew 'fork 106M, wte(S states of Africa& M

CALUSUai AMD ASSOCIATES, Fatent Attorneys, off

48-SS Bridge Road, Richmond, Stat· of Victoria, Aestraiia. «BOWL»G ΒΉ& PATH IMDICATOft WITH 30ft

Cowtam Wkm tar *· taMba «Meh MIL ££EK SEIJSCTOH*

ftsoMhlE am a

u- ♦ «Λ * » « **» * ft·»* a ae * * a

FieU of title Saveption

This invention relates to apparatus for automatic bowling pit spotting mschine* and more particularly to improved apparatus £oz «electing and indicating to a player the. proper path along which a. .ball should be rolled xn order for that 'player to knock down the maximum number of bowling pins .

«»♦*»· ♦ « #* a * a ««♦

Jatwtica

The present, invention is an xmprovmant in ball- path indicating systems for bowling pin spotting aachina* of the type disclosed in U.S.

**·«« g

Patent .Wo. 3,212,779 to Grus* et al of October 19,

a ♦ »9

* % ♦ »»»

1965, for (1) selectively actuated ball path xadicwting system, U.S. Patent ho. 3,223,416 to

Blwwitt, Ur., Sacamber 14, 1965, and U.S. Patent **·*»· *

«••ft<a ♦ »

So. 3,460,132 to Blewitt Ur., of August 13, 1969, for (2) .bowling path indicator, and U.S. Patent ho. 3,841,633 to Walsh, et al of October 15, 1974, for <3/ bowling ball path indicator. These patent» ar* assigned to AMF Incorporated, The assignee of the present invention.

Such ball .path indicating system* generally include, for each pin spotting machine.

•swans, operative prior to the rolling of the ball

* ft* * ft ft ♦ft# ft *♦»♦ ft * •♦ft * ft* ft ft ft a·*· « ♦€*·«» ♦ ft ft* ft ft ft *♦♦ ft ftft**o * ft «· ft ft #» ft ft* * ft ft· ♦ ♦•ft ♦ ♦♦♦ft :

* Q & ft of a fra··# for determining the number and arrange· sent of standing pins» which means is associated with wans for computing and selecting the optiaun point of entry into an array of standing pins which the next rolled ball should take to achieve aaximo· scoring results. Further, for each pin spotting machine an indicator is provided, coupled to the computer which xs actuated to indicate to the bowler the optimum points so selected by the coeputer. ‘the bowler, by following the visual directions provided by the indicating systaw, rolls· his ball accordingly and xf las aim is true will, knock down the maximum number of standing pins· each time.

The foregoing sophisticated but highly desxrable ball path indication asd automatic selection of the ball path for xsaxiaited scoring has heretofore required a. central bail path computer for up to, for example, 50 individual

20- pin spotter machines and that computer acts to calculate a multiplicity of ball paths for a bowler at any given pxn spotter open the receipt of a. call signal and a standing pin information signal fjem that gives* pin spotter.

In the system of the 'Welsh et al ball paths resulting from, the various pexnuta- * 4» ♦ » a »»* a **»* *

• «« e ♦ e ·«·· a

eeee© on a bawling alley after the rolling of the first ball. By scanning the 19 possible ball .paths isa a predetermined sequence, the optimum path * #» * * w ♦ «· * <**· a»** # wa * ♦ e f ·«· . o «»»««> a a ♦ * a see xa the .scanning sequence

Further, In that scanning sequence ··*»» a © * c a a · ♦ «Ο information was brought into, the sequence scan.

»»«5 *

* 0 a a * a - • «» ‘ * · »·#» a *· a e «« »9 selector through 19 input lines, to a. diode logic ball path indicator relays which in turn are respectively actuated to illuminate a -particular characteristics diespite the fact that at any given time after a first ball has been roiled.

ft aseesy ♦ « a

• β·»· * ®

-*Γ”

there ere 1,023 poesible conditions of steading pie* fining on the bowling alley.

As can be seen fro· the foregoing discussion of the prior art, the requirement for a centralized computer, scan sequence· selector.

and. reeoltant wiring and interconnection and

<td> * e* * « w **-· * * «»♦· « * ®</td><td> sapsUble signal exchange between the-, scan selector, central computer and all of the pin spotter units in ao. establishment is λ camples</td>

<td> ♦ *#» ¢. ♦ © >· e · ή ·»«</td><td> 10 and softdabkaHad. system. Accordingly, there is a .standing, mad long-felt need m the art to simplify the equipment providing the highly desirable</td>

automatic ball path indication function together with indications of remaining pins standing after the rolling of a first ball.

a • ##ae » »

It Ms, therefore·, an object of the present invention to provide a simplified ball path indicating system for automatic pin spotting macmnes which obviate* the need for a scan sequence 20 selector and central computer.

aneaher object o£> the preaent inven· tzon is to provide a new and novel^b^llpath selector system. for automatic gid spotting machines which is seif-contained within the individual pm spotted and which requires no external coatpdl circuitry to effectuate the

- due lied i1^dXxatlw,~-trf*elm^^ .....and.....standing1 pram·.

I

?e

Ί general t/ypa which spot and. re-spot pins, remove bowling pins from the bowling alley deck, -and which operate in accordance with the various ball cycles

Congress.

possible ball paths which can be rolled, combination and. these, pat&s have sufficient overlapping' characteristics ';,he rolling of a mil there ultimate number of resolved resulting froa along such that the optimus ball paths •st·?» e e » * a c a © ® eer ♦· ft e . eeea >

w ft ft ft a & » is reduced to 11 that aay be.

is thrown.

possible is ling combination nay have one ball paths as previously discussed. The memory

-equxrements, therefore, to properly manage. such •c

The above identified Walsh et al patent is incorporated by reference herein and all of the other prior patents noted above which are alse incorporated by reference to the extent required, provide the mans to define the various pin combinations ard the resulting bail e* e a o a· a

« * * 9 invention is to set up an addressinc system and store the « e e ·♦ ♦

«* a a *

proper ball path at characteristic of a each address location which particular pin combination is

For this pcr::'.-to-, the present invent ton hereinafter referred to as the uses a read only

SO». The FSM is

Kessory# preferably «* a v « « *3 a separate item but the StO8i in a self-aontaaned means my also be util toed. The ROM as a bin - -y device bavins only too unique logic states, namely, cne and aerc, ccmbi ned with which a weighted system of address inc ant outputs is used t© define the total number rf ccmbmatiano that ©ceur. This weighted system io defined m the ♦

.. ,: following fable:

» ·

cm aedmessing giipurs;

♦» e «ft

<td></td><td> Pin</td><td> Address</td><td> Binary</td>

<td></td><td></td><td> Lins</td><td> Weight</td>

<td></td><td colspan="2"> TOTAL COMBINATIONS</td><td> 1,023</td>

<td> 15</td><td colspan="3"> The 1 324th combination is all zero inputs</td>

<td></td><td> > a strik&i.</td><td> Thus, only 1</td><td> ,323 address positions</td>

<td></td><td> are required</td><td> as a unique</td><td> address in the ROM</td>

<td></td><td> aemcry. The</td><td> HOM address</td><td> is formed by adding</td>

<td></td><td> together the</td><td> numerical we</td><td> ighted value of the</td>

<td> 20</td><td> standing pins</td><td> By way of</td><td> example, the following</td>

<td></td><td colspan="2"> table is illustrative:</td><td></td>

<td> Pins Standing</td><td> weighted Value</td><td> Address</td>

The ROM outputs ere four weighted, data of which only 11 are used consistent with the ntebtr of resolved ball paths which have been found in the art to properly define the desired ♦» O' ♦ 9© ♦** © # -· Ο O to be rolled in correlation with, the various possibilities of standing pins renaming after a first bail has been thrown. The following table illustrated the ROM outputs correlated with the ball path arrows· which include .their path designations as suffixes, either as single pm suffixes or ® · ft · - s c ©

Q c sulti-pm suffixes illustrating the LL mtiaua resolved ball paths known in the art. The ROM in the following table to preclude confusion -r.

this regard:

ROM OUTPUTS

MSB i4 S 4

1S8

2^ 2.

a 2 1

Assigned Bail Path

Arrow IS

Arrow v2::

<td> ®4 S</td><td> °3 4</td><td> 0«. 2</td><td> X L</td><td> Assigned Ball Path</td>

<td> a</td><td> 0</td><td> 1</td><td></td><td> Arrow (3></td>

<td></td><td> 1</td><td> ©</td><td> Uf</td><td> Arrow ¢4^</td>

<td> 0</td><td> a X</td><td> 0</td><td> β</td><td> Arrow ul - 2</td>

<td> 0</td><td> 1</td><td> R X</td><td> Πί</td><td> Arrow C65</td>

<td> 0</td><td> 1</td><td> 1</td><td> * A</td><td> Arrow m</td>

<td> 1</td><td> 0</td><td> 0</td><td> s</td><td> Arrow t,l - 3B</td>

<td> 1</td><td> a</td><td> 0</td><td> Λ.</td><td> Arrow C2 - 45</td>

<td> 1</td><td> 0</td><td> 1</td><td> 0</td><td> Arrow ¢131</td>

<td> x>.</td><td> ©</td><td> * Ai</td><td> 1</td><td> Arrow ¢3 - S»</td>

<td></td><td></td><td> After</td><td> the</td><td> pin data has been inputted</td>

<td> to the</td><td colspan="2"> ROM memo</td><td colspan="2"> ry and the resulting logic outputs</td>

have been effectuated, a decode demultiplexer receive» these signals and converts the binary output fro· the ROM lot® a unique output for every combination of inputs such that standing pin indicator lights and ball path indicating arrow are illuminated on the pm spotter mask amt

Detailed Description of the Drawings

Referring to Figure I, the pin specter control chassis 10 of the present invention is shown as including a RDM printed circuit card

PCI, a computer ca*. signal printed circuit card PC2, a pin data printed circuit card FC4ff a XX or master relay means, a dummy hall pare, plug 3FP interconnecting the pm data card FC4 through, the master relay 33C mt© the MM inputs

1© 1?. . . 10P to thereby place ;he standing pin information at the input side of the RDM memory in the ROM card PCI. The ROM card outputs BAI . - . SAIL corresponding to the -. call path arrows m the mask unit - are connected thcxrugh me output

IS interconnection device FM to suitable -nteromnac-

after more

1*2 the So. 11 pm mdicator larps on the rasx 12 as will also he acre fii-y fesocmei heremafter

IS.

RDM printed circuit card FC1 is shown as including terminal pms 8 tnrough 1 ’ correspsnimg.

respectively„ to the So. .. mrcugh the 5»o. 12

ί f-. ii μ

il l· * ** ft * ft 'ft# ft ft ft ft· ft ft > ftftftft ©

♦ **·*♦» ft e ft* ft * ft ftftO pin 1BP, th* designations 2? through 10? comprising the inputs for the pm data derived' free the gripper switches 3S1 through 3S10 scheeacicalZy illustrated in Figure 2A.

The dussy ball path plug BPP includes ten connecticns £16 through £25 which correspond, respectively, to input terminal piss connections S through 17 and inputs 1? . . . zap of the RDM 'printed circuit card PCI.

The. master relay KX is constantly engaged -through a terminal pit. £4 on th® ball path plug BPP «eeeably which connects to ground through another texainal pin £29 :.r the call cash ft O » ft ft ft * ft ft ft* ft ft* ft ft * • •♦ft »

··*·« n * o •

-«♦ft·· ?

♦ e plug asseably BPP. The pm £4 is connected to the catbod· side of an isolating diode MR58 -n series with the winding af the relay XX, the latter being connected at -ts ippisitc end ts a plus 13 volt sen®». A shunt disde *R2A is connected, in the reverse direitijr across the winding of the relay XX as ,s »e·. <nuwn in the art.

As farther illustrated in Figure ZB0 a plurality of sis data .ines ¢31 . . . ¢312, corresponding, respectively, to the first through the tenth pins and the gricy *r «witches 3S2 . . .

GS1@, are correlated with terminal pins £9, £11, £8, £22, E”, £13, ES, £24 „ £5 and £21 white are

X.s.

- 13 respectively shunted by jumpers 31 through

JIG to the terminal pins. SI6 through £25 cm the previously described half of the. dwy ball path plug ass—bly 3PP. A -n—rn ground connection between the terminal pins £27 and £29 on the. .ball, path plug assembly £PP is indicated as a jumper jg.

»»«

Therefore, to summarise, the ball path plug -assembly 1PF interconnects the pin data .lines PD1 through PD10 to the ROW card inputs

IP' through 10P, respectively.

The pin data, lines Phi . . . 2310 are sees# ® e e © c © <* a>

so «5

C*·» «s*»s * o ft eeaab > & ΐ connected through, pairs of relay cantacts of the master relay .means XX., where the relay XX is included, in a given automatic pm setting machine nr through direct lines, to- oomfem sensing terminals RBI . . . RB1Q through, respective coupling diodes MRD1 . . . connected in the forward direction from the ball path plug pms to the- said

c.aamen sensing junctxsns RBI . . . RB10.

Where master relay means XX is included m a given pin spotter chassis, contact numbers and 12 are in the line Phi, contact numbers and 16 are in the line- Ph2, contact numbers.

25- 9 .and 13 are m the line. PO3, contact numbers 17 and IS are in the line PD4 * contact numbers ”* th

WMMfel wms—*'

- 14 and and and δ .are in the line Pt>lt contact* numbers 21 and.

are in are in the line PD9, and contacts numbers and in the line· PUIO

The

RB1Q are. located, respectively, in . 1010 on the cathode aid· of coupling diodes MBD-l .

β9·«Β » ♦ « « a e« anode side of 'the «aid. coupling diode* being'

LSI through LD10 to the pin lamp* PH through

PL10, respectively.

through number 10 pins on the bowling alley associated with the pin spotter chassis.

e co e « c e a e a

PHO are connected in coaaon to a 12 volt filtered supply through a terminal pm 21 on the main interconnector and thence through respective through LD10, respectively,

ft •7

I

* IS rempectlwaiy , to the output· BAI through BAI1 from 6m BOH printed cixantit card PCI.

£h thia regard the. nain interconnector tn ha» tte ball path lamp» BPL1 through 1^111 ceBM0tftl rampactively with connector pin*

Μ, Μ» W. Ill» 2X5, 213, 110, 23, 27, 212 am* M together with output terminal pis· 22., 24, ft ft ft ft*#·

*$** **♦* ft ft* ft ft ft

M*f*9 ft ft ft* ft ft ft

36, 36, 23, 31, 21, 21, 25, 30, and 27 of the ROM printed circuit card PCI.

The ROM. printed circuit card PCI *1*0 include· a ground pin X -and * plus 10 volt pin Wo. 2.

Mjmmmt «mob bail path bap 3HJ thsou£s BK2 is ft •ft···ft &

ft- ft# ft ft ft ♦ ft* a subscript which indicate* the number of individual lamp· connected .in parallel to constitute a reepective full arrow illumination for a ball path indication. For exmple, the ball path Laue*

3ΡΣ.1 through BP14 each consist of two leaps m parallel m a preferred embodiment, the fifth ba 15 path lamp BFL5 haJ 4 bulb·, the sixth ball pat lamp BPX.6 .ha* 2 bulb*, the eighth, ninth -and eleventh ball path imp» BP18, BPL9 and BP111 have 3 bulb· each, and the seventh and. tenth ball path lamps

1PL7 and BPL1Q have. 1 bulb .each. By correlating i 25 the subscript· adjacent each of the lamp* BPbl i

Φ »* * * a e

me a *<*Ti *♦ * · · ««♦I a

aesas e a ee * ♦ w *«o ιβ a o * as * a g ο» through a pin information coupler PIC or input terminal. device PIC to a plurality of identical a *· « * a a*·· sensing circuits which will be· described as typical

GS1 and GS10 .

««««*» « &

Wf erring so the gripper switch. SSI, it can be i«tn that one side of the grippar «witch is grounded while the other side is connected directly through a resistor R< to the base terminal of a transistor Cl and thence through a resistor

R3 to a suitable bias voltage# minus 6.® volts

a plus IQ volt supply in er—ion with <11 of the emitters of * plurality of transistors “1 through T1Q. associated, respectively, with. the. gripper swit— 0*1 through GS10. The collector of the. traesistor Cl, which is. a ?W transistor is a ee < « « eee « .* «**» o ** ♦ V s »»♦ a g .. a a e* e » « ee» c—statd through a resistor R2 and hl to grouad with, ths 'jumction between the resistors hl aed

ί. through < capacitor Cll and.

silicon control rectifier SCSI. The silicon control rectifier 5^*1 has a capacitor Cl shunt across its anode and cathode taxmiiials with the. cathode terminal of the silicon control rectifier SCR1 ©

*«***· £5 being grounded and the anode being connected * *e see * ** through a resistor R48 and- isolating diode M5D1 «4**· to the first pin lamp data line PLD1.

A co—os output connecter PCC xs provided . » with a plurality of terminal pms thereon correoeso * * · * a ,,w: 20 1«tad to each of the pin lamp .data lines. LD1 through LO10 and the corresponding common sensing junction» Ml through M10 therein.

Similarly, for the gripper- switch GS10 for the So. 10 pin, one side of the GS10 is grounded while the other side is connected directly through a resistance R21 to the. base terminal of a PXP

I

- It transistor T10 while the base is connected through a resistance »22 to the minus 6.3 wit supply. The emitter terminal of the transistor T10 is- connected to the plus 10 volt supply » XCX1· t». collector xs connected through a resistor 123 and »24 to. ground. The:- junction hMEMSSK ths resistors »23 and 124 is grounded through a capacitor C20 and conaected directly to the .gats, terminal of a tenth silicoo control rectifier SCJtlO idiich is .peculiar to the tenth .pin·, co the alley associated with th® pin spotter table ftT and., the. gripper settcbes. GS1 through GS10« The silicon coatrol rectifier e»»t9 a © o

« a * « & a »

SCX10 has its cathode, grounded, its anode shunted 15 to ground 'through a capacitor CIG and its anode· connected through a resistor »49 directly to the data line WIG of the pm lawp PH© as. well as the common sensing *unctxoo »B1G therein. This connection xs effectuated· through the common aut20 pat coonecfdor VCC* Thus, similar SC& trigger

circuits are provided, for each, gripper witch in the tan gripper switch array 081 through 0810, respectively. Accordingly, when a gripper switch is closed, its respectively associated transistor 25 xs caused to conduct which causes· a bias potential known automatic pin spotting machines of the

to .he applied to the gate of the SCR associated therewith, which fires and draws currant from the plus 12 volt filtered supply thorugh a particular data lime LSI through LDXO to illuminate a particular pin lamp PH through PbllJ. and maintain the. SCR. in its conducting condition until such tims as «sternal means axe applied to extinguish * 4* « » Λ a e a e a «•»9 e a o * e « • ••3 β · · ο ίο

SO e o • i ©' « « · t » »s

a e

th· particular pin indicator lamp ?L1 through

FXJ.0 (i.e., the filtering xs ramoved from the plus 12 volt lamp supply extinguishing the pin lamps whom th· voltage -goes to zerol.

To.- complete the description of Figures

2A and 2B, a SK gate input terminal pin 5 is provided at the input terminals of the BOM printed printed circuit card Rd which xs connected by a set signal lead SSI to the collector of an NFS transistor T14 having a grounded emitter and having xts base, terminal connected to a logic input function Ul, the latter being connected to the minus 6.8 volt source through a. resistor R5C, through a resistor RSI to a first status input

81, and through a resistor R5-2 to a second status .input 82, the status inputs SI and 82 representing various conditions of the pin «potter being monitored a* will be hereinafter more fully described.

Φ **»·* a e » * * * · e ' ««««

- 20 Further, the icjic sensing junction. 1*31 is connected through a resistor 353 to the collector of another XPN transistor T6 which collector is connected to the plus 10 volt supply through a resistor R54. The. emitter of the 'transistor

T6 Is itKOunded and the base of the transistor T6 is ncHMWtcted to a second logic .sensing junction U2 which is connected through a resistor 355 to e

the. Minus 6.3 volt supply, through resistor 356 to a £hird status input S3, through a resistor

357 to a fourth status input S4, through & resistor 353 to the first, status input 51 and through a resistor 359 to the im&soA status input S2.

Thus, the transistor T6 is connected

IS tn a JSOR gate configuration with its various resistors ar.d inputs and thence controls an or-not gate configuration comprising the transistor T14 and its various resistors and status inputs. These two- gates act together to provide a set

2G signal input broadly identified m Figure 1 as the SET gate input of the- printed cncult card PCI and- also identified as the SET gate input of the printed circuit card ?C1 m Figure 2B, with the SET gate signal being accoeplished through the input terminal pin 5.

- 21 In sensing ths nput conditions of an associated pinspotter, the status inputs SI,

S3, S3 and S4 are defined as- follows, with logic values correlated to degrees of rotation

S of the pinspottar machine table for the first two status inputs SI and S2, the presence of a normal /abnormal cycle for the third status- input S3 and pits present for the fourth status- input S4.

SI * G For Pinspotter Machine Table Rotation 260® - 3500 » 3 For Piaspotter Machine. Table Rotation

660 - 186® « * For a normal cycle ae.g. absence of off- center pins no' fouls or pinspotter machine table) · 1 For any pins present on the ptnspctter machine table.

Under other than specified conditions.

respective inverse logic values prevail for

SI, S2, S3 and S4.

Referring now to Figures 3A, 33, 3C and 30, a preferred embodiment of the printed circuit card FT1 including the ROM memory for the ball path indicator of the present invention will now- .be described cosaKencmg with the inputs IF through 1GP corresponding, respectively, to input terminals 8 through 1 together with the SET gate

5, 8

4. Ί, 6, 10

16*54*128

8*64*22 *512

208 * 616

- 22 this ·Ό·ηεη bank of input, connections to the output connections 3A1 through 3A11 previously described with respect to Figures 2Ά and 22.

Input terminal pms 8, 9, 10 and

S 11 corresponding, respectively, to input terminals

IP, 2P, 3P and. 4P of the printed circuit board

PCI are connected through the reverse conducting direction of isolating diodes €21, €22, €23 and €24 respectively, to terminal pins 2, 3, 6 and 7 of 1C an optical coupled S3. These terminal pin connections of the anode* of the isolating diodes €21 through €24 coupled to the cathodes of individual Light emitting diode* illustrated at LED1 which drive light sensitive photo diode or switch LSTL to optically couple an input tics of a particular standing pxn renaming m the alley after the first ball has seen rolled. The various —ght emitting diodes within the optical uuupler 13 nave a driving bias applied thereto fro© a first LSD driver circuit L’lA having output temma- pms 2, 4, 5 and 6 connected, respectively to apply driving bias voltages to the input terminal pins 1, 4,5 and 8 of the optical coupler w »

The first LSD driver circuit 01A also has an output terminal pin 3 which is connected, t©

- 23 supply driving· bias to the terminal pin 1 ©f a second optical coupler 04 which includes an .LCDS and a light sensitive transistor 0ST5 by way of illustration.

S An additional or second LED driver circuit ©13 has terminal pins 3, 4 and 6 connected, respectively, to terminal gins 4,5 and 8 of the optical coupler C4 to provide driving- bias to the. balance of that circuit while a. third optical

IS coupler 05 is .provided having an L£S9 and. an associated light sensitive transducer 2ST9 corresponding to the input terminal 9P with the second ISO driver circuit 013 having terminal pins 2 and 5, respectively, applying bias to

IS input terminal pms 1 and 4 of the said optical coupler 05. This completes the driving bias circuit for the optical couplers 03, 04 and *S.

The- remaining input terminals 5P through

LGP are connected through isolating diodes 035

2© through CR10, respectively, with the terminal pins 2, 3, 6 and ~ of the optical coupler 04 and terminal pins 2 and 3 of the optical coupler 05. The· emitters of the various light sensitive transistors such as LST1, LST5 and 2ST9 are all connect.ad to ground through a common lead <32.

•connected to the terminal pins 16, 13, 12 and 9

of transistor Q2 of the PSP type whxch: is connected. at its emitter to the 10 volt power supply by a coupling diode CRH conducting into

IS the ssrittar. The. base of the trans is tor Q2 is connected through a resistor 318 o the- plus

IS' volt power supply and through a resistor 317 and the forward conducting path of a coupling

diode CR12 into the collector of an SPS transisi.tr IS 21» the. latter having its emitter connected to ground and its base connected through a resistor 313 to ground and through a coupling resistor 312 to the texairsa^ pm 13 cf a S23 gate module 714, the Latter having ganged terminal

2S pins No. 11 and 11 connected in ccwacn to ganged terminal pins 5 and o of a SC3 gate ocdule 212 and terminal pm 11 of the !*©R gate nodule T12.

The SSR gate nodule 312 has terminal pans 8 and 9 ganged together and cmnested through a resistor 314 to a S volt ’supply, through a capacitor 238 to ground and t© the set gate

- 2S terminal pm 5 of the moat terminals of the printed circuit beard ?22.

Terminal pin 1: if the NQR gate nodule

U12 is connected t© the panged terminal pins 5 and 6 ©f that nodule? terminal nm 4 ”f that .module is coanecued to panged terminal pins

2. and 3 of that module; terminal pm 1 of that module is connected t© i resistor RLS to terminal pin 12 of that module, the latter being connected to ground through a ©apacitsr 21 and terminal pm of that module is connected t© pangod re

Ό**

the sc ar d Fll., the input terminal pin 2 m connected t© the plus -Z ©©it suppli and thence t© the terminal pm NS. 2 ©f a voltage regulars© acdu*e '2' having a terminal pm 3 ©onnected t© jrcund

<td> and a terminal pm 2</td><td> ©mnecteo t</td><td> * la, * «»' V «> W lC</td><td> 1 . <s</td>

<td> 5 volt output across</td><td> a ©apacitir</td><td> 1 whxch</td><td> IS</td>

<td> connected ta ground.</td><td></td><td></td><td></td>

<td> The my ©t</td><td> termma*</td><td> » & 9» >»Λ ** tu vxf</td><td> »· e ·*( *»</td>

of that module whim are further rmreoted t© a

?Γ ’

* * * ♦ *

* ♦ *r < * 9 ©

»9»·»ς * ft «« * * ♦ 9 ft 1 ft ftftftfe. 4 * « * ft ft

9 ft

W ft* ft «ft C ♦ ft *♦·*

- 26 Mo. 4 of the MOR gate module 713 is connected to ganged terminal pins and 3 of that nodule: a terminal pin 1 of that module is connected through a -e*s -r R16 to the terminal pin

12 of that module, .and to ground through a capacitor C3 and the remaining terminal pin 13 if the MOP gate module CIS is connected to ganged terminal pins 8 and 9 of yet another MOR gate module Uli.

Pm Mo. 13 of the. MGR gate module

U12 is .also connected to pins 8, 9, 11 and 12 of yet another NOR gate module 78 to complete the interconnections of the nodules 712 and 713 with the balance of the circuit of Figures 3.

Three N©R gate modules 26. 7’ and 48 provide an intricate connection between the optical couplers 73, 74 and 75, respectively, with the R2H memory chip 415.

ft ft « ftftftftftft *

The optical coupler 73 has output terminal pins 15, 14, 21 and 12 connected.

respectively, with input terminal pins 8, 22, 3 and 6 of the KSR gate module 76. Terminal pin of NCR gate module 76 is grounded while terminal pins 9, 12. 2 and S are commonly driven by the terminal pm 23 ..f the K73 gate module 78 responsive ts the output from terminal p Xft atO· ii k-

A

the SOR gate 3®dule 012 as will be- hereinafter more- folly described.

Optxcatl coupler 04 has output, terminal pins 15, 14, 11 and 13 which drive, respectively, input terminal pin numbers S, 11, 3 and 5 of the 43ft gate nodule C“, the latter having its terminal pin 9 driven by the tenainal pin 10 of the module 08 and its teramal pins 12, and 5 driven by the terminal pin 13 of the nodule 08, also responsive to the output from id» terminal pm 13 of the nodule 012.

Terainal pin nunbar 2 of the module CT is connected to ground .as is terminal pin number * of the nodule OS. The optical coupler OS has output terminal

IS pins nuadser ~ and number δ which drive terminal pm numbers 3 and δ, respectively, of the KCR gate module 08, the latter having its terminal pins

90» and 5 jointly driven by the ; -n r.usber 13 of the module 03 responsive to the output at tesrmal pm 13 of the module 012. A NCR gate driver circuit 02 is provided with its terminal pins 2, 3, and 4 connected t© a plus 5 volt source and its terminal pin 14 connected to a

Im* 3Pta through BPL11 which correspcnd.

e «»β *l*o utilised m similar fashion. by capacitors not shown connected to corresponding plus 5 volt biased terminal pins on nodules CJ6 through 016 as will be described with respect to each of these modules. Thus» the capacitor C4 iv a typical connection. Terminal pins 7, 5, 1 and 6 of the module 02: drive terminal pins 8, 11, and. 6, respectively, of the nodule 06. Terminal pm* 8, 10 r 11 and 9 drive terminal pins 2, 11, and 6 of the MOR gate module 77. Tarainal pins and 12 of the NOR gate driver circuit 02 drive

IS terminal pans 3 and 6, respectively, of th* NOR < * · ♦ta a »

« e « « «»«· »*««# w «

4»* * a « asses· »

» * a «

gate nodule 08.

& ae « a « «***

The. output sides of the terminal modules

06, 07 and 08 are shown as including terminal pins having a plus 5 volt indication adjacent thereto.

These terminal pins 14 are each provided with a decoupling capacitor similar to the capacitor 04 for the NOR gate driver circuit 02.

t·«*«« * *·

The NCR gate module 06 has output terminal pins 10, 13, 1 and 4. which correspond, respectively, to ROM CPROH) input terminals pin numbers 5, 6, 7 and 4, respectively, which provide

* wn a * φ «#♦ · *

* <» » a e «·♦ ♦ ••tw * ♦ e* * * ♦ to# «•I»»? ' a o ea • « » « a* « « * * ♦ · *«*« £#»#»» * · # βί·»»ί » * designated inputs AQ, Λ,, A2 and A^, respectively, to ths MOK (PROM) U15. A ground terminal pin. number a is also provided in the RON: (FKN) S15.

The NOR gate, module 07 includes outpet ranaiaai pin numbers 10» 13# 1 and. 4. which drive input terminal pin numbers 3# 2, 1 and 15# respectively,, of the ROM (.PROM) 015 thereby providing the respective ROM (PROM) inputs

A*, A^, A$ and and the NOR gate module O* has output terminal pin. numbers 1 and 4 which correo|wn3 to input terminal pin numbers 14 and 13# respectively, of the .ROM. (PROM) 015 thereby providing ROM. (PROM) inputs A3 and A9, respect- ively. ’

Several different versions of ROM (PROM) nodule ’J15 can be utilised such as, for example, a 16-pin ROM (Signetics 8223 (16 pin) ROM (1024 x 4) 4096 Bipolar I Package) which is designated by the plain terminal pin numbers, or an 18-'pin PROM {Signetics 825136/137 (18 pin) PROM (1024 x 4) 4096 Bipolar F Package) which is designated by the parenthetical pin numbers in Figure 3B. The preferred ambodieant will be described with respect to the ordinary terminal pin numbers and the. parenthetical terminal pin

- 30 nnUMvrs be permitted to speak fer themeelves.

The MH (PROM) also includes the terminal pin number If which is a plus 5 volt bias, terminal * #>

* * e

4*· e ···» »4«t * ♦* * * * ά

* o * «·# e »««« * ♦ < *♦ e # ♦ * ee o H ·» * * #»«Λ which, as previously described with regard to the

S WCR gat·: driver circuit U2, will have a decoupling capacitor connected between that terminal and groumd.

The. ROM' (PROM) will have four outputs * ®2* ^3 aad G4 respectively , to output terminal pin number* 12, 11, 10 and g.

These output terminals 12, 11, 10 and 9 of the RON 015 drive input terminal pins 23 22, 21 and 20 corresponding, respective!./, to the A, 3, C, D .inputs'' of a. decoder/demultiplexer ©16 where A comprises the least significant bit (LSI) and the D ίη>Λχε comprise* the most significant bit ifSBJ. The decoder/damuitiplexer C16 is provided with a grounded terminal pin number 12 and. with first and second gate terminals G1 and G2 ganged together by terminal pins IS and 19 coemonly connected to the output terminal pin 10 of the SJOR gate module Gil. The decoder/demultiplexer U16 has a terminal pin number 24 connected to the plus 5 volt source and this terminal pin will have a decoupling capacitor connected to ground therefrom as previously

- η described with regard to the NOR.. gate driver cinsait 02.

A terminal pin 1 is an unused teixiaal pin in the decodar/deeulripXexar 015 while a terminal pin 2 comprises an output number 1 for the dooodar/demultiplexer. Outputs 1 through 11 oocsempomd to output terminal pins 2 through 11 a 13, respectively, of the dacoder/dmmultiplexer OK. Unused outputs 12, 13, 14 and 15 correspond to unused terminal pins 14, IS, 15 and 17 άλ shown.

The outputs from, the decoder/denul tipi alter U15 are coupled to ball path arrow enabling circuits by means' of NOR gate nodules

IS 09, 010 and Oil which, will now .be described·.

The NOR gate nodule 1’9 has a grounded terminal pin number 7 and a plus 5 volt connected terminal pin number 14 which is provided. with a decoupling capacitor in the manner previously described with respect, to NOR. gate driver U2.

'The NOR gate modules U1Q and gil also have similar terminal pin numbers 14 having a plus volt supply connected thereto and also being provided with such derailing capacitors.

Output terminal pins 2, 3, 4, and 5 ar·' connected, respectively, to ganged terminal

- 33. ο* * ,4 *»♦ * Η β «·* # # *9 ♦ S © ο capacitors C27 through C37». respectively,, to coeplete the ball path arrow energiiation circuitsAs previously described with respect

5. to Figure 2S, the output terminals BAI. through •All, correspond to printed ciz-cuit .board PCX ougpmt terminal pin numbers 22, 24, 26, 29, 23, 31, 26, 21, 25, 30 and 27, respectively. The particular ball path arrow legend corresponding to these pin numbers and to the outputs BAI through .1*11 are Hated in Figure 3C to the right of the said terminal pins.

This cewpletes the- detailed description of mtexconrections of' Figure 3.

1S iteration of the Invention

In the operation of the present invention, the pis fall and ball path indicator mask 12 in Figure 1 bear the same identifying numerals for the standing pins as the pin lamps

PL1 through PL10 and for particular ball paths by the. .ball path las© numerals BPL1 through

33111 in correlation to the legends printed' next to these respective lamps in Figure 2B.

For the sake of illustration, the operation of the present invent ion will be input terminal pit 5.

- 34· described on the assumption that the first ball has just been roj.led and that the No. 1 and. No. 2 pins remain- standing as indicated by the standing pm indicator lamps PL1 and PL2, respectively.

Xt is further assumed that the pm spotter machine has been actuated and the machine cable carrying the gripper switches GS1 through GS10 of Figure 2A has been actuated through its 250° position in. the. first ball cycle and has picked

IS up the No. 1 and Xo. 2 pins m its grippers, a* -well known in the art, thereby closing the gripper switches GS1 .and GS2. The remaining gripper switches GS3 through GS10 remain open.

*hen. the- machine table advances to the

260® position m its cycle of operation, the

SET GATE signal goes from a Lc state to a Hi state by virtue of the status signal SI driving the base of the transistor T14 through the resistor

R51 thereby turning the transistor T14 off to

2© raise the potential of the SET GATE pm No. 5 m the printed circuit card FC1 to a Hi logic voltage.

This results m the Nos. 3 and 9 terminal pms of the NCR module SIX to receive the SET GATE signal as illustrated m Figtires 3D and thence 25 through the output terminal pin 13, and the Nos.

11, 12 and 13 pits of the Norgate module 014, to y'*·’ input at 5, the- plus 10 vol* dc applied, tn pin

2, and grounded input pm 1 and will commence from.

~ 35 drive the base of the transistor QI. by means ©f the input resistors R12 and »13.

When the transisctr QI is turned on, tMs causes the transistor Q2 to turn on through the resistor ®1~ and the coupling diode CJU.2. As a result, the transistor Q2 turns on the light emitting diodes m the. optical coupled 03 which are coupled to the terminal pins 1/2 and 3/4 corresponding to the So. 1 and No. 2

1© pin input 1? and 2Ρ of the ROM circuit card PCI.

These LEDs, comprising L£D1 and L2D2, the latter not being shown, are caused to be illuminated due to the turning on of the controlled rectifiers SC3U and SCS2 on the printed circuit card PC4 cf Figure 2A in response to the closing of the gripper switches GS1 and GS2.

The QI and Q2 transistor stages are thus used no limit the current drain cn she pin spotter chassis only to the time m which the SET GATE signal is applied which corresponds to a 260C through a

350° machine table motion of the gripper switches which results in a SET GATE signal duration of approximately 1.5 seconds.

As a result of the actuation cf the controlled rectifiers SCR1 andSCRl, the plus volt filtered power supply is connected through

• to

- 37 t© th· ROM <PBOM> module 715. After approximately 10 i s.. iseconds Save elasped from th® receipt of the SET GATE signal, pin No- 13 of the Norgate module 712 is drive® to a Hi logic -condition. This Hi logic state presents itself on pins- 9 and 9 and XL and 12 of the Norgate module CS. This causes the seminal pins 13 and 10 of the module 78 to go t© a Lc state thereby gating any signals present on the input pms of the modules 76, 7’ and 78 which exist from, the optical coupler modules 73, 74 and 75. In the present example, s-gnals at pins 8 and. 11 of the module 76 fro® pins 25 and 14 if the modu:© 73. respectively, axe gated through cc pins 2G and 23, respectively, of the module 76. Since the pins 25 and 24 of the module 73 are -n a io state due to the action if the opto-isolators. a low set of signals -s present at pins 8, 9 and 11 12 of the nodule 76 since the pias 9 and 22 are driven by the pins 23 and 10 of the module 78 as previously indicated. The HSR function then yields a Hi state output at pins and 23 of the ccdule 76 which correspond t© addresses A. and A. terminal pms 5 and 6,

Λ, respectively .n the R2M PR2M 71S. The

ROM GRRSMr; 715 is a positive *ogic device and

and 28 perform both and arrow 3PLS.

This xs m Keeping with the c

Logic resulting xn the selective a out a of the ial^ path Lamps allowed before the

ώ.

cay be read at the .trough '4 terminal pins order

ROM, PRCM combinations available froa various manufacturers, the gating signals supplied to such

25.

c e a s a

foregoing cable.

22, therefore the modules c ® s ® <a β s

output pits © o to properly utilise the various © e <

a ts . 4, 5, or word which corresponds to the 1-2 ball paths

11, 12 and 9, respectively: .

words scored in the ROM PR2K,

When an a&dress presents itse*i in the input terminal pins 5, t, addresses. A$ and A, is 3. At this location m the MM (PRQM> memory is a four-bit binary code address inputs A, through Aa of the iWM PR2M V 7 , 25 , s* *

Ρ ι ’ :> t »

1:1

a A

proceed toward that end.

The decoder demultiplexer 016 will present a £e logic leyex at its number 5 cutput *.iich corresponds tc rhe number 6 output terminal pin thereon, thereby applying this Lxs Lcgm level to the nunber 8 and manner 9 terminal > »> *· ♦ s *©< e »·»· c wee ♦ ♦· ♦ ο c 9» X *· »

* !‘ ae * « e os o

«»♦ · e

e «4 » e> » * «Ο * * · ♦ ··« <

e ««»«« w o pin· of the Norgate module ”10 causing a logic inversion resulting .n a Hi Logic level at the output terminal pm 10 of the Norgate module

OXO, thereby biasing the gate terminal if the controlled rectifier SCB5A to turn m the controlled rectifier SCR5A and illuminate the ball path lamps B.PL5- through the cutnut BAS and termini pm 23 of the printed circuit card FC1. 3zmv stack to Figure 2B, it is noted that me tastes mttxconnector has a tanamal sir. £*Ξ xnmh corresponds to the cutput BAS and tormina- sm if the printed circuit card ?0L tn wn-ct me ta.. ,-:a-n Lamps BBLS .all four of them., xs rtmecned. One other side tf this ea*l path .amp 3PL5 -s tmnected through a c-daecn lead tc ,.ne plus -1 .-c*- t.ltered power supply and -s mereby erergmed ‘‘hrough me centre* lex5 rectifier SCRSA which -3 ground at -ts catncde.

2S 'the ROM and the demult-i-exer, me gat.ns a*ma*

RS·!

for the demultiplexer 016 is formed by a time delay of approximately 10 milliseconds. consisting of the MOR gate module 013, the resistor R16 and the capacitor C3. This tine delay begins its timing cycle after' the use delay formed by the preceedmg MOR gate module 012, resistor R15 and the capacitor C2 times out.

Wen this 10 ms. time, delay times out, then the G1 and G2 gate terminals C terminal pins

13 and 19, respectively), in the decoder/demal diplexer are driven to a to state since they have been inverted by 'the MOR gate in the MGR gate module 011 Cterminal pm 10 thereof;, which m turn has been ^Margined through its terminal

IS pins 8 and 9 from the terminal pin 23 ;f the preceding MOR gate nodule 013. All other output pms of the decoder demultiplexer are neld in a Hi logic state. This time <Wlay is provided tc compensate for any settling time required for the change m ROM »?R£-X'' address no ee outputed.

The number 5 sutput of the decoder demultiplexer 016 being in a Lc state is inverted in the MOR gate acdule 010 as previously described. Thus, the MOR gate modules 09, 013 and 011 with the exception of the last available MOR gate m Oil act as inverter driver* for the

- 42 output of the deccder/demultiplexer in presenting proper logic, levels associated ther-wxtte to the gates of the respective controlled rectifiers SCR1A through SCR11A representative of the ball path outputs BAI through 3*11, respectively as well as the ball path lamps SPbl through 3PL11, respectively.

With regard to the controlled rectifier

SCR5A, the resistor R5 associated therewith forms a gate to cathode- voltage developing resistor while the capacitors C2(3 -and C31 associated therewith fora «^-capacitor network to suppress voltage, transients. Similar networks are formed by the resistor/capacitor networks associated with the other controlled rectifiers SCR1A through SCR11A.

The controlled rectifier SCR5A remains in the OH state by means of the filtered plus 12 volt supply frees, the control chassis and no further action is required by the ROM circuxtsv after a specific SCR has been selected. The entire action described above occurs m milliseconds and accordingly, ...the use of) a 1.5 second SET GATE signal is used as the only main control signal for

the entire device.

As can be seen fro® the foregoing description of the invention and the description

- 5< λ.,* WAUI W sov pin numbers and the parenthetical terminal pin

* a* ♦ ♦ *< * e ; * « · #»·« * s λ we s • · · ♦ w a e e e.

« a * *E * ♦

- haw e

Oa»«T * » » 4» we * * «» * <· * e> * »

*O··* ate * •e * >

- 43 of operation thereof, the occurrence of the closure of gripper witches GS1 through 0810 is Moled as a Lo logic condition and transmitted through suitable isolation and. logic conversion S circuits to a positive logic ROM (PROHJ where the addressee are cumulatively coded by adding the weighted significance of the standing pin inputs lb. keeping with the weighted valua .address tables. These inputs result in the generation of stored code words representative of particular addresses which, by seen* of a decoder/demsxltiplexer, are codes corresponding to specific ball path arrows illuminated by the ball path lamps BPL1 through 3PL11 and illustrated on the face of the ball

IS path, and standing pin mask 12 as basically shown in Figure 1. Thus, there is a very simplistic direct, instantaneous and simple mput-to-output conversion of standing pin data, to optimum ball path direction correlated to that standing pm data for maximum effectiveness assuming a. ball can be .rolled true in accordance with the indicated ball path.

♦ «*.*«*« ♦ ♦ * #w * *r « *♦* ♦ *

**«* » *« « ♦ • #•4 **««» * * «♦ * * * * .; &

Φ #**«#->

* « ♦ ee • * * * *# < O ® « <>

«»«»

Parts List

<td></td><td colspan="2"> l BB*£</td><td> OMcdsWicn</td>

<td> U1A</td><td> aouce - Ttiapoe Pxcdnct Divxaiai</td><td> ♦43OGW01-471</td><td></td>

<td> ma</td><td> BXKas - Trimpoc 9ihA·» nitri^jrgi</td><td> ♦43001-101-471</td><td> Hbb^Moc MsockSc 470 CM t 21</td>

<td> uz</td><td> Oouams - Trjjqpoe</td><td> ♦4114R-O22-103</td><td> MMBMor MMcKfc 14 Μη D.X.P.</td>

<td> 03</td><td> UMKMXX</td><td> HQ74</td><td> Opts Xsolaimr 00-74 14 Μη D.I.P.</td>

<td> 04</td><td> XiSMSOflDC</td><td> HQ74</td><td> Cpte Xeolz^sx HO-74 U Pin O.XvF.</td>

<td> os-ms</td><td> WHS</td><td> >74003</td><td> PCS. 3CRGKEE</td>

<td></td><td> tsSdSe s</td><td> JM 74032 Nl 74002</td><td> 74002 14 Pin O.I.P.</td>

<td> 014</td><td> sxaoncs</td><td> K7402</td><td> PCS. NCPGME</td>

<td></td><td> JCTOUXA MnzoNtf. Φ -r »«M»·</td><td> JC 7402D M 740» SN 740»</td><td> H7402 14 Pin O.X.P.</td>

<td> ms</td><td> SXOOHCS</td><td> 8228</td><td> 4096 - 3XT aXFOAR MM (1024 X 4) (16 Pin)</td>

<td></td><td> sttattcscs wwtrwrr</td><td> 82S136/137</td><td> 4096-BXT miwab sane (1024 x 4) <10 Pis)</td>

<td> me</td><td> JfffXCWL</td><td> JM 740154</td><td> Dtooder/HulciplMer</td>

<td></td><td> OUJBES</td><td> JM 74C154</td><td> 740154</td>

The following data .sheets on the. commercially available integrated circuit chips utilised with the present invention as described hereinbefore with reference to the Figures are incorporated by reference into the. disclosure *

* * * « * ♦ ♦ ··♦» «>·» « ·β s · w ♦ *·» * a * e * Sea e as • * e #»*»

as**· *

of the application:

Bata Sheet MM 74C02 Quad 2-input MOMGATE by National Semiconductor

Bata Sheet IW-74 IO&to Isolators pgs. 21, 35) by LIXTBOMIX

Bata Sheet .110-74. (Opto Isolators pgs. 21, 35) by LINTKMIX

Data. Sheet Model 4306R-1G1 (SIP resistor networks pg. 10) by Bourns - Trimpot Division

Data Sheet Model 430·Μ-101 (SIP resistor networks pg. 10) by BournsTrimpot Division

Data Sheet MIS4C154/MI74C154 (pgs. 48-502 by Matronal Semiconductor

Data Sheet 409S-BIT Bipolar ROM (pgs. 23, 53) by SIGMETICS

Data. Sheet 54/74 Families of Ccapatible H& Circuits (pgs. 5-9) by Texas Instruments

Data Sheet 54/74 SSI Devices by National Semiconductor

Any suitable software may be. used.

Applicant's worksheet for .BOM content compulation is incorporated by reference into the disclosure of this application.

US with the | Patent and. Trid—ark Office in connection K US. pfcie^ **b»<

with the disclosure o^tbis ippHBaiian for review of the public open request.

*♦ « ft » * «a * * < *«* <

**#» » a ft* » * ** # » * * * » » ♦ eewftftft ft ft ft* * ft * ft* ft «

It should he understood that the BOMLIWG

MU. MTS INDICATOR WXTH ROM BALL PATS SIX1CT0R

Mgr be. ftodified as wold occur to one of ordinary skill in -tbe art without departing fro· the spirit and scope of the preeent invention.

next to these respective leap* in Figure 28 operation of the present invention will be !

J

The dates bowling al pin «easin the bowlin’ «electing « path arrow

O β ft ft ft β ί ft a

ball an #ai generate re;

signa Is f re:

with said s?

with said os signals csrr said address

II !

Contents10

12 members in 8 offices

This recordMember, by publication datePriority claim

Priority claims1

Priority claims
Document	Office	Kind	Date
16442980	United States of America	A	1980-06-30

Members12

Family members, oldest first
Document	Office	Kind
FR2485769A1	France	A1	1981-12-31
SE8103995L	Sweden	L	1981-12-31
AU7164581A	Australia	A	1982-01-07
GB2078531A	United Kingdom	A	1982-01-13
DE3125798A1	Germany	A1	1982-04-15
JPS5775673A	Japan	A	1982-05-12
US4339128A	United States of America	A	1982-07-13
GB2078531B	United Kingdom	B	1985-02-13
AU552003B2This record	Australia	B2	1986-05-22
SE445088B	Sweden	B	1986-06-02
MX153011A	Mexico	A	1986-07-18
FR2485769B1	France	B1	1988-06-17