Compensated high-speed pll circuit

The invention relates to a compensation method and phase-locked loop (PLL) circuit, wherein different kinds of two-point modulations are used and the integral regulator of a loop filter is replaced by introducing predetermined settings at the loop filter or at a voltage controlled oscillator. Thereby, the dynamic settling time of the PLL circuit can be improved to gain time for other circuit components which can thus assure required precision for the modulation.