Hybrid interleaver for turbo codes

A turbo code encoder with a hybrid interleaver having two recursive systematic constituent code (RSC) encoders. The system encodes a finite sequence of informative bits without requiring a plurality of tail bits to flush the registers of each encoder to an all-zero state. The hybrid interleaver reduces the turbo code overhead by using only a single tail bit sequence. By using only a single m-bit tail, the hybrid interleaver improves bit error rate (BER).