Balanced cryptographic computational method and apparatus for leak minimization in smartcards and other cryptosystems
Abstract
Cryptographic devices that leak information about their secrets through externally monitorable characteristics (such as electromagnetic radiation and power consumption) may be vulnerable to attack, and previously-known methods that could address such leaking are inappropriate for smartcards and many other cryptographic applications. Methods and apparatuses are disclosed for performing computations in which the representation of data, the number of system state transitions at each computational step, and the Hamming weights of all operands are independent of computation inputs, intermediate values, or results. Exemplary embodiments implemented using conventional (leaky) hardware elements (such as electronic components, logic gates, etc.) as well as software executing on conventional (leaky) microprocessors are described. Smartcards and other tamper-resistant devices of the invention provide greatly improved resistance to cryptographic attacks involving external monitoring.
Term
Term ended
Expired 3 June 2019, 7.3 years ago.
- Priority
- Filed
- Granted
- Expired
- Today
17 members in 6 offices
Priority claims1
| Document | Office | Kind | Date |
|---|---|---|---|
| 8787998 | United States of America | P |
Members17
| Document | Office | Kind | |
|---|---|---|---|
| WO9967766A2 | World Intellectual Property Organization (WIPO) | A2 | |
| AU6238499A | Australia | A | |
| WO9967766A3 | World Intellectual Property Organization (WIPO) | A3 | |
| WO9967766A8 | World Intellectual Property Organization (WIPO) | A8 | |
| EP1088295A2 | European Patent Office (EPO) | A2 | |
| US6510518B1 | United States of America | B1 | |
| US2003140240A1 | United States of America | A1 | |
| US6654884B2 | United States of America | B2 | |
| EP1088295A4 | European Patent Office (EPO) | A4 | |
| EP1802024A2 | European Patent Office (EPO) | A2 | |
| EP1088295B1 | European Patent Office (EPO) | B1 | |
| AT370490T | Austria | T | |
| DE69936856D1 | Germany | D1 | |
| EP1802024A3 | European Patent Office (EPO) | A3 | |
| DE69936856T2 | Germany | T2 | |
| EP1802024B1 | European Patent Office (EPO) | B1 | |
| AT548819TThis record | Austria | T |
Numbers
- Application
- 7075144
Titles2
- German
- SYMMETRISCHES KRYPTOGRAPHISCHES RECHENVERFAHREN UND VORRICHTUNG ZUR VERLUSTMINIMIERUNG BEI CHIPKARTEN UND ANDEREN VERSCHLÜSSELUNGSSYSTEMEN
- English
- SYMMETRIC CRYPTOGRAPHIC ACTION PROCESS AND DEVICE FOR LOSS MINIMIZATION IN CHIP CARDS AND OTHER ENCRYPTION SYSTEMS
Classification
- CPC, 7
- H04L9/0618
- G06F21/602
- G06F2207/7219
- G06F21/755
- H04L63/1441
- H04L9/003
- H04L2209/122
- IPC, 1
- H04L9 06