Direct memory access controller

The system operates independently from the operation as a central processing unit (CPU), a sleep mode or to be operated a plurality of system components to operate in a low power mode and active mode, and the CPU to operate in a sleep mode or low power mode and active mode and a sleep mode and a low power mode and may include operational DMA controller to operate in the active mode, the DMA controller is to be further operated to transmit data also in the memory or the peripheral device from the memory or the peripheral device, the system is in sleep mode or low power mode system components required only to implement a DMA controller and the DMA transaction if necessary when one is also switched to the active mode.