Gnss signal processor

[Subject] A GNSS super parallel processor which consumes electric power less than a known processor is provided.<br />[Means for Solution] A signal processor for GPS or other GNSS radio localization systems, Synchronizing with numerals NCO, a sampling rate is managed with programmable oscillator 350 set up according to a Doppler shift of a satellite for acquisition, Alignment of all the samples in a buffer is fixed including buffer 37 before RAM correlation filled with a sample generated by sampling stage 35. Without needing a middle buffer including amplitude compression machine 36 for restricting size of a buffer memory, it is optimized so that data may be supplied to DFT unit 60 in a small burst which can be processed in real time and which follows. As a result of these features, quantity of a high-speed middle memory is restricted, it is simplified more, and a processor has lower power consumption.<br />[Chosen drawing] Drawing 2