Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory

Write check bits are generated in a predictive manner for partial-word write transactions in a memory system implementing error code correction. A read data word and associated read check bits are read from an address of the memory. If an error exists in a byte of the read data word, this byte is identified. At the same time, one or more bytes of the uncorrected read data word are merged with one or more bytes of a write data word, thereby creating a merged data word. Write check bits are generated in response to the merged data word. If the merged data word includes a byte of the read data word, which contains an error, the write check bits are modified to reflect this error. The merged data word and the modified (or unmodified) write check bits are then written to the address of the memory.