Semiconductor structures formed on substrates and methods of manufacturing the same

Summary f

Processes used to transfer semiconductor structures from an initial borrowed substrate to a base substrate include attaching the initial substrate to a doped f with a silicon dioxide layer

Silicon structure is bonded, which is weakened sufficiently for cleavage by a hydrogen implantation. After cleaving, a doped silicon layer remains, which buries the silicon dioxide layer between the doped silicon layer and the initial substrate. Semiconductor structures are formed in / on an epitaxial layer, the I an. the doped silicon layer is arranged, wherein a semiconductor 1

Intermediate structure is formed. A process support is temporarily used for the |

Bearings bonded to the semiconductor structures. The initial substrate J is formed through a mechanical thinning process followed by chemical etching using the buried silicon dioxide layer as ί

Etch stop, thinned and removed. The silicon dioxide layer is chemically removed from the doped silicon layer. A base substrate is formed on the doped silicon layer. The process holder is removed, leaving behind the semiconductor structures arranged on the base substrate.

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TRAINED ON SUBSTRATES HAS.RT.RITER STRUCTURES AND PROCEDURES FOR

MANUFACTURING THESE ·· ··

BACKGROUND OF THE INVENTION

The present invention relates generally to semiconductor devices and, more particularly, to various embodiments of semiconductor structures formed on various substrates, such as metal, and methods of making such devices.

In general, conventional semiconductor manufacture employs a number of processes to form semiconductor structures on substrates. The substrate is typically part of a wafer. A wafer is a small, thin, circular disc of a semiconducting material, such as silicon, on which semiconductor structures are formed. Standard device manufacturing processes, such as etching, deposition, and electroplating, are used to create semiconductor structures on the wafer. After the semiconductor structures have been formed, the wafer is tested and then diced to separate individual semiconductor structures, commonly called chips, which include a substrate layer. A substrate layer (substrate) is often referred to as the base layer or body of the chip on which other layers are deposited to form the semiconductor structures. Semiconductor structures formed on the substrate can be discrete components or integrated circuits. For example, the semiconductor structure can consist of a single discrete power transistor or can be formed from a number of transistors and other electronic elements, such as resistors, capacitors, etc., which are electrically coupled together to form an integrated circuit.

The substrate plays a crucial role with regard to the semiconductor structures it carries, whether it is a discrete component such as a power transistor or an integrated circuit. The substrate is often used to structurally support the semiconductor structure from damage due to mechanical bending. The substrate can also be used as part of the semiconductor structure, where vertical or lateral current flows are supported. In some components, the substrate is used as an insulator, the substrate being designed to separate the semiconductor structure from other semiconductor structures or from an electronic

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·· ·· see coupling with a conductive surface to isolate.

Depending on its properties and dimensions, a substrate can adversely affect the performance of semiconductor structures it supports. The substrate can introduce undesirable parasitic impedances and heat conduction paths, which can influence the power consumption, the power dissipation and the operating bandwidth of a semiconductor structure. For example, in a typical integrated circuit (CMOS circuit) designed as a complementary metal oxide semiconductor, the substrate can contribute to a latch-up. Placing the CMOS component on an insulating substrate, e.g. silicon-on-insulator (SOI), instead of on a conductive substrate can reduce leakage currents and help prevent latch-up. Circuit can restrict. For radio frequency (RF) devices, the substrate is often a critical design element in terms of transmission lines used to transmit high speed data. The thickness and type of substrate material are important to the transmission efficiency of such high speed signals. The substrate often plays an important role in dissipating heat from the semiconductor structure. For example, a metal substrate can be used to help remove heat from a component to an outside environment. Therefore, the thickness, material, and structural design of the substrate layer are critical components in terms of the performance and structural integrity of the semiconductor structure it supports.

In certain devices, the substrate is used as part of the power conduction path. For example, the substrate plays an important role in the solid-state switch, which is an important semiconductor structure used for discrete component and integrated circuit applications. Solid state switches include, for example, the metal oxide semiconductor field effect power transistor (power MOSFET), the insulated gate bipolar transistor (IGBT), and various types of thyristors. Some of the defining performance characteristics for the circuit breaker are its on-resistance (i.e., drain-source-on resistance, Rusen), its breakdown voltage, and its switching speed. Depending on the requirements of a particular application, a different focus is placed on each of these performance criteria. For example, in power applications greater than 300-400 volts, the IGBT has an inherently lower on-resistance compared to the power MOSFET, but its switching speed is lower due to its slow turn-off characteristics. Therefore the ·· ·· • · · «• · · · ··

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IGBT is the preferred switch for applications greater than 400 volts with low switching frequencies requiring a low on-resistance, while the power MOSFET is often chosen as a device for relatively higher frequency applications.

In general, the switching speed, the on-resistance, the breakdown voltage and the power dissipation of a typical MOSFET device are influenced by the layout, the dimensions and the materials. Design practice in the industry sought to keep the on-resistance of the MOSFET as low as possible in order to reduce static dissipation and increase current densities. For example, in vertical power MOSFET components, the on-resistance consists of various resistors, such as a channel resistor, an epitaxial film resistor, and a substrate resistor. The resistance of such a vertical power MOSFET device (as well as other MOSFET devices) is directly affected by the type and dimensions of the materials used to form the drain-source conduction path. Therefore, the substrate is a critical power element in a vertical power MOSFET.

In addition to the substrate layer, the semiconductor layers that form semiconductor structures such as MOSFETs and CMOS circuits inherently affect the operational performance of the semiconductor structures. The substrate layer and the semiconductor layers introduce parasitic effects in the semiconductor structures, which are inherent in the substrate and the semiconductor layers. For example, parasitic capacitances and inductances are directly caused by the materials that are used for the semiconductor layers and the substrate (e.g. insulator, semiconductor, doping concentration, etc.) and the dimensions (e.g. height, width, length, etc.) that are used to form and support the semiconductor structures. Such parasitic effects generally lead to a deterioration in the electrical performance and the operation of the semiconductor structure.

In general, smaller dimensions of the semiconductor structures tend to reduce parameters such as resistance, power dissipation and parasitic impedance. With respect to the semiconductor layers, for example, the thinner the semiconductor layers, the better the semiconductor structure operating frequency. Also, substrate materials with a larger specific heat capacity and more heat-capacitive substrate materials tend to increase the heat dissipation capacity of the semiconductor structures, whereas thinner substrates tend to reduce the operating frequency.

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• 4 • · • · • 4 • · · 4

4th 4 4 • 444 4 for those devices that rely on the substrate as part of the conduction path. However, as semiconductor structures are reduced in size, providing thinner semiconductor layers and substrates presents a process challenge for semiconductor manufacturers. In conventional semiconductor structure fabrication processes, after semiconductor structures, other semiconductor layers, and metal layers have been applied to the substrate, the substrate is often thinned using a process such as chemical mechanical polishing (CMP). Chemical etching processes have been developed to further etch the substrate to a thinner profile, however chemical etching processes are difficult to control and often result in damaged semiconductor structures that are inadvertently etched during the process. In addition, conventional substrate thinning processes have their own limitations, since the semiconductor structures require structural support. Therefore, conventional processes for thinning the substrate generally produce some defective semiconductor structures due to etch imperfections and mechanical bending of the substrate.

There is therefore a need for structures and methods for forming semiconductor structures with optimized semiconductor layers and substrates to improve operational performance while minimizing process-related defects due to structural stresses.

BRIEF SUMMARY OF THE INVENTION

Embodiments of the present invention relate to a formation of semiconductor structures and a process for transferring semiconductor structures formed in and / or on silicon layers deposited on an initial substrate to a base substrate such as metal, silicon, glass and the like . In one embodiment, the present invention discloses methods and structures used to transfer discrete components and integrated circuits from the initial substrate layer to a base substrate. The processes and structures described herein provide semiconductor layers and substrates with improved electrical and structural performance, which provides improved electrical performance of the semiconductor structures that are integral with and supported by the semiconductor layers and substrates.

In another embodiment, the invention provides a method for

Transfer of semiconductor structures from an initial substrate to

A basic substrate ready. The method includes providing an initial substrate with an etch stop layer, providing a doped silicon layer on the etch stop layer, and forming semiconductor structures on the doped silicon layer. The semiconductor structures, the doped silicon layer, the etch stop layer and the initial substrate form a semiconductor process. The method further includes supporting the semiconductor process with a removable support structure, removing the initial substrate using a chemical etch process that removes the initial substrate down to the etch stop layer, removing the etch stop layer with a chemical etching process, and applying a substrate material to the doped Silicon layer is deposited to form the base substrate.

In another embodiment, the present invention provides a method of forming semiconductor structures on a metal substrate. The method includes an initial substrate is provided with an exposed silicon dioxide etch stop layer, a doped silicon material implanted with hydrogen is bonded to the silicon dioxide etch stop layer, a region of the doped silicon material is determined that is sufficiently weakened by the hydrogen to cleave the doped To allow silicon material along the area and cleaving the doped silicon material along the region, leaving a doped silicon layer bonded to the silicon dioxide layer. The method further includes that semiconductor structures are formed on the doped silicon layer, the semiconductor structures, the silicon dioxide layer and the initial substrate are supported with a carrier device, the initial substrate is removed, the silicon dioxide layer is removed and a sufficient amount of metal for the doped Silicon layer is provided to form a metal substrate.

In another embodiment, the invention provides a substrate structure. The substrate structure includes an etch stop layer disposed on an initial substrate. The etch stop layer is configured to provide a process barrier to a process of chemical mechanical polishing to remove the initial substrate. The substrate structure also comprises a semiconductor layer arranged on the etch stop layer.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 shows a cross-sectional view of an embodiment of a two-

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exemplary n-type trench MOSFETs according to embodiments of the invention; 2 shows a cross-sectional view of an embodiment of a silicon material with a region implanted with hydrogen ions according to embodiments of the invention; 3 shows a cross-sectional view of one embodiment of an initial substrate and the doped silicon material in accordance with embodiments of the invention; Fig. 4th FIG. 3 shows a cross-sectional view of one embodiment of the initial substrate bonded to the doped silicon material of FIG. 3, in accordance with embodiments of the invention; FIG. FIG. 5 shows a cross-sectional view of one embodiment of the initial substrate comprised of the doped silicon material of FIG. 3 is separated, leaving a layer of doped silicon on the initial substrate and forming a semiconductor process structure, according to embodiments of the invention; 6 shows a cross-sectional view of an embodiment of the semiconductor process structure of FIG. 5 with an epitaxial layer arranged on the doped silicon layer in accordance with embodiments of the invention; Fig. 7th FIG. 6 shows a cross-sectional view of one embodiment of the semiconductor process structure of FIG. 6, wherein semiconductor structures formed on the epitaxial layer form a semiconductor structure layer, in accordance with embodiments of the invention; FIG. 8 shows a cross-sectional view of one embodiment of a process fixture attached to the semiconductor structure layer to support the semiconductor process structure for processing, in accordance with embodiments of the invention; Fig. 9 12 shows a cross-sectional view of one embodiment of the semiconductor process structure after thinning the initial substrate by a substrate thinning process in accordance with embodiments of the invention; 10 shows a cross-sectional view of one embodiment of the semiconductor process structure after removal of the initial substrate by a substrate etch process in accordance with embodiments of the invention; Fig. 11 12 shows a cross-sectional view of an embodiment of the semiconductor process structure after the etch stop layer has been removed by an etching process according to embodiments of the invention; 12 shows a cross-sectional view of one embodiment of the semiconductor process structure after forming a metal substrate on the doped silicon layer in accordance with embodiments of the invention; Fig. 13 Figure 12 shows a cross-sectional view of one embodiment of the semiconductor process structure after removing the process fixture from the semiconductor process structure in accordance with embodiments of the invention;

14 shows a cross-sectional view of one embodiment of the semiconductor process structure prior to dicing in accordance with embodiments of the invention; and FIG. 15 shows a cross-sectional view of an embodiment

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··· • '• φ of the semiconductor process structure after the division into individual components according to embodiments of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to semiconductor structures and processes for transferring semiconductor structures formed in and / or on silicon layers formed on an initial substrate, such as an initial substrate for a power MOSFET, to a base substrate, such as metal, Glass, silicon or the like. The present invention also relates to transferring semiconductor structures formed in and / or on silicon layers formed on an initial substrate to an insulator for silicon-on-insulator components (SOI components). The process includes forming a layer of silicon dioxide (SiO₂) on the initial substrate. The process further includes providing a doped silicon layer on the SiO₂-Layer. A doped semiconductor material is implanted with hydrogen ions (eg H +) to form a cleavable region. The doped silicon material is attached to the SiO₂-Layer bonded. The hydrogen concentration in the cleavable region is sufficient to enable the doped silicon material to be cleaved. In one embodiment, the doped silicon material is annealed at a temperature sufficient to cleave the cleavable region. After cleaving, a layer of doped silicon material remains on the SiO₂-Layer that makes up the SiO₂Layer buried between the substrate and the doped silicon layer. An epitaxial layer is formed on the doped silicon layer. Semiconductor structures are formed in and / or on the epitaxial layer using conventional semiconductor structure formation processes to form a semiconductor structure layer (ie, a layer containing electronic components such as discrete transistors, integrated circuits, and the like). The substrate, the doped silicon layer, the SiO₂Layer, the epitaxial layer and the semiconductor structure layer form a semiconductor intermediate structure body. The method further includes attaching a support structure to the semiconductor structures in order to support the intermediate semiconductor process structure for further processing. Once the intermediate semiconductor process structure is supported, the initial substrate is made using a mechanical

Grinding process, followed by a chemical etching process using the buried SiO₂Layer as an etch stop layer, removed. the

SiO₂-Layer is then removed using a chemical etching process. The doped silicon layer, the epitaxial layer and the semiconductor structures form a second intermediate semiconductor process structure. Then, a base substrate layer, such as a metal, is formed on the doped silicon layer having a thickness sufficient to form the base substrate. The base substrate, the doped silicon layer, the epitaxial layer and the semiconductor structures form a final semiconductor process structure. In another process step, the final semiconductor process structure can be divided up and packed into one or more semiconductor structures, for example chips. In one embodiment, a metal such as copper is used as the substrate formed on the doped silicon layer.

For a better understanding of the exemplary process flow described above, the invention will be described in more detail in the context of a vertical power MOSFET of the type shown in FIG. 1. 1 shows a cross-sectional view of an embodiment of an exemplary n-type trench MOSFET 100. It should be understood, however, that the principal techniques of the present invention apply to both discrete components and integrated circuits using any processing technology. As with all other figures described herein, it is to be understood that the relative dimensions and sizes of various elements and components shown in the figures are not intended to exactly reflect actual dimensions and are intended for purposes of illustration only. The MOSFET 100 includes a gate electrode G formed in trenches 102. The trenches 102 extend from the surface of a p-well body region 104 and terminate in a conductive drift or epitaxial region 106. In one embodiment, the trenches 102 are lined with thin layers of dielectric 108 and are substantially covered with conductive material 110, such as doped polysilicon. N-conductive source regions 112 are formed in the p-well body region 104 adjacent to the trenches 102. The MOSFET 100 includes a p + body region 117 which is formed in the p-well body region 104. The MOSFET 100 comprises a metal source layer 116. A drain connection D for the MOSFET 100 is coupled to a metal substrate 118 arranged on a doped silicon layer 114. The epitaxial layer 106 and the body region 104 form a semiconductor structure layer 107 arranged on the doped silicon layer 114. The structure of FIG. 1 is repeated many times to form an arrangement of transistors. A number of different power devices with various improvements are described in more detail in commonly assigned U.S. Patent Application No. 11 / 026,276 with the title Power Semiconductor Devices and Methods of Manufacture, the disclosure content of which: · · · ..

Is incorporated herein by reference in its entirety.

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Although conventional vertical trench MOSFETs have good on-resistance, they generally have a relatively high input capacitance. The input capacitance for vertical trench MOSFETs, including MOSFET 100, has two components: the gate-source capacitance Cgs and the gate-drain capacitance Cgd. The gate-source capacitance Cgs results from the intersection between the conductive gate material 110 and the source regions 112 near the top of the trench 102. The capacitance formed between the gate and the inverted channel in the body also contributes to Cgs since in typical power switching applications the body and source electrodes of the transistor are short-circuited. The gate-drain capacitance Cgd results from the intersection between the conductive gate material 110 at the bottom of each trench 102 and the epitaxial layer 106, which is connected to the metal substrate 118 via the doped silicon layer 114. The gate-drain capacitance Cgd, or Miller capacitance, limits the transition time VDS of the transistor. Therefore, higher Cgs and Cgd lead to significant switching losses. These switching losses are becoming increasingly important as power management applications move towards higher switching frequencies.

One way to reduce the gate-source capacitance Cgs is to reduce the channel length of the transistor. A shorter channel length directly reduces the gate-channel component of Cgs. A shorter channel length is also directly proportional to the on-resistance and enables the same current capacitance of the device to be obtained with fewer gate trenches. This reduces both Cgs and Cgd by reducing the amount of gate-source and gate-drain intersection. However, a shorter channel length also makes the device prone to breakdown if the depletion layer formed as a result of the reverse biased body-drain junction extends deep into the body region and approaches the source regions. Decreasing the doping concentration of the epitaxial layer 106 so that it maintains more of the depletion layer has the undesirable effect of increasing the transistor's density.

In one embodiment, the on-resistance of the device can be reduced by reducing the thickness of the semiconductor structure layer 107. For example, reducing the thickness of the semiconductor structure layer 107 reduces the channel length. In one embodiment, a lower Cgd is also provided by providing a relatively thin doped silicon layer 114 on the metal substrate 118. The metal sub-

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strat 118 also provides structural support for the transistor structure. With the processes described herein, the semiconductor structure layer 107 and the doped silicon layer 114 can have a size that is significantly thinner than that of conventional transistor configurations. For example, the drift region can be approximately 7.5 micrometers (gm) of the total thickness of approximately 10 μτα of the semiconductor structure layer 107, which comprises the component region 104. In addition, since there is no thick initial substrate to overcome, the epitaxial layer 106 can be doped with a predetermined doping profile and formed with a reduced thickness to maintain acceptable dielectric strength while reducing Rnson.

FIG. 2 shows a cross-sectional view of one embodiment of a doped silicon material 202 having a hydrogen ion (H +) doped region 204, and FIG. 3 shows a cross-sectional view of one embodiment of an initial substrate (e.g., a carrier mount) 308 and the doped silicon material 202 in accordance with embodiments the invention. With reference to Fig. 2 For example, the doped silicon material 202 may be doped by almost any type of dopant, such as boron, arsenic, and the like, that are used to form semiconductor structures. In this example, a dopant is used to form an n + -type material. To create the layer 114 of doped silicon, the doped silicon material 202 is doped with hydrogen ions to form the hydrogen-rich region 204. An exemplary process for doping hydrogen ions into a silicon substrate is disclosed in U.S. Patent No. 5,374,564 to Bruel, the disclosure of which is incorporated herein by reference in its entirety.

In one embodiment, the concentration of hydrogen ions on the surface of the doped silicon 202 is provided at a sufficient depth and energy potential to form a cleavable region 208 with an exemplary thickness of between about 1-2 μτα. For example, the doped silicon material 202 with hydrogen ions with an energy level of 170 keV to a dose level of 5E16 / cm² Hydrogen ion doped to form the cleavable region 208 with a thickness of about 1.7 µm. Because of the hydrogen embrittlement, the lattice of the cleavable region 208 is weaker than the lattice of the silicon which is not doped with hydrogen.

The initial substrate 308 comprises a silicon dioxide (SiO₂Layer) 306. The SiO₂Layer 306 is used as an etch stop layer

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and can be of almost any thickness that can be of benefit. For example, the SiO₂-Layer 306 are between 2500 and 4000 angstroms. The SiO₂Layer 306 can be formed on the initial substrate 308 using almost any SiO₂-Layer formation process to be grown or deposited on. For example, the SiO₂Layer 306 can be grown using a thermal oxidation process. In one embodiment, the SiO₂Layer 306 can be formed on the initial substrate 308 and / or the SiO₂Layer 306 can be formed on the doped silicon material 202 on the surface of the region 204. The SiO₂Layer 306 is further described below.

FIG. 4 shows a cross-sectional view of one embodiment of the initial substrate 308 bonded to the doped silicon material 202 of FIG. 3. FIG. 5 shows a cross-sectional view of one embodiment of the initial substrate 308 formed from the doped silicon material 202 of FIG. 3 using a cleavage process separated (i.e. split). The cleavage process leaves a layer 114B of doped silicon on the initial substrate 308 and a remaining layer portion 114A of the hydrogen doped silicon on the doped silicon material 202. The SiO₂Layer 306 may be bonded to doped silicon material 202 using several bonding techniques. For example, the SiO₂Layer 306 and the doped silicon material after a wet chemical treatment and a treatment with deionized water (DI water treatment) to form the SiO₂Layer 306 and the doped silicon material with a hydrophilic surface are bonded, for example at room temperature using conventional bonding techniques. After the bonding process, the doped silicon material 202 is cleaved from the initial substrate 308 using any number of cleavage processes. In one embodiment, the cleavage process includes annealing the doped silicon material 202 and the initial substrate 308 at a temperature between 200 and 300 degrees Celsius for about 5 to 10 hours. The cleavage process includes annealing the doped silicon material 202 and the initial substrate 308 at a temperature of about 450 degrees Celsius for about 15 minutes. The annealing process is used to break the lattice structure of the cleavable area 208.

FIG. 6 shows a cross-sectional view of one embodiment of the semiconductor process structure of FIG. 5 with an epitaxial layer 106 disposed on doped silicon layer 114B, and FIG. 7 shows one

Cross-sectional view of one embodiment of the semiconductor structure of FIG.

6, wherein the semiconductor structure layer 107 according to embodiments of FIG

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····

Invention semiconductor structures 702 has. Optionally, the cleaved doped silicon layer 114B can be pretreated in a CVD chamber in order to prepare the doped silicon layer 114B for the formation of the epitaxial layer 106. CVD treatment can be used to create a more uniform surface. The epitaxial layer 106 can be formed on the doped silicon layer 114B using a number of techniques. For example, the epitaxial layer 106 can be grown on the doped silicon layer 114B. Referring to FIG. 6, the carrier mounts 308 form the SiO₂Layer 306, doped silicon layer 114B, and epitaxial layer 106, in one embodiment, an intermediate semiconductor processing structure 606. The formation of the semiconductor structure layer 107 can be accomplished by any conventional semiconductor structure formation technique. For example, the semiconductor structures 702 can be formed on and / or in the epitaxial layer 106 using conventional semiconductor structure production steps, such as, for example, layer formation, structuring and doping. The semiconductor structures 702 can also be formed on the doped silicon layer 114B and / or integrally thereon. In an optional operational configuration, the metal layer 116 is formed on the semiconductor structures 702 for MOSFETs, for example. The metal layer 116 can be deposited using almost any process, some of which are described herein. In another embodiment, the initial substrate 308 is formed by the SiO₂Layer 306, the doped silicon layer 114B and the semiconductor structure layer 107, after the formation of the device layer 107, another semiconductor processing intermediate structure 706.

Referring now to FIG. 8, there is shown a cross-sectional view of one embodiment of a process fixture 802 attached to the semiconductor structure layer 107 to support the semiconductor process structure 706 for processing. In one embodiment, the process fixture 802 is temporarily attached to the semiconductor structure layer 107 to support the intermediate semiconductor process structure 706. For example, the process holder 802 is attached to the semiconductor structures 702 in one process step using a UV-releasable double-sided adhesive tape 804. The tape 804 provides an adhesive bond of sufficient strength to hold the intermediate semiconductor process structure 706 in place for processing. In another embodiment, the initial substrate 308 forms the SiO₂Layer 306, doped silicon layer 114B, semiconductor structure layer 107, tape 804, and process fixture 802, another intermediate semiconductor processing structure 806.

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9 shows a cross-sectional view of one embodiment of the semiconductor process structure 706 after thinning the initial substrate 308 by a substrate thinning process. Optionally, in one embodiment, the initial substrate 308 is thinned using a mechanical thinning process, such as mechanical polishing / grinding, to form a thinner substrate 308A. The initial substrate 308 can, for example thinned to about 8 mils for quick chemical removal. In another embodiment, the substrate 308A constitutes the SiO₂Layer 306, doped silicon layer 114B, and semiconductor structure layer 107 are another intermediate semiconductor processing structure 906.

10 shows a cross-sectional view of one embodiment of the semiconductor processing structure after removal of the initial substrate 308A by a substrate etch process. In one process, the initial substrate 308A is formed by chemically etching the substrate 308A with a chemical etching process using the buried SiO₂Layer 306 removed as an etch stop layer. Since the SiO₂Layer 306 is configured to stop the chemical etch process, the semiconductor structure layer 107 is unaffected by the chemical used to etch the initial substrate 308A. The chemical etching can be performed by any process for removing the initial substrate 308A. For example, the etching process can be performed with chemicals such as acids, hydroxides, and the like that remove the initial substrate 308A but not the buried SiO₂Etch layer 306. In one process, the chemical etch process to remove the initial substrate 308A can be represented by the following chemical formula:

Si + OH- + 2H₂O - »SiO₂ (OH)²'+ H₂ (Equation 1)

det. For example, the SiO₂-Layer 306 with a 49 wt .-% HF where SiO₂(OH)²'is a soluble complex. In another embodiment, the form SiO₂Layer 306, doped silicon layer 114B, and semiconductor structure layer 107, after removing the thinned initial substrate 308A, another intermediate semiconductor processing structure 1006.

11 shows a cross-sectional view of one embodiment of the semiconductor process structure 1006 after removing the SiO₂Layer 306 by an etching process. The buried SiO₂Layer 306 can be chemically etched using a solution of dilute HF. In this configuration, the doped silicon layer 114B is used as the etch stop

·*·..·· ............

• ·· ·· ;; ?; ·· · : :: .: ······..:: :

.........

Solution can be etched at room temperature. This exemplary solution can be the SiO₂Etch layer 306 at about 2.5 μm / min. The etching process to remove layer 306 can be represented by the following chemical equation:

SiO₂ + 6HF -> H₂SiF₆(aq) + 2H₂O (equation 2)

In another embodiment, the doped silicon layer 114B, the semiconductor structure layer 107, the adhesive tape 804, and the process fixture 802 form after the SiO is etched away₂Layer 306 from doped silicon layer 114B to another intermediate semiconductor processing structure 1106.

12 shows a cross-sectional view of one embodiment of the semiconductor process structure 1106 after the metal substrate 118 is formed on the doped silicon layer 114. For the sake of clarity, the formation of a metal substrate 118 will be described, but it should be understood that the formed base substrate may include nearly any type of material such as metal, glass, semiconductor and the like, which can be used advantageously. In one embodiment, the metal substrate 118 can be formed using nearly any process such as electroplating and / or using deposition processes such as plasma vapor deposition (PVD), chemical vapor deposition (CVD), and the like. For example, the doped silicon layer 114 can be galvanically (electrically) coated with the metal substrate 118. The metal substrate 118 can comprise virtually any metal or conductor that can be used to advantage, such as copper, aluminum, or alloys such as solder or the like. In one embodiment, after metal substrate 118 is formed, metal substrate 118, doped silicon layer 114B, semiconductor structure layer 107, adhesive tape 804, and process fixture 802 form another intermediate semiconductor processing structure 1206.

13 shows a cross-sectional view of one embodiment of the semiconductor process structure 1206 after the process fixture 802 has been removed from the semiconductor process structure 1206. The process fixture 802 can be removed using any number of techniques. For example, the process fixture 802 may be removed using an ultraviolet light process in which the adhesive tape 804 is configured to peel off when exposed to a sufficient amount of UV light for a predetermined duration. In one embodiment, the metal substrate 118 forms the doped silicon layer

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114B and semiconductor structure layer 107, after removing process fixture 802, another intermediate semiconductor processing structure 1306.

14 shows a cross-sectional view of an embodiment of the semiconductor process structure 1406 before dicing, and FIG. 15 shows a cross-sectional view of an embodiment of the semiconductor process structure 1406 after dicing into individual components (chips), such as the MOSFET 100, according to embodiments of the invention.

While the above provides a detailed description of various embodiments of the invention, many alternatives, modifications, and equivalents are possible. For example, many of the integrated formation techniques described herein in the context of a MOSFET, particularly a trench-gate MOSFET, can be used for other types of process technologies to fabricate semiconductor structures, such as integrated circuits formed with bipolar transistors or integrated circuits formed as CMOS, etc. Those skilled in the art will recognize that the same techniques can be applied to other types of devices, including nearly any semiconductor structure associated with a substrate, either as a process carrier or as part of the semiconductor structure body. For example, the processes described herein can be used to transfer a CMOS integrated circuit from an initial substrate to an insulator. With respect to RF devices, the processes and structures described can be used to transfer an RF device and / or circuit onto a substrate configured with a thickness and suitable dielectric to accommodate an RF circuit, such as for example an alumina ceramic substrate. Furthermore, it is to be understood that all numerical examples and material types provided herein to describe various dimensions, energy levels, doping concentrations, different semiconducting or insulating layers are for illustrative purposes only. For these and other reasons, therefore, the above description should not be used to limit the scope of the invention, which is defined by the appended claims.