Structure and method of making strained semiconductor cmos transistors having lattice-mismatched source and drain regions

The invention claims a integrated - circuit p- field effect transistor (PFET (10) and n-layer field effect transistor (NFET (12). Via is arranged PFET (10), which is not NFET (12) source and drain electrode area (111) and network mispairing semiconductor layer is of a silicon germanium, applying first strain to PFET (10), which is not NFET (12) and area (20). The invention claims a PFET (10) and NFET (12) manufacturing method. Etching groove of the areas, wherein formation PFET source and drain electrode area (111), so the silicon germanium layer (121) epitaxial growing of transistor grid mispairing, and used for applying strain with wherein the PFET channel region. With a silicon (14) growing the silicon germanium layer (121), and is formed on the silicide of the silicon (68), wherein provides low resistance source and drain electrode area (111).