Compression of data traces for an integrated circuit with multiple memories

An integrated circuit (100) comprising: a plurality of memories (126a, 126b); and trace module (140) operative to form packets of trace data, characterized in that each memory of the plurality of memories (126a, 126b) is accessible independently and the average tracking form packets of trace data for memory accesses of the plurality of memories, each packet including trace data for an address and data memory access to a specific memory and a memory identifier for the particular memory.