AT500554T

Memory system with burst length shorter than prefetch length

Abstract

Some embodiments, the invention comprises a system; the system is a storage control unit and bus and first and second memory device. The storage control unit request for reading and writing operation and a pulse on the operation. First and second memory device is the bus and storage control unit the coupling; the first and second memory device is respectively perpendicular to the pulse string length and prefetching length, reading device and request of the pulse string and performing and writing the operation. The descriptions and claim embodiments.

Term

Term ended

Expired 11 March 2023, 3.5 years ago.

  1. Priority
  2. Filed
  3. Granted
  4. Expired
  5. Today

18 members in 10 offices

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Priority claims
DocumentOfficeKindDate
10427002United States of AmericaA
0307513United States of AmericaW

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DocumentOfficeKind
US2003182513A1United States of AmericaA1
WO03083662A2World Intellectual Property Organization (WIPO)A2
AU2003213840A1AustraliaA1
AU2003213840A8AustraliaA8
WO03083662A3World Intellectual Property Organization (WIPO)A3
TW200401189ATaiwan Province of ChinaA
US6795899B2United States of AmericaB2
KR20040106303ARepublic of KoreaA
EP1488323A2European Patent Office (EPO)A2
HK1068181AHong Kong, ChinaA
CN1656463AChinaA
TWI246648BTaiwan Province of ChinaB
KR100633828B1Republic of KoreaB1
CN100386753CChinaC
EP1488323B1European Patent Office (EPO)B1
AT500554TThis recordAustriaT
ATE500554T1AustriaT1
DE60336212D1GermanyD1