Floating gate memory cells with increased coupling ratio

A a cylindrical flotation grid non-volatile semiconductor device control grid (18) and flotation grid (14) between the coupling rate method. The floats of the laminated grid of this invention the gate transistor, a conductive gap layer (24) is in overlapping two sides. Optimized with the aid of conductive layer (34) conductive gap layer (24) connected current control grid (18), further (22) and floating gate (14) which wherein the aid of the insulating layer. The conductive gap layer (24) and capacitor and grid (14) side (C1, C2) is a control grid (18) and flotation grid (14) between the normal capacitor.