Interconnections in simd processor architectures

Single command two or more data (SIMD) processor (1), It is divided into a memory part (14. . . 14) so that the process element array (10) containing two or more process elements (PE. . . PE) and operation are possible, and each memory part is equipped with the memory array (14) currently assigned to the specific process element. The 1st process element (PE) can operate so that a part of memory array which accessed a part of memory array (14) assigned to this 1st process element, and was assigned to the 2nd process element may be accessed. Such access is performed using the index value which shows the process element assigned to the memory location which should be accessed.