Enhancing strained device performance by use of multi narrow section layout

A with high tensile stress semiconductor device. The semiconductor device including at the source region and leakage area substrate. The source region and leakage each region comprises multiple lead supply parts and drain electrode part are. And the output region and between the drain electrode part of the shallow trench to the frame (STI) area between the source area between two parts supply. The gate stacked staggered fins on the top of on the substrate. The tension to and vibrates layer on a substrate. The tension causing layer to cover the STI region and source region, arranged on the area, and grid without interrupting. The tension causing layer is connected with the substrate to make the tensile stress-reducing insulating material.