Clock signal generation techniques for memories that do not generate a strobe

The present invention describes a clock circuit for a memory controller. The described circuit uses a processor clock signal to generate a feedback clock signal for use for generating an input clock signal for use during write operations to the memory or read operation from the memory. The circuit is particularly applicable to a mobile wireless device including a memory that does not generate a strobe. A clock circuit that generates an input clock signal for input to a memory, a resistor element in series with the driver, and a receiver in series with a resistor for generating a feedback clock signal for output from the memory-capacitor (RC) may comprise a filter, and The input to the RC filter is tap (tap) between the driver and the resistor element.