Out of order dram sequencer

As a memory controlling data memory and acquisition and access memory and. When the upper execute for operating handle for detecting the pressing receiving to any occur conflict or a latent detention the temporarily of the adjacent requests, and the access memory and a receiving sequence to avoid or minimum conflicts or retards, and optimizing to the memory data bus data stream or source automatic and a data bus the data streams. Request according to the upper execute storage for storing rearranges, original for receiving sequence of tracking and. After performing, according to turn of original for reading and by performing the access memory and data transmission of reading a storage device to each support.