Method and apparatus for instruction set architecture having dyadic digital signal processing instructions

For designed to adapt to the digital signal processing applications for application program signal processor (ASSP) device of instructions structure. The device of instructions structure according to ASSP is matched to the DSP algorithm structure. The ISA indication signal usually 20, further expandable is 40, the two serial or concurrency executions instructions. ISA of instructions DSP for use in all two operations one of the two DSP instructions. The DSP indication or the operation of The preferred embodiment/maximized indication (MIN/MAX) is further mounted to image end of the indication) while an indication (MULT (504) and instruction head (sampling pipe (510) and minimum comprises a and non-operational handle (NOP), and instruction with a related operation code (a opcode) are. The invention is the sleeve of instructions structure and performing DSP instruction of for application signal processor the hardware system structure of efficient.