Data strobe synchronization circuit and method for double data rate, multi-bit writes

A selection data synchronizing circuit, a receiving global data gate pulse and each signal the first and second logic circuit. The control circuit flow the signal of the first to the first logic circuit, and first logic circuit response generating first data gate pulse of each global data gate pulse. The control circuit used for receiving the control signal. The writing control signal is integrated, the control circuit end flow the first logic circuit is signal, and flow of the signal switch to the second logic circuit. The second logic circuit is responded of the global data gate pulse generating second data gate pulse. First and second data gate pulse is used for locking the balance according to the signal of each trigger. Data gate pulse, wherein the data gate pulse's front and back of the storing the data in the trigger to.