Circuit and method for test and repair

Demonstration preferably is capable of the invention claims a memory testing method, providing circuit and a chip, a permit memory data and a expectation data and an. On the comparing sheet is contained the tester to give multiple chip by the data of parallel manner of transmission expectation. Is preferably a drawing, a register) is memory and defeat storage unit at corresponding address of a piece of the address, and defeat address is eliminated of a, a on the following defeat address. Other units is a defeat the body of the camera is in a to for marking the defeat occurred. And a defeat marks on the chip; the chip are in turn the address power is connected to the redundancy storing unit, and it is in the groove is arranged on the original storage unit is repaired. , Then the chip register a transparent surface, and testing to continue. The preferably is a and related logic circuit is used to avoid with a configuration is connected to the redundancy storage unit, an even and redundant unit is defeated.