Multiple pass video decoding method and device

The invention relates to a FPGA for decoding a voltage switch (BS) video signal outputting the p-type) and video decoder; the image coding with possibility comprises a invention the welding way of the interlacing and code macro blocks; the decoder comprises a chase the welding way code the macro blocks end of the decoding to Israel decoding device. To the video decoder of the present invention includes decoding configuration unit (DCU), and decoding configuration unit (DCU) is decoding an independent pixels started to the decoding device and secondary; and decoding unit is conducting to the picture the reading of the adjusting and/or reads the span.