Digital signal processing device

The invention relates to a digital signal processing device, in particular a digital computing device, according to the introductory part of claim 1.

In digital signal processing, digital signals are created using a wide variety of applications

Algorithms handled digitally, the digital signals being derived, for example, from originally analog signals by sampling. The signal processing can take place in the form of calculations in accordance with telecommunications algorithms in order to implement a bandpass filter or the like, for example. For such digital signal processing, the digital signal values ​​are stored in storage means in binary form, the values ​​usually being stored in a 2's complement representation as a whole number or as a fixed point number (FixedPoint Format). The more complex floating point representation (floating point format) can also be used for certain applications.

Digital signal processors (DSP) are mostly used to carry out the digital signal processing; in applications with very high throughput rates, such as in the course of image compression or in DSL (digital subscriber line) technology, specially tailored arithmetic units are also used, which have significantly higher computing speeds allow.

In the course of signal processing, a format conversion is often required, ie the representation of numbers must be changed with regard to the desired accuracy. It is typical here that the number of bits used, i.e. the bit width of the data words, is increased for greater accuracy, with a subsequent reduction again being necessary, and the position of the decimal point also has to be adapted for these format changes. These format conversions and decimal point adjustments naturally result in numerical errors which subsequently affect the accuracy of the result and thus the quality of the output signal; the reduction in the quality of the output signal can manifest itself, for example, in communications technology applications as signal noise, and, for example, in the case of the implementation of integrating filters, a total failure of these filters can be caused.

The exact format conversion and possibly also correct rounding in terms of signal technology are therefore very critical aspects in the course of such digital signal processing, and these manipulations also frequently occur in the usual practical applications in addition to the actual mathematical calculations such as multiplication or addition. Such a format conversion accordingly also has significant effects on the achievable processing speeds, ie to the clock frequency that can be achieved in each case, which subsequently also determines the technical and economic feasibility.

In the case of the signal processors currently used or known, format adjustments and rounding are carried out in the program with the aid of a series of individual commands, several clock cycles being required to carry out these commands; In some cases, the number of clock cycles required for this can then be greater than the number of clock cycles for the actual algorithmic signal processing or calculation, which of course is particularly disadvantageous.

It is now the object of the invention to enable particularly efficient processing of digital signals using number format conversions and possibly rounding operations, in particular a format conversion should be made possible within a single clock cycle, also in the same step as the actual mathematical operations.

To achieve this object, the invention provides a digital signal processing device with the features of claim 1. Particularly advantageous embodiments and further 3

AT 413 895 Β formations are defined in the subclaims.

According to the invention, in accordance with a particularly preferred aspect, a format conversion unit, preferably with a rounding unit, is thus inserted directly into the data path of the

Integrated arithmetic unit. Any format conversions and possibly rounding operations thus become a direct component of every signal processing command, so that, as a rule, no separate clock cycle is required. Another advantage is that the program creation is significantly simplified, since the problems in connection with the format conversion are automatically relieved of the programmer, io The number format conversion unit, if necessary with the integrated rounding unit, can be designed for a predetermined format, However, a format specification or setting is possible with particular advantage, For this purpose, a format register is preferably provided as the format specification unit. This format register is loaded once as required and then, based on its content, determines the format conversions and roundings and thus the exact functionality of these units. In particular, the format register can contain fields for specifying the data format, such as the total number of digits and the number of digits after the decimal point.

Furthermore, a saturation function (also

Called clipping function) in order to prevent a signal value from overflowing into the wrong sign when the maximum value is exceeded. By integrating such a saturation function, ie Incorporation of a saturation unit in the format conversion unit also means that no additional clock cycle is required and, as mentioned, errors that could possibly arise in connection with the format conversion and rounding function are prevented by this saturation function. A comparable saturation function is preferably also assigned to the rounding unit in order to recognize any overflow when rounding up and to deliver the correct result.

The invention is explained in more detail below with reference to preferred exemplary embodiments to which, however, it is not intended to be restricted. The drawings show in detail: FIG. 1 a block diagram of a signal processor known per se; 2 shows a schematic block diagram of an arithmetic unit of such a processor, specifically with a number format conversion unit according to the invention, to which a format specification unit is assigned;

3 shows such an arithmetic unit with a number format conversion unit in greater detail; 4 schematically shows a format of a format register as a format specification unit; 5 shows a detailed structure of the number format conversion unit including rounding unit and saturation unit; 6 shows, by way of example, a table with signed positive and negative 4-bit binary numbers, with a value range from -8 to +7; Fig. 7th a comparable table with 4 Bit40 binary numbers, each with two places before the decimal point and two places after the decimal point, with values ​​ranging from -2 to +1.75; FIG. 8 schematically, in association with the arrangement of FIG. 5, an example of a number format conversion with rounding and saturation, with an overflow; FIG. and FIG. 9 shows a comparable example of a number format conversion with rounding and saturation, but now with an underflow.

In Fig. 1, the known structure of a processor is shown schematically in a block diagram, a program memory 1 is provided to which a program controller 2 is connected in order to control an arithmetic logic unit 4 receiving the data to be processed from a data memory 3. The Harvard architecture, as shown, or also the Von Neumann architecture are known for the construction of such computing units 4, with a computing unit 4 with Harvard architecture being assumed here, even if this is of course not to be seen as restrictive. The arithmetic unit 4 contains, as will be explained in more detail below, for example with reference to FIG. 3, quite generally an arithmetic unit (ARU-arithmetic unit), and it defines a data path.

AT 413 895 Β

In such a digital signal processor, each program instruction is executed in three phases, the sequence being controlled with the aid of the program controller 2. In the first phase, the so-called fetch phase (fetch command call), a command word is read out from the program memory and supplied to the program controller 2, as illustrated in FIG. 1 with the reference number 1a. In the subsequent decode (decoding) phase, this command word is decoded and split into individual micro-operations with which the arithmetic unit 4 is controlled. This is indicated in FIG. 1 with the connection 2a between program control 2 and arithmetic logic unit 4. In the third phase, the Execute phase, the instruction is processed, and accordingly in this phase the micro-operations are passed on in the form of control signals via the connection 2a and the arithmetic logic unit 4 for actual execution, and additionally via the data connection 3a Data are loaded from the data memory 3 into the arithmetic unit 4; The arithmetic processing of these data and the intermediate storage in registers takes place in the arithmetic unit 4. After this processing, the data obtained are stored again in the data memory 3, for example via a connection 4a. In this respect, the data memory 3 forms, for example, input storage means and at the same time output storage means for arithmetic unit 4.

In Fig. 2 the structure of an arithmetic unit 4 is shown in somewhat more detail in a block diagram, with data Α, B to be linked to one another, for example input registers 5A,

5B are supplied (for example from the data memory 3 according to FIG. 1), after which they arrive in the arithmetic unit when the mentioned micro-operations are processed, a multiplier unit 6 being provided in series with an adder unit 7 here, for example. The result of these arithmetic operations is normally supplied to output storage means, illustrated here schematically by a result register 8, the result being indicated by Y. The individual components 5A, 5B to 8 define a data path 9, and a number format conversion unit 10 is also arranged directly in this data path 9, which at the same time contains a rounding unit, as will be explained in more detail below. This number format conversion unit 10, hereinafter referred to as conversion unit or adaptation unit for short, can convert the supplied data into a predetermined fixed one

Convert number format, but preferably, as shown in Fig. 2, a format specification unit 11 is provided, which is in particular in the form of a format register, and the output of which is connected to the conversion unit 10, as indicated in Fig. 2 with the connection 11a is. This format specification unit 11 can be filled with appropriate format information for the respective computing process or data processing process, as shown in FIG. 2 is indicated schematically at input 11b.

The arrangement of the conversion unit 10 directly in the data path 9 leading from the input registers 5A, 5B to the result register 8 in the manner shown means that the desired format conversions and possibly rounding operations in the same

Clock cycle can take place in which the arithmetic operations are carried out, with only a certain delay time to be accepted until the data appear at the output of the conversion unit 10. This means a time acceleration compared to the conventional technology, in which the format conversions and rounding operations are carried out via the program, so that they only take place in subsequent clock cycles, after the actual calculation processes, in separate conversion and rounding steps of the program. The present hardware implementation of these conversion and rounding tasks directly in the data path 9 also enables the programming to be simplified, since the respective program that is stored in the program memory 1 in FIG. 1 is to be saved, at most the desired target formats are to be provided for storage in the format specification unit 11 (provided that these formats do not result from the storage format of the data memory 3 by themselves, as will usually be the case), but no conversion whatsoever - and rounding operations must be programmed. If the above-mentioned delay time, which is to be taken into account with the present technology, should be rather long compared to the cycle time, for example should already last half a cycle, which is particularly important in the case of particularly fast arithmetic units 4

AT 413 895 Β short clock cycles, which could be the case under certain circumstances, provision can be made for a memory element (register) to be built into the conversion unit 10 for buffering so that the format conversion and rounding activity started in the given clock cycle in one second clock cycle can be completed without the given delay times affecting the result of the operations in the arithmetic unit, which is stored as result Y in register 8, could affect.

Further details for the construction of such a typical arithmetic unit 4 for DSP applications (DSP digital signal processor) emerge from FIG. 3. One important task in digital signal processing is, for example, the so-called multiply-accumulate function (MAC function; MAC multiply accumulate). With this function, two input numbers (operands) are multiplied and the result of the multiplication is then added to the contents of an accumulator. Such a MAC function is implemented, for example, with the arithmetic unit 4 according to FIG. 3, the result obtained also being subjected to a number range adaptation using the technology according to the invention (number format conversion and rounding). For such functions, the signed 2's complement representation is often used for the numbers, as shown below with reference to Fig. 6th 7 and 7 are to be explained in more detail, although the invention is of course not intended to be restricted to such representations. In the following description, however, for the sake of simplicity, such a signed 2's complement representation is used throughout.

According to FIG. 3, at the beginning the desired numbers A, B for the multiplication to be carried out are read out of the data memory 3 and loaded into the registers 5A, 5B, which is carried out by the program control (program control 2 in

Fig. 1) is accomplished. In a comparable manner, the data memory 3 also receives CONTROL commands from the program memory 2 via a control line 3b. The data or operands A, B are then fed in the next step to the arithmetic unit 6, a corresponding control signal (MUL / DIV multiplying / dividing) being applied to this by the program controller 2 at 6b. The multiplication result is fed via the connection 6a to the adder / subtracter 7, to which an add command (or subtract command; ADD / SUB) is fed in a corresponding manner from the program controller 2 via a control connection 7b. The current content of this accumulator 12 is fed to a second input of this adder / subtracter 7 from the output of an accumulator 12, as indicated in FIG. 3 at 12a. The result of this addition is again stored in the accumulator 12, see the output 7a of the adder 7, with a multiplexer 13 connected in between, which is controlled via a control input 13b (SELECT); is set by the program control 2 so that the multiplexer 13 brings the adder output 7a to the corresponding input of the accumulator 12 (see the connection 13a between multiplexer 13 and accumulator 12). The function of the accumulator 12 is initiated by the program control 2 with a control input 12b (OPERATION).

The multiply-accumulate instruction is usually repeated several times in a loop; as soon as the final result is available in accumulator 12, in the present example it is stored again in data memory 3, although the number format is adjusted beforehand, since the width of accumulator 12 is usually greater than the width of the data values ​​read from data memory 3 AWAY. In the present example, the multiplexer 13 is used to load the accumulator 12 with an initial value from the data memory 3 with its own instruction at the beginning of a loop. The value 00 is usually used as this initial value.

The content of the accumulator 12 (output 12a) is thus transferred to the conversion unit 10 before the restoring in the data memory 3 for the purpose of number format conversion and preferably also for the purpose of possible rounding, in which the adaptation of the Number format and rounding can be carried out. This ensures that the calculation result is stored in the specified memory6

AT 413 895 B format, although for the arithmetic operations carried out in the arithmetic unit 4, a larger word length (number width, ie a larger number of bits per number) can be used for a high accuracy of the calculation. The conversion unit 10 receives the corresponding control information from the format specification unit 11, preferably a register which contains control data relating to the respectively specified format (FXD_FORMAT): this control information is stored in advance, at the beginning of the program, during an initialization phase, in accordance with the storage format - Defaults about the data memory 3 loaded. For example, at the beginning of the program, a value is read out directly from the data memory 3, see output 3a in FIG. 3, and loaded into the specification unit 11 with the aid of a control signal 11b (LOAD). This word thus specifies the target format that the result Y obtained (cf. a corresponding area DST (DST destination target) is contained in register 11, apart from a memory area SRC (SRC source source) for corresponding format information on the format used during the calculation in arithmetic unit 4.

The corresponding format information in register 11 can each be 8 bits long (cf. bit positions 0-7, in total 0-15, in specification unit 11 according to FIG. 4).

The SRC format in the specification unit 11 thus relates to the format of the number given at the output of the accumulator 12, the source number, whereas the DST format specifies the target format of the data words for storage in the data memory 3. Each DST or SRC field in register 11 contains the position of the decimal point in the form of an unsigned binary number, with a value of 2 indicating, for example, that the number to be considered should have two decimal places, ie two places to the right of the decimal point, so that the decimal point is shifted two places from the rightmost place to the left.

According to FIG. 3, the conversion unit 10 delivers the result (Y; see also FIG. 2) at its actual output 10a, which is stored in output storage means according to FIG. 3 is stored immediately in the data memory 3; In addition, the format conversion and rounding can also result in an overflow or an underflow in the number adjustment (underflow UFL; overflow OFL), and corresponding status signals UFL and OFL are present at outputs 10b and Weder conversion unit 10; These two status signals UFL, OFL can preferably be fed to a status register 14 in order to be available for handling exceptional cases.

The mode of operation of the conversion unit 10 (format conversion, rounding) will now be explained in more detail with reference to FIG. 5, reference being made to FIGS. 6-9 in the following. FIG. 5 also contains exemplary dimensional information relating to the number of bits or the bit width of the individual data values ​​pending in the course of processing, these dimensional information corresponding to common practical examples. In the following, further explanations are to be given on the basis of concrete, but simplified numerical examples with lower bit numbers, with reference in particular to FIGS. 8 and 9 for easier understanding, with 2's complement number representations with regard to overflow also previously with reference to FIGS. 6 and 7 and underflow should be explained.

The conversion unit 10 according to the invention, also called ALIGN and ROUND units (with regard to format adaptation and rounding), receives, as already mentioned, the output value 12a of the accumulator 12, as can be seen in FIG. 5 as well as in FIG. 3. The format of this output value at the output 12a of the accumulator 12 is subsequently adapted by the conversion unit 10 in accordance with the specification by the register 11 (generally called the format specification unit) so that the finally received data word (output 10a) can be stored in the data memory 3 (or any other data memory, possibly with a different number format) is suitable. The conversion unit is in the data path (see data path 9 in Fig. 2) of the arithmetic unit 4 arranged directly,

that is, in the normal case, the operations carried out by the conversion unit 10

AT 413 895 Β preferably carried out in the same clock cycle as the arithmetic operations in the preceding arithmetic units 6, 7, with only a slight delay time from stage to stage. If, however, extremely short clock cycles are specified and the circuit modules with which the individual components, in particular the conversion unit 10, are implemented, cause a delay that is somewhat too great in comparison, then, as already mentioned, intermediate storage within the conversion unit 10, possibly also before and / or after the conversion unit 10, are provided, so as to perform a first part of the operations in a first clock cycle and a second part of the operations in a second clock cycle. In FIG. 5, however, the graphic representation of a temporary storage unit (in particular a register) to be inserted in this way has been disregarded, since in the normal case such a buffering will not be necessary, rather in one and the same

Cycle the arithmetic operations as well as the format conversions can take place.

The present conversion unit 10 also contains, as an integral hardware component, a rounding unit 15, which consists of individual logic modules and an adder, as will be explained in more detail below; Furthermore, a so-called saturation function is integrated in order to prevent a change in sign in the event of a number overflow or underflow (overflow, underflow), see also the following explanations in connection with FIGS. 6 and 7.

In the example according to FIG. 5, the accumulator 12 has a width of 80 bits (cf. the bit positions no. 0-79), and a conversion is to take place in the conversion unit 10 into a number with a width of 32 bits, which is the width of a data word in the data memory 3 corresponds. For this purpose, the format register 11 also contains in the SRC field (see Fig. 4) a value of 40 and in the DST field a value of 16, which means that the 80-bit number from the accumulator 12 (the SRC number, i.e. the source number) has its decimal point to the right of bit no. 40, whereas the 32-bit target number (DST number) should have its decimal point to the right of bit no.16 after the adaptation or conversion process.

At the beginning of the number format adaptation or conversion, the 80 bit number is expanded on both sides with the help of an expansion unit 16, namely on the right side, the LSB side (LSB Least Significant Bit) by 32 bits, i.e. by has as many bits as the target word DST, these newly added 32 bits being all set to 0. On the other, left-hand side of the MSB (MSB-Most Significant Bit), the 32 bits are also added to the extension, corresponding to the bit width of the target word, the value of these bits corresponding to the value of the sign bit derived from the Accumulator 12 is accepted, so the bit at position 79 is selected. This process is also referred to as Sign Extend (sign extension), see also the bit field SIGN (SRC) of the extension unit 16 in FIG. 5. In total, this results in a width of 32 + 80 + 32 =

144 Bits, from bit no. 0 to bit no. 143, are obtained, the bits in positions 32-111 forming the original number at output 12a of accumulator 12.

Following this, the decimal point of this number, which has been extended to a total of 144 bits, must now be adjusted in such a way that the decimal point is exactly at the required position in the

With regard to the target number, it comes to lie at the output 10a of the conversion unit 10. It is assumed that the bit no. 0 in the source number, i.e. at the output 12a of the accumulator 12, is always to the left of the decimal point as a bit with the value 2 °, so that this bit is present in the source number at position 40, where it should be at position 16 in the target number (output 10a of the conversion unit 10). There must therefore be a shift by (40-16 =) 24 bits to the right (as shown in FIG. 5). This shift is carried out with the aid of the shifting unit 17 (SHIFT), this shifting process to the right (by 24 places) being schematically illustrated by the inclined representation of its output 17a. The displacement unit 17, which can be formed, for example, by a multiplexer control block, receives the corresponding one at its control input 17b

Control information for this shift from a calculating the shift quantity

AT 413 895 Β

Control unit 17 'supplied; this control unit 17 'calculates the shift amount from the values ​​of the format specification register 11, which are at its output 11a and which are fed to the control unit 17'. The calculated shift amount results from the difference between the decimal point positions of the source format (SRC field in register 11) and the target format (DST field in register 11; see FIG. 4). Specifically, the control unit 17 ′ can thus consist of a subtracter which forms the difference between the two contents of the fields SRC and DST of the register 11, and it can also be integrated directly into the shifting unit 17 as a control stage.

In FIG. 5, the bit chain obtained in this way is schematically illustrated by a block 18, with dashed, oblique lines showing that the number originally coming from the accumulator 12 now moves a corresponding number (namely 24 bits) to the right has been postponed. With this shift, the bit positions that become free due to the shift must be filled with the correct sign on the left-hand side, ie they must be filled

Bits with the value of the sign bit of the source number (bit number 79 in accumulator 12) used for padding.

If, in contrast to what is shown in FIG. 5, a shift to the left is required (in order to provide a larger number of decimal places), then the bit positions that become free on the right-hand side are filled with 0 bits.

After this shift, the decimal point is already in the right place, corresponding to that in the target number, and the target number can now be taken from the total word - ie from the bit string 18 - as a subfield according to the desired accuracy. In the present

In this case, the accuracy for the target number results from its digits with 32 bits. The fields of the total word are not changed, but only interpreted in the format of the target number. This can also be referred to as a mask change, and in FIG. 5 this operation is illustrated by the arrow 18a. The result of this is shown in Fig. 5 illustrated with the subfield unit 19, it being evident that the actual number field 19DST (DST-Destination30 target number) is now 32 bits wide, 80 bits being contained to the left of it in a sign field 19SIGN. On the right-hand side, the bits for the digits to be cut away (decimal places) are contained in the bit positions 0 to 31, whereby a simple cut corresponds to rounding off, whereas under certain conditions, as explained in more detail below, rounding up with the help of the rounding unit 15 he follows. In the

Withdrawal of the bits for the target number (output 19a), the given number range can be exceeded or not reached. It can only be exceeded if the number of sources was positive, and undercut only if the number of sources was negative.

A logic unit 20 is provided to detect any overflow or underflow (overflow or underflow) of the number range, which via a connection 19b from the output of the subfield unit 19 sends all 80 sign bits of the sign field 19SIGN and the sign bit of the target word in the target word field 19DST (bit at position 31 , indicated in the drawing with DST (31)). In the case of a valid number in the sub-field unit 19, all sign bits are the same, either all equal to 0 or all equal to 1. With the help of an OR gate 21 it is now recognized whether all bit positions of the sign field have the value 0, and with the help of an AND gate 22 it is recognized whether all bit positions of the sign field have the value 1. The outputs of these gates 21, 22 are applied to inputs of a test block 23, which detects whether the value is exceeded or not reached, so if the output signal (output 21a) of the OR gate 21 is not equal to 0, or the output signal 22a of the AND gate 22 is not equal to 1 is. If the output signal 21a is not equal to 0 or the output signal 22a is not equal to 1, the test block 23 only has to determine whether there is an overshoot or an undershoot, and this determination is made with the help of the sign bit of the source number as it is in the accumulator 12 is included, see also connection 12s to test block 12 in FIG. 5. Has this sign bit

AT 413 895 Β (bit no. 79) has the value 0, then there is an overflow or an overflow, and a - provisional - overflow signal OFL is activated at output 23o of test block 23. However, if the sign bit has the value 1, then there is an underflow, and an underflow signal UFL is activated at the output 23u of the test block 23. This is then also what is already described in the description of FIG. 3 addressed status signal UFL at output 10b of conversion unit 10.

The evaluation result of the test block 23 is also transmitted via a connection 23a to a saturation unit 24, which is 33 bits wide, i.e. one bit more than the width io of the target number, in order to avoid a new possible overflow after a - yet to be described - To be able to recognize rounding addition.

The saturation unit 24 sets the number supplied at 19a at its output 24a 15 to the respective maximum final value in accordance with the test evaluation by the test block 23 (output 23a relating to UFL / OFL state). In more detail, this is the largest positive number in the event of an overflow (OFL), i.e. in this case all bits with the exception of the sign bits (bits 31 and 32) are set to 1, whereas the sign bits at positions 31 and 32 can be set to 0. In the event of an undershoot (UFL), the largest negative number (ie the negative number with the largest absolute amount) is output at output 24a, ie all bits in this output number are set to the value 0, with the exception of the two

Sign bits No. 31 and No. 32, which are set to the value 1. As already mentioned, a corresponding underflow signal UFL or overflow signal OFL is additionally emitted at the outputs 10b and 10c.

When truncating the lower-order bits (in the case of the subfield unit 19 to the right of the target word field

19DST, i.e. the bits at positions no. 0-31), a systematic error arises, whereby if the operations described are carried out several times (e.g. when results are accumulated in the course of filter implementations) these errors add up unfavorably and, under certain circumstances, a total malfunction of certain Algorithms can result. In order to counteract this, the aforementioned rounding unit 15 is provided, which is intended to reduce the systematic errors generated to 0 on average. In practice, for example, so-called ΙΕΕΕ-rounding can be used (see, for example, IEEE Standard for Binary Floating-Point Arithmetic IEEE 754-1985). With this rounding, rounding up is carried out if and only if at the decimal places (here the bit positions no. 0-31) at least one 1 bit in addition to a 1 bit occurs somewhere at position no. 31 (a single such additional 1 bit is sufficient), or if only bit no. 31 has the value 1, and if the LSB bit in the target word field 19DST also has the value 1. Such rounding up means that, with the aid of an adder 25, a 1 (generally: the smallest positive value) is added to the number obtained at the output of the saturation unit 24. A logic 40 unit 26 with an OR gate 27 and an AND gate 28 detects whether such rounding (rounding up exactly) is actually to be carried out. For this purpose, the least significant bit (LSB bit) from the target word field 19DST (see connection 19c) and the truncated bits (see connection 19d) are applied to the OR gate 27, whose output 27a as well as bit no. 31 of the truncated lower bits (see output 19e) to the AND gate 28 is applied. The aforementioned ΙΕΕΕ-rounding provides for rounding up, i.e. adding a 1 in adder 25 (output 1 of AND gate 28, connection 28a) if any bit 19d or 19c is set to 1 and at the same time bit 19e (bit No. 31 of subfield unit 19) also has the value 1.

However, such a rounding up only takes place if the test block 23 has not detected any undershoot (signal UFL), ie an input of the adder 25 is also at the output 23u of the test block 23. If such an undershoot has not been detected and rounding up to be carried out, then the adder 25 adds the smallest possible positive number to the result in the output 24 a of the saturation unit 24.

ο

AT 413 895 Β

Since such rounding up can again lead to a number overflow (overflow OFL), a further saturation unit 29 is connected to the output 25a of the adder 25, and this saturation unit 29 limits the output result (the Target word) to the highest possible

Numerical value. This highest possible numerical value is output at output 29a and stored in a register 30. If there is no overflow, the number received from adder 25 is written directly into register 30. In the event of an overflow, a corresponding OFL signal is output at output 29b of saturation unit 29, and this OFL signal is linked to the OFL signal at output 23o of test block 23 according to an OR function io, see OR gate 31 in FIG Fig. 5, so that a corresponding OFL signal is received at the output 10c of the conversion unit 10 even in the event of an overflow.

It can be seen from the above that in the event that the number is not exceeded or not reached when returning to the subfield (see subfield unit 19), the units 24,

25th and 29 remain inoperative and the output number 19a of the subfield unit 19 goes directly to the

Register 30 (as output storage means) arrives and is stored there.

This completes the conversion of the number format and any rounding, and the end result, ie the target number DST, with the desired bit width (corresponding to the bit width of the

Target number field 10DST of subfield unit 19) can now, as explained above with reference in particular to FIGS. 1 and 3, be written back into the general data memory 3 as result Y. The status signals UFL and OFL, on the other hand, are loaded into the status register 14 (cf. FIG. 3).

As a supplement, the so-called 2's complement representation of the binary numbers will now be briefly explained as an example with reference to FIGS. 6 and 7, since this 2's complement representation was used as the basis for the operations according to FIG. In FIG. 6, 4-bit binary numbers provided with a sign bit S are illustrated in a table, the value range in this example extending from -8 to +7. The positive numbers are shown at P, the negative numbers at N. As can be seen, when the sign bit S has the value 0, the number is positive (the number 0 should also be added to the positive numbers); If, on the other hand, the sign bit S is 1, the number is a negative number N. When adding or subtracting, the case can now arise that the number range limits are exceeded or undershot, see arrows 40 and 41 in FIG. 6. For example, in the case of a

Addition of a positive number to a positive number (see arrow 40) the range P of positive numbers are exceeded (overflow), so that a negative number is created, since the bit word 0111 (for the number +7) in the binary number representation shown is the The number 1000 follows, but it is already the largest negative number (-8). Similarly, if a negative number is added (in terms of amount) to a negative number (see arrow 41 in Fig. 6), a positive number arise (namely with a 0 in the place of the sign bit S), so that there is an underflow or an undershoot of the value range.

FIG. 7 also shows 4-bit binary numbers with a sign (again in the 1st column of the bits) with integer components I (1-integer) and two decimal places F (F45 fraction), the range of values ​​of these binary numbers being from -2 to +1.75. If the IEEE rounding mentioned above with reference to FIG. +2, the decimal places should be cut away; however, no rounding up would be performed on the number +0.5. In this ΙΕΕΕ-round, the number 0.5 is rounded down, 0.51 is already rounded up, the number 1.5 is also rounded up, but not the number 2.5, but again the number 3.5, etc.

8 and 9 are in the form of simplified bit representations shown in lines (1) to (8) (with much smaller bit widths compared to FIG. 5) examples with format conversion and rounding, one with an overflow (FIG. 8) and once with a shortfall (Fig. 9),

1

AT 413 895 B illustrates.

In detail, the 1st line in FIG. 8 shows an 8-bit source number SRC which contains an integer 4-bit portion and 4-bit decimal places. The leftmost bit in the integer parts is the sign bit S. The target number DST shown in the 8th line, on the other hand, consists of 6 bits, with the first three bits representing the whole number parts including the sign bit and the other three bits representing the decimal places . The value of the source number SRC is +7.9375, which corresponds to the largest representable value here.

According to line (2), an extension is made to the left of the sign bit S, with the same number (namely 6) of bits (here 0 bits) as the number of bits of the target number DST being added. At the same time, exactly as many 0 bits (i.e. 6 0 bits) are appended to the right of the source number SRC.

For the shift now required, the difference between the number of decimal places of the source number SRC and that of the target number DST is to be calculated (which is accomplished in FIG. 5 with the control unit 17), and this difference is 1 in the example of FIG the bit string is shifted one position to the right, see line (3) in FIG. 8; the left-hand side is filled with the value of the sign bit, ie an O-bit is specifically added here. Then, according to line (4) in FIG. 8, a new mask is placed over this chain, now with only 6 digits, corresponding to the number of bits of the target number DST. This mask can be seen in FIG. 8 by a shorter block (compared to lines (1) to (3)). As can be seen, this makes the 6-bit number in the 4th line of FIG. 8 negative (1-bit in the leftmost position). The 9 bits to the left of this (including the sign bit of the target number) are now checked for equality, and since they are not all the same, an underflow / overflow condition is determined, see logic unit 20 in FIG to determine whether there is an overflow or an undershoot, the sign bit of the source number SRC is used; this sign bit has the value 0 in the present case, so that a

Overflow (OFL) is detected. If the sign bit of the source number SRC had the value 1, an underflow would be detected. With the help of the saturation unit 24 (FIG. 5), the target word DST now receives the highest positive value, as can be seen from the 5th line in FIG. 8, this value now being +3.875. The rounding unit 15 (see FIG. 5) recognizes at R in FIG. 8th the need for rounding up, the rounding unit 15 using the 7 rightmost bits for this. Accordingly, the target number DST is incremented by the value 0.125 (the smallest representable value with 3 bits), this added value being shown in the 6th line of FIG. 8, whereas the highest positive value obtained by the saturation unit 24 is shown in FIG the 5th line is shown.

This addition of the numbers again results in a negative number, see the 6th line in FIG. 8, which is recognized by the second saturation unit 29 (see FIG. 5). The target number is therefore again set to the largest positive value, which is shown in the 7th line of FIG. 8, and the number thus obtained is passed to the register 30 (see FIG. 5) as the final target number DST, as in FIG 8th line of Fig. 8 is illustrated. At the same time, a corresponding overflow signal OFL is also output to the status register 14 (see FIG. 3).

In the example in FIG. 9, the source number SRC is again an 8-bit number with a sign bit S and 4-bit decimal places, the illustrated source number SRC having the largest negative value (in terms of absolute value), namely -4,000. The target number should again have 6 bit positions, and according to this number of bits, the sign bits are extended with six 1 bits on the left-hand side according to the 2nd line of FIG. 9, whereas the bits on the right-hand side are filled with 0s. Then again - see the 3rd line of FIG. 9 - the chain is shifted by one place to the right, with a 1 bit being inserted again on the left-hand side. When changing the mask, according to the 4th line in FIG. 9, the number of bits to 6, according to the

To reduce the number of bits of the target number DST, it can be seen that the number is now one

2

AT 413 895 Β has assumed a positive value (the left bit, the sign bit, has the value 0), and the overflow / underflow test also determines that the 9 bits on the left are not the same. Therefore, since this is recognized as an underflow, the number is set to the largest negative value, see the 5th line in Fig. 9. Underflow (OFL / UFL) in this example shows that there is an underflow or undershoot, since the sign bit S of the source number SRC has the value 1.)

In the event of an underflow, however, the adder 25 is not able to add any rounding result to the target number, ie the number remains the same at the output of the adder 25, see the 6th line in FIG Overflow or underflow (7th line in FIG. 9) and forwards the numerical value unchanged to the following register 30, see 8th line in FIG. 9.

The configuration described in particular with reference to FIG. 5 can in practice preferably be implemented in combinatorial logic (i.e. in particular with AND and OR gates and with multiplexer chains for shifting, etc.) without storing elements (registers) being provided in between. In this way it is achieved that the format adjustments and any rounding operations can also take place in the same clock cycle in which the arithmetic operations are carried out. If very short cycle times are to be achieved, memory elements (registers) can also be provided between individual units, as already mentioned.

The ΙΕΕΕ-rounding was explained above in connection with the rounding as an example. Of course, other types of rounding are also conceivable within the scope of the invention, such as commercial rounding, simply cutting away the rear positions and other known types of rounding. The only important thing here is that the corresponding logic is implemented in terms of hardware, instead of providing programming for the arithmetic unit 4.