AT413648T

Methods and apparatus for controlling a cache memory

Abstract

A method for controlling a cache (110, 110A) memory, comprising the steps of: receiving (300) an address (204) to at least one of the options of writing data to and retrieve data from the cache, including label address bits and index bits; accessing (302) one or more cache lines (200) corresponding to the cache index bits of the address; each cache line including an address label (210), a data validity flag (212A) and a flag data type (212B); determining (304) whether data in at least one of the one or more cache lines is valid based on the validity flag data; determining (312) what type of data is stored in at least one cache line based on the flag data type; and prohibit (322) overwriting floating point data in the at least one cache line when the same data are valid and the data stored in the at least one cache line are integer data.

Term

No projected expiry on record.

  1. Priority
  2. Filed
  3. Granted
  4. Today

13 members in 8 offices

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Priority claims
DocumentOfficeKindDate
37819902United States of AmericaP
18715002United States of AmericaA

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US2003208661A1United States of AmericaA1
AU2002333656A1AustraliaA1
WO03096194A1World Intellectual Property Organization (WIPO)A1
US6751707B2United States of AmericaB2
EP1502191A1European Patent Office (EPO)A1
JP2005524905AJapanA
EP1502191A4European Patent Office (EPO)A4
JP3974131B2JapanB2
EP1502191B1European Patent Office (EPO)B1
AT413648TThis recordAustriaT
ATE413648T1AustriaT1
DE60229790D1GermanyD1
ES2316653T3SpainT3