Mosfet controlling multiplier

(54) A MOSFET CONTROL MULTIPLIER CIRCUIT (57) A MOSFET control multiplication circuit is characterized in that a MOSFET linear device (1) for linearly varying the output current (I) to a node (A) in accordance with an input voltage from an input voltage source (Vg) and a symmetrical input voltage of two voltage sources (Vx and -Vx) is provided, wherein the MOSFET linear device (1) comprises: a first resistance element (10) connected to one of the two voltage sources (Vx); a first MOSFET (M1) having a gate electrode (Gl) connected to the input voltage source (Vg), a drain electrode (D1) connected to the first resistance element (10), and a source electrode (S1); a second resistance element (20) connected to the other of the two voltage sources (-Vx) and the source electrode (S1) of the first MOSFET (M1); a first current source (30) functioning as a current source QQ for offset control connected to the one of the two voltage sources (Vx) and to the node (A); a second current source (40) for the current mirror circuit connected to the node (A) and to the other of the two voltage sources (-Vx); and that an impedance element (Z) is provided, at which a voltage (Vo) occurs, wherein the impedance element (2) to the node (A) of the MOSFET linear device (1) and ground is connected.

<img file="AT398010B_D0001.tif" />

AT 398 010

BR 0078313

AT 398 010 Β

The present invention relates to a MOSFET control multiplying circuit.

The development of VLSI (Largest Scale Integration) technology has created the need to bring integration technology into not only digital systems but also analog systems. For example, digital technology is used for computers and also in a new field where it is possible to achieve either humanization or the use of a neural communication technology network between remote systems or between user connections. Under these circumstances, both in a classical sense of the algorithmic aspect and in a simulated realization aspect, that is, a real connection from the outside, there are limitations in the digital system of the prior art VLSI technique. Problems arise for the multiplication process based on a method using VLSI technology because the width required for the necessary chips is considerably increased and the speed of operation of the system for performing the synchronization operation of the system is limited. In addition, the technology of the analog integrated circuit has difficulty in realizing the VLSI technology because of its limited precision and difficulty in system construction.

Therefore, it is an object of the present invention to solve the above-mentioned problems and to provide a MOSFET control multiplying circuit in which a precise function of operational multiplication is offered, with both VLSI technology - which has the advantage of reaching the digital system is - as well as a new analog integrated circuit is used.

Furthermore, it is an object of the present invention to provide an analog-digital hybrid type artificial neural synapse to realize a scheme for the new generation of computer technology.

These objects are achieved in a MOSFET control multiplying circuit according to the invention by providing a MOSFET linear device for linearly varying the output current to a node according to an input voltage from an input voltage source and a balanced input voltage from two voltage sources. wherein the MOSFET linear device comprises: a first resistance element connected to one of the two voltage sources; a first MOSFET having a gate electrode connected to the input voltage source, a drain electrode connected to the first resistive element, and a source electrode; a second resistance element connected to the other of the two voltage sources and the source electrode of the first MOSFET; a first current source acting as a current source for offset control connected to the one of the two voltage sources and to the node; a second current source for the current mirror circuit connected to the node and to the other of the two voltage sources; and that an impedance element is provided at which a voltage occurs, wherein the impedance element is connected to the node of the MOSFET linear device and ground. This provides a MOSFET control multiplication circuit for obtaining the accurate function of operational multiplication by offsetting the offset voltage of a MOSFET by employing balanced voltages applied across a resistive MOSFET and a current mirror circuit to remove the non-linear current from the MOSFET and Accuracy of the multiplier significantly improve.

Another MOSFET pulse repetitive circuit is characterized by comprising: a first MOSFET having a source electrode, a drain electrode and a gate electrode, the gate electrode being connected to an input voltage source; a fourth MOSFET having a gate electrode and a drain electrode connected to each other so as to be connected to the one of two balanced voltage sources, and a source electrode connected to the drain electrode of the first MOSFET; a fifth MOSFET having a source electrode, a gate electrode and a drain electrode, the drain electrode and the gate electrode being connected together to be connected to the source electrode of the first MOSFET, the source electrode being connected to the other of two balanced voltage sources; a third MOSFET having a drain electrode connected to the drain electrode and gate electrode of the fourth MOSFET and one of two power sources, and a source electrode connected to a node and a gate electrode to which a reference voltage from a reference voltage source is applied ; a second MOSFET having a source electrode, a gate electrode and a drain electrode, the drain electrode connected to the node, and wherein the source electrode is connected to the source electrode of the fifth MOSFET and the other of two voltage sources; and an impedance element at which a voltage occurs, wherein the impedance element is connected to the node and ground.

A further MOSFET control multiplication circuit is according to the invention characterized in that it comprises: a first MOSFET having a source electrode, a drain electrode and a gate electrode, the gate electrode being connected to a voltage source; a fourth MOSFET with a

AT 398 010 B

A gate electrode and a drain electrode connected to each other and to one of two balanced voltage sources, and a source electrode connected to the drain electrode of the first MOSFET; a fifth MOSFET having a source electrode, a gate electrode and a drain electrode, the drain electrode and the gate electrode connected to each other and to the source electrode of the first MOSFET, the source electrode of the fifth MOSFET being connected to the other of two balanced voltage sources; a third MOSFET having a drain electrode connected to the drain electrode and gate electrode of the fourth MOSFET and to one of two voltage sources, and a source electrode connected to a node and a gate electrode for applying a reference voltage from a reference voltage source connected is; a second MOSFET having a source electrode, a gate electrode and a drain electrode, said drain electrode connected to said node, said source electrode connected to said source electrode of said fifth MOSFET and the other of two voltage sources; an impedance element at which a voltage occurs, wherein the impedance element is connected to the node and ground; and an eighth MOSFET connected between the node and the impedance element and having a gate electrode for applying a neural state signal to thereby function as a neural synapse network.

Another MOSFET control multiplying circuit is characterized by comprising: a first MOSFET having a source electrode, a drain electrode and a gate electrode, the gate electrode being connected to a power source; a fourth MOSFET having a gate electrode and a drain electrode connected to each other and to one of two balanced voltage sources and a source electrode connected to the drain electrode of the first MOSFET; a fifth MOSFET having a source electrode, a gate electrode and a drain electrode, wherein the drain electrode and the gate electrode are connected to each other and to the source electrode of the first MOSFET, and wherein the source electrode of the fifth MOSFET is connected to the other of two balanced voltage sources; a third MOSFET having a drain electrode connected to the drain electrode and gate electrode of the fourth MOSFET and to one of two voltage sources, and a source electrode connected to a node and a gate electrode to which a reference voltage from a reference voltage source is applied ; a second MOSFET having a source electrode, a gate electrode and a drain electrode, the drain electrode connected to the node and the source electrode connected to the source electrode of the fifth MOSFET and to the other of two voltage sources; an impedance element at which a voltage occurs, wherein the impedance element is connected to the node and ground; wherein the connected first, second, third, fourth and fifth MOSFETs define a MOSFET linear device, a sixth MOSFET is connected between the one of two voltage sources and the MOSFET linear device to receive voltage from the one of two voltage sources and a seventh MOSFET interposed between the other of two voltage sources and the MOSFET linear device is connected to receive voltage from the other of two voltage sources, wherein each of the sixth and seventh MOSFETs further includes gate electrodes connected to each other to obtain a neural state signal, thereby to function as a neural network of synapses.

A specific embodiment of the MOSFET analog multiplication circuit according to the invention is shown in the drawings. In summary, the invention relates to a MOSFET controlled multiplier circuit, the MOSFET linear devices 1 for linearly varying the to a node A, ie a particular connection point, output output current I according to an input voltage from an input voltage source Vg and a balanced input voltage from voltage sources Vx and -Vx. The input voltage from an input voltage source Vg is associated with the operation of the balanced input voltage from the voltage sources Vx and -Vx. An impedance element Z supplies a voltage Vo, the impedance element Z being connected to the node A of the MOSFET linear device 1 and ground.

The MOSFET linear device preferably comprises a first resistance element 1Q connected to a voltage source Vx and to a drain of a MOSFET M1. (The term "connected" means that the particular element in the circuit of the present invention is connected in such a way that the purpose of the circuit is achieved, ie the MOSFET linear device t outputs a linearly varying current I and the impedance element Z supplies a voltage Vo.) A gate electrode G1 of the MOSFET M1 is connected to a voltage source Vg. A second resistance element 20 is connected to a voltage source -Vx and a source electrode S1 of the MOSFET Ml. A first current source 30, which functions as a current source for offset control, is connected to the voltage source Vx and to the node A. A second current source 40 for the current mirror 3

ΔΊ 398 010 Β

Circuit is connected to node A and to voltage source -Vx.

The first resistance element 10 is preferably a MOSFET M4 whose gate electrode G4 and drain electrode D4 are connected to each other and connected to the voltage source Vx, and whose source electrode S4 is connected to the drain electrode D1 of the MOSFET M1.

The second resistance element 20 is preferably a MOSFET M5 whose drain electrode D5 and gate electrode G5 are connected to each other and connected to the source electrode S1 of the MOSFET M1, and whose source electrode S5 is connected to the voltage source -Vx.

The first current source 30 is preferably a MOSFET M3 whose drain electrode D3 is connected to the voltage source Vx and to the first resistive element 10, whose source electrode S3 is connected to the node A and whose gate electrode G3 is connected to a reference voltage of a voltage source Vr.

The second current source 40 is preferably a MOSFET M2 whose drain electrode D2 is connected to the node A and whose source electrode S2 and gate electrode G2 are respectively connected to the second resistance element 20 and the voltage source -Vx.

A MOSFET M8 may be turned on between the node A and the impedance element Z. The gate electrode G8 of the MOSFET M8 receives a neural state signal NZS and thereby functions as a neural synapse network.

A MOSFET M6 may be connected between the voltage source Vx and the MOSFET linear device 1 to obtain voltage from the voltage source Vx. A MOSFET M7 may be connected between the voltage source -Vx and the MOSFET linear device 1 to obtain voltage from the voltage source -Vx, the gate electrodes G6, G7 of the MOSFETs M6, M7 being connected together to receive a neural state signal NZS and to thereby function as a neural network of synapses.

The preferred MOSFET multiplier circuit includes a number of MOSFETs and an impedance element. More specifically, the preferred MOSFET multiplier circuit includes a MOSFET M1 having a source electrode S1, a drain electrode D1, and a gate electrode G1, the gate electrode G1 being connected to a voltage line Vg. A MOSFET M4 is used whose gate electrode G4 and drain electrode D4 are connected to each other and connected to a voltage source Vx, and whose source electrode S4 is connected to the drain electrode D4 of the MOSFET M1. There is used a MOSFET M5 whose drain electrode D5 and gate electrode G5 are connected to each other and connected to the source electrode S1 of the MOSFET M1, and whose source electrode S5 is connected to a power source -Vx. There is used a MOSFET M3 whose drain electrode D3 is connected to the voltage source Vx whose source electrode S3 is connected to the node A and whose gate electrode G3 is connected to receive a reference voltage from a voltage source Vr. In the multiplier circuit, a MOSFET M2 is used which has a source electrode S2, a gate electrode G2 and a drain electrode D2. The drain electrode D2 of the MOSFET M £ is connected to the node A, the source electrode S2 of the MOSFET M2 is connected to the source electrode S5 of the MOSFET M5 and to the voltage source -Vx and the gate electrode G2 of the MOSFET M2 is connected to the gate electrode G3 of the MOSFET M3 and the source electrode S1 of the MOSFET M1. The impedance element Z supplies a voltage Vo, wherein the impedance element Z is connected to the node A and ground.

Preferably, the MOSFET multiplier circuit further comprises a MOSFET M8 connected between the node A and the impedance element Z, wherein the gate electrode G8 of the MOSFET M8 receives neural state signal NZS and thereby functions as a neural synapse network.

The MOSFET multiplier circuit comprises a number of connected MOSFETs M1, M2, M3, M4 and M5, which define a MOSFET linear device 1. The MOSFET multiplier circuit further comprises a MOSFET M6 connected between the voltage source Vx and the MOSFET linear device 1 to connect the voltage line Vx and the MOSFET linear device 1 with each other. A MOSFET M7 is connected between the voltage source -Vx and the MOSFET linear device 1 to connect the voltage source -Vx and the MOSFET linear device 1 with each other. Each of the MOSFETs M6 and M7 further includes a gate electrode G6, G7 connected to each other to receive a neural state signal NZS to thereby function as a neural network of synapses. That is, the MOSFETs M6 and M7 are respectively connected between the power sources Vx, -Vx and the MOSFET linear device 1, and their gate electrodes G6, G7 are connected to receive a neural state signal and thereby function as a neural network of synapses. An impedance element Z supplies a voltage Vo, the impedance element Z being connected to node A and ground

In a preferred embodiment, the MOSFET M6 is connected to a voltage source Vx and to the MOSFETs M4 and M3 of the MOSFET linear device 1. The MOSFET M7 is with the Span4

AT 398 010 B source -Vx and connected to the MOSFETs M2 and M5 of the MOSFET linear device 1, wherein each MOSFET M6 and M7 further includes gate electrodes G6, G7, which are connected together to receive a neural state signal and thereby as a neural Synapse network to act.

The more salient and more important features of the present invention have been set forth above in order that the detailed description of the invention which follows may be better understood and the present contribution to the art fully appreciated. Additional features of the invention described below form the subject of the claims of the invention. Those skilled in the art will appreciate that the concept and specific embodiment disclosed herein may be readily utilized as a basis for modifying or planning other structures for carrying out the same purposes of the present invention. It will be further understood by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the claims.

In order to better understand the nature and objects of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings, in which:

Fig. 1A is a symbol of a MOSFET;

Fig. 1B illustrates an equivalent circuit in a non-saturation region of a MOSFET; Fig. 2 illustrates a simplified schematic circuit of the present invention;

Fig. 3 illustrates a circuit of the MOSFET control multiplying circuit according to the present invention;

Fig. 4 illustrates a first embodiment of the present invention; and Figure 5 illustrates a second embodiment of the present invention.

Like reference numerals refer to like components throughout the several views of the drawings.

Fig. 1A shows a symbol of a MOSFET having a gate electrode G, a source electrode S and a drain electrode D.

Fig. 1B shows an equivalent circuit of a MOSFET in the unsaturation region, wherein the drain current characteristics in the resistance region can be expressed by the following equations:

COX * W "} 1 ^{1 -} ~ 2L 1 (COX'W * / 1)

RL • (-V^ads) .... (1) •• (Vgs - Vt) ..... (2) the mobility of the majority carrier, the copositive reactance of the gates per unit area, the length of the channel, the width of the channel (normal direction to L ), the voltage between the drain electrode D and the source electrode S, the voltage between the gate electrode G and the source electrode S, the threshold voltage.

Fig. 12 is a schematic view of the present invention, wherein a voltage source Vx through which U:

Cox:

L:

W:

ds:

gs:

Vt:

FIG.

Furthermore, the voltage source Vx is connected to the voltage source -Vx through a first current source 3Q, a node A, and a second current source 40. The first voltage source is connected to a first resistance element 10, a MOSFET M1 and a second resistance element 20. Further, the potential gradient Vxp of the drain electrode Dl of the MOSFET M1 has a symmetrical relation to the potential level -Vxp of the drain electrode DI of the MOSFET M1. A voltage source Vg is connected to the gate electrode G1 of the MOSFET M1, the operational description of which is given below. It will be noted that, as shown in the drawing, the voltage sources Vx and -Vx simultaneously provide balanced input voltage.

Referring to the drawing, the current 11 flowing through the resistance MOSFET M1 can be expressed by the following equation:

AT 398 010 Β

II = (Cox * W'U) / L [(Vgs-Vt) Vds -V¹ds / 2] = a [(Vg + Vxp - Vt) 2Vxp - 4Vxp^x/ 2] = a (Vg - Vt) 2Vxp = a-Vg-Vds -β ...... (3) where a = (Cox «W« w) / L

Vd = Vxp, Vs = -Vxp

Vds = 2Vxp and β is an offset.

Therefore, as is apparent from equation (3), when the β term is offset by using a current source (such as a current mirror circuit) of the same size as that of current source I to eliminate the offset noise, the quadratic term is calculated from the equation ( 1), so that the resulting current I obtains a value proportional to the product of the input voltages from the voltage sources Vg and Vds, This results in a basis for an application for a multiplier circuit.

Fig. 3 illustrates a circuit of the MOSFET multiplying circuit according to the present invention. The voltage source Vx is connected through a MOSFET M4 to S of a gate electrode G4 and its drain electrode D4, the source electrode S4 of this MOSFET M4 being connected to the drain electrode D1 of the MOSFET M1, the voltage of the voltage source Vg being applied to the gate electrode G1 of the MOSFET M1 and wherein the source electrode S1 of the MOSFET M1 is connected both to the drain electrode D5 and to the gate electrode G5 of another MOSFET M5, whose source electrode S5 is connected to the voltage source -Vx. Further, the voltage source Vx through a MOSFET M3 functioning as a current source for offset control is a node A, ie a special connection point, and a MOSFET M2 for current mirror circuit having a gate electrode G2, which is connected to the gate electrode G5 of the MOSFET M5, connected to the voltage source -Vx, whereby a MOSFET linear device 1 is formed with input terminals connected to the voltage sources Vx and .Vx are connected. At node A, an output voltage Vo is output and node A is connected through an impedance element Z to ground. The operation description thereof follows below.

Since the output current I flows linearly, both due to current I1 equivalent to the current flowing through MOSFET M1 and flowing through MOSFET M2, which functions as a current mirror circuit, and due to current I2 acting as one Current source for offset control and flows through the MOSFET M3, the output voltage Vo is supplied by the impedance element, where the output voltage Vo receives a value, which is proportional to the product of the input voltages from the voltage sources Vx and Vg. Such a product function can be realized by providing a circuit of Fig. 3 according to the invention, wherein the primary linear relationship in the non-saturation region of MOSFET is emphasized. It is noted that a reference voltage Vr is applied to the gate electrode G3 of MOSFET M3 to control the current flowing through the MOSFET M2 to be equal to the current flowing through the MOSFET M1.

Fig. 4 illustrates a first embodiment of the present invention in which a MOSFET M8 is connected between the node A and the impedance element Z so as to receive a neural state signal NZS through its gate electrode G8, thereby functioning as a neural synapse network. According to the above-described embodiment, when the voltage from the voltage source Vx is set at a predetermined level, the voltage from the voltage source Vg acts as a synapse weight of the neural network and the neural state pulse signal is applied to the gate electrode G8 of the MOSFET M8 a circuit for realizing the basic structure of the neural network of synapses, which obtains the neural state using an integrating capacitor not shown. A new hybrid neuronal network can also be realized which, although using only a few MOSFETs, can still perform a fully asynchronous operation with a high processing speed.

Fig. 5 shows a second embodiment of the present invention wherein the MOSFETs M6 and M7 may be provided at the input terminals, ie both between the voltage source Vx and the MOSFET M4 and between the voltage source -Vx and the MOSFET M5. The gate electrodes G6 and G7 of the MOSFETs M6 and M7 are connected to each other, thereby making it possible to supply the neural-state input signal NZS therethrough. Therefore, if no

AT 398 010 Β

Input signal is applied to it, which are eliminated at the MOSFETs Mt and M2 existing load current.

According to the second embodiment of the present invention, another new neuronal

Synapse Network, which minimizes the consumption of power required for high system health.

As described above, according to the present invention, not only a simple and an accurate result can be obtained by taking advantage of the primary linear characteristics of MOSFETs, but also realizing a mixed analog-digital type of artificial neural network which is available for realizing the neural network so that the technical principle of the present invention can be advantageously applied to the computer systems of the new generation.