Mosfet analog multiplier

(54) MOSFET ANALOG MULTIPLIER CIRCUIT (57)

There is provided a MOSFET analog multiplier circuit having a variable resistance MOSFET linear device for linearly varying output current I in response to a balanced input voltage from voltage sources V2 and -V2 and an input voltage from an input voltage source VI operating with the balanced input voltage from the voltage sources V2 and -V2 is disclosed, wherein the variable resistance MOSFET linear device has a node A, to send the varied output current I as an output therethrough; and an operational amplifier unit for amplifying the linearly varied output current I including an operational amplifier U having an inverting input connected to the node A of the MOSFET linear device, a grounded non-inverting input, and an output. The operational amplifier unit further includes a feedback element Z connected between the inverting input and the output of the operational amplifier U, the output providing a voltage Vo.

AT 397 443

<img file="AT397443B_D0001.tif" />

jjvReews

The invention relates to a variable resistance MOS-FET analog multiplier circuit, and more particularly to a variable resistance MOSFET analog multiplier circuit using a variable resistance MOSFET linear device comprising two MOSFETs for removing the non-linear current of the MOSFET, thereby improving the accuracy of the multiplier circuit is significantly improved.

Recently, the development of VLSI (Largest Scale Integration) technology has resulted in the need to introduce the integration technology not only to the digital system but also to the analog system. Thus, digital technology is used not only for computers, but also in a new field where it is possible to achieve either humanization or the achievement of a neutral communication technology network between remote systems or between user connections. Under the circumstances there are, both in a classical sense algorithmic aspect and in a simulated realization aspect, that is, a real connection from the outside, there are limitations in the prior art digital VLSI technology system. Problems arise for the multiplication process based on a method using VLSI technology because the width required for the necessary chips is considerably increased and the speed of operation of the system for performing the synchronization operation of the system is limited.

In addition, the technology of the analog integrated circuit has difficulty in realizing the VLSI technology because of its limited precision and difficulty in system construction itself.

Therefore, it is an object of the present invention to solve the problems set forth above and to provide a MOSFET analogue multiplication circuit which provides precise function of operational multiplication, with both VLSI technology having the advantage of being a digital system and a new analog integrated circuit is used.

Furthermore, it is an object of the present invention to provide an analog-digital hybrid type artificial neural synapse to realize a scheme for a new generation of computer technology.

The above objects are intended only to illustrate some of the salient features and applications of the present invention. By applying the disclosed invention in a different manner or varying the invention within the scope of the disclosure, many other positive results can be obtained. Accordingly, other objects and a fuller understanding of the invention may be obtained by reference to the following summary of the invention and detailed description, which, taken in conjunction with the annexed drawings, describes the preferred embodiment in addition to the scope of the invention as defined by the claims.

The MOSFET analog multiplier circuit according to the present invention is defined by the claims, and a specific embodiment is shown in the accompanying drawings. In summary, the invention relates to a MOSFET analog multiplier circuit, characterized in that it comprises:

a first MOSFET having a gate electrode connected to a first voltage source, a drain electrode connected to a second voltage source, and a source electrode;

a second MOSFET having a source electrode and a gate electrode connected to the negatively poled second voltage source and a drain electrode, the second voltage sources providing balanced input voltages, and wherein the source electrode of the first MOSFET and the drain electrode of the second MOSFET are connected to a node providing a linearly variable output current to define a variable resistance MOSFET linear device;

an operational amplifier for amplifying the linearly varied output current whose inverting input is connected to the node of the variable resistance MOSFET linear device and whose non-inverting input is grounded, and which comprises an output; and a feedback element connected to the inverting input and the output of the operational amplifier and providing an output voltage at its output; and a third MOSFET connected between the node and the inverting input of the operational amplifier, the third MOSFET having a gate electrode to which a neural state signal as an input signal is applied.

It is advantageous if the first and second MOSFETs are depletion MOSFETs.

A variant of the MOSFET analog multiplication circuit according to the invention is characterized in that it comprises:

a first MOSFET having a gate electrode connected to a first voltage source, a drain electrode connected to a second voltage source, and a source electrode;

a second MOSFET having a source electrode and a gate electrode connected to the negatively poled second voltage source and a drain electrode, the second voltage sources providing balanced input voltages, and wherein the source electrode of the first MOSFET and the drain electrode of the second MOSFET are connected to a node providing a linearly variable output current to define a variable resistance MOSFET linear device;

-2AT397443B an operational amplifier for amplifying the linearly varied output current whose inverting input is connected to the node of the variable resistance MOSFET linear device and whose non-inverting input is grounded, and which comprises an output; and a feedback element connected to the inverting input and the output of the operational amplifier and providing an output voltage at its output; and a fourth MOSFET connected between the second voltage source and the drain electrode of the first MOSFET of the variable resistance MOSFET linear device; and a fifth MOSFET connected between the negative-pole second voltage source and the source and gate electrodes of the second MOSFET, wherein the gate electrodes of the fourth and fifth MOSFETs are connected to receive a neural-state signal as an input signal.

It is advantageous if the first and second MOSFETs are depletion MOSFETs.

Above, the more salient and more important features of the present invention have been set forth in order to facilitate a better understanding of the following detailed description of the invention and a proper assessment of the present contribution to the prior art. Further features of the invention described below are the subject of the claims of the invention. Those skilled in the art may appreciate that the concept and specific embodiment of the invention disclosed herein may be readily utilized as a basis for altering or planning other structures for carrying out the same purposes of the present invention.

In order to better understand the nature and objects of the invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, in which:

Fig. 1A illustrates a symbol of a MOSFET; Fig. 1B illustrates an equivalent circuit in the non-saturation region of the MOSFETs; Fig. 2 illustrates a main circuit according to the present invention; Fig. 3 illustrates a circuit of a MOSFET analog multiplier circuit according to the present invention; Fig. 4 illustrates a first embodiment of the present invention; and Figure 5 illustrates a second embodiment of the present invention

Like reference numerals refer to like parts throughout the drawings.

Fig. 1A diagrammatically illustrates a circuit symbol of a MOSFET having a gate electrode (G), a source electrode (S) and a drain electrode (D). Fig. 1B shows an equivalent circuit of a MOSFET in the unsaturation region, wherein the drain current characteristics in the resistance region can be expressed by the following equations;

Cox «W« g V²ds I --- ... (1)

L 2 r = -... (2) (Cox · W · g) / L (Vgs - Vt) where μ: the mobility of the majority carrier

Cox: the gate capacitance per unit area

L: The length of the channel

W: The width of the channel (vertical direction to L)

Vds: The voltage between the drain and the source

Vgs: The voltage between the gate electrode and the source electrode

V t: The threshold voltage means.

Fig. 2 is a schematic view of the present invention wherein, in order to remove the nonlinear piezoelectric component of equation (1), two MOSFETs (Q1) and (Q2) (which are of the depletion type) are employed as shown, wherein the source electrode (S1 ) of the MOSFET (Ql) is connected to the drain electrode (D2) of the MOSFET (Q2) to obtain a current (I) at the output. The gate electrode (G1) of the MOSFET (Q1) is connected to a voltage source (VI) and the drain electrode (D1) is connected to a voltage source (V2) so that the current (II) flows from the voltage source (V2) to the MOSFET (Q1) , The source electrode (S2) and the gate electrode (G2) of the MOSFET (Q2) are connected to the voltage source (-V2), so that the current (12) flows from the MOSFET (Q2) to the voltage source (-V2). The voltage sources (V2) and (-V2) supply the MOSFETs (Q1) and (Q2) with balanced input voltages.

The current-voltage characteristics of the MOSFETs (Q1) and (Q2) can be expressed by the following equations:

The current-voltage characteristic of the MOSFET (Q1) is shown below as follows II = (Cox * W * u) / L [(Vgs -Vt) * Vds -V²ds / 2] ... (3)

-3AT397443B and the voltage characteristic of the MOSFET (Q2) is given as follows:

= (Cox · W · u) / L ((-Vt) · Vds - V^{1 2}ds / 2] ... (4).

Therefore, the resulting current-voltage relationship can be calculated using equations (3) and (4) as follows:

I = 11-12 = (Cox * W * g) / L [Vgs * Vds] = α * Vgs * Vds ... (5), where α = (Cox * X * g) / L.

From the above it can be seen that the quadratic term is eliminated from the results

Fig. 3 shows a circuit of a MOSFET analog multiplication circuit according to the present invention. A variable resistance MOSFET linear device (20) is shown in which the gate electrode (G1) of the MOSFET (Q1) is connected to a voltage source (VI). the drain electrode (D1) thereof, which is an input, is connected to a voltage source (V2). The source electrode (S2) of the MOSFET (Q2) representing the other input is connected to the voltage source (-V2) and further connected to the Gate electrode (G2). The source electrode (S1) of the MOSFET (Q1) is connected to the drain electrode of the MOSFET (Q2) with the connection therebetween, ie Node (A), with an inverting input of an operational amplifier (U) of an amplifier unit (10) is connected. A non-inverting input of the operational amplifier (Ü) is connected to ground, and the output is connected to the inverting input through a feedback element (Z).

Referring to the drawing, the output voltage (Vo) obtained from both of the respective currents (II) and (12) flowing through the MOSFETs (Q1) and (Q2) and the feedback element (Z) are given a value. which is proportional to the product of the input voltages from the voltage sources (VI) (Vgs) and (V2) (Vds), respectively.

4 illustrates another embodiment of the present invention wherein a MOSFET (Q3) is connected between the variable resistance MOSFET linear device (20) and the inverting input of the operational amplifier (U) of the amplifier unit (10) to provide the neural state signal (Q). NZS) to the gate electrode (G3) as an input. According to the above-mentioned embodiment, when the input voltage of the voltage source (V2) of the MOSFET linear device (20) is set to a predetermined level and the input voltage of the voltage source (VI) functions as a synapse weight of a neural network, a new circuit for realizing the neural network can be provided Basic structure of the hybrid neural network, which stores the neuronal state using a feedback capacitor in electrical form.

Fig. 5 shows another embodiment of the present invention. Referring to Fig. 3, the MOSFETs (Q4) and (Q5) are connected between the voltage sources (V2) and (-V2) and the MOSFET linear device (20), the gate electrodes (G4), (G5) are connected together allowing the neural state signal (NZS) to be input as an input. Therefore, when no input signal is applied, the power consumption existing at the MOSFETs (Q1) and (Q2) can be eliminated. According to the second embodiment of the invention described above, a new neural network can be obtained for minimizing the power consumption required for high integrity of the system.

As described above, according to the present invention, a simple and accurate operation result can be achieved by taking advantage of the primary linear characteristics of the MOSFET. It is also possible to construct a new neural network of synapses, with which it is possible, although few MOSFETs are used, to achieve a fully asynchronous operation with high processing speed.