Microcomputer controlled data receiver

(42) Date of commencement of the patent: 15.11.1992 (45) Date of issue: 25. 8.1993

<td>(30) Priority:</td><td>(73) Patent owner:</td>

<td>12. 5. 1983 US 493919 claimed.</td><td>MOTOROLA, INC. 60196 SCHAUMBURG (US).</td>

<td>(56) Documents:</td><td>(72) Inventor:</td>

<td>US PS4369516</td><td>WILSON JAMES LESLIE SCHAUMBURG (US). EDWARDS SHANNON MARENGO (US).</td>

(54) DEVICE FOR RECEIVING A BLOCK OF BINARY OATEN BITS OF FIRST AND SECOND DATA SIGNALS

OQ

AT 396,315

MR 0070310

AT396 315B

The present invention relates to an apparatus for receiving a block of binary data bits of first and second data signals, which are generated by a signal source, wherein the first and second data signals have a binary zero state before and after the block of data bits, the first data signal has the binary zero state and the second data signal has the binary one state for data signal bits with the binary zero state, the first data signal has the binary one state and the second data signal has the binary zero state for data signal bits having the binary one state, and the first and second data signals have the binary one state between successive data signal bits.

In prior art data receivers, it is necessary to recover a clock signal from a self-clocking data bus before the data transmitted thereon can be received. For example, in the self-clocking data transmission system described in U.S. Patent 4,369,516, two data signals are used to transmit self-clocking data from a data transmitter to a data receiver. The data receivers include a circuit that derives a bit clock signal that clocks the data into a receiving register. However, the use of a separate circuit to receive self-clocking data in microcomputer-controlled data receivers is not desirable.

Therefore, it is an object of the present invention to provide an improved processor-controlled data receiver which receives self-clocking data with a minimum of non-constituent processor elements.

This object is achieved according to the invention in a device of the type mentioned by means for generating a data transition signal, that has the binary one state, if the first and second data signals have different binary states from each other, and has the binary zero state, when the first and second data signals have equal binary states; a device connected to the data transfer signal generator for generating an interrupt signal, that has the binary one state, when the data transition signal and an interrupt control signal have equal binary states, and otherwise has the binary zero state; and a processor connected to the interrupt signal generator for generating the interrupt control signal having an initial binary one state, wherein the processor is responsive to the binary one state of the interrupt signal, to save a data bit, if the interrupt control signal has binary one state, and further responsive to the binary one state of the interrupt signal, to change the binary state of the interrupt control signal.

A preferred embodiment of the present invention will be explained below with reference to the accompanying drawings.

Show it:

Figure 1 is a circuit diagram of a data processing circuit embodying the present invention.

Figure 2 is a general flow diagram of a computer program executed when the data processing circuit of Figure 1 is interrupted, and

Figures 3 to 9 are detailed flowcharts of the computer programs executed by the data processing circuit of Figure 1 in response to an interrupt.

Figure 1 is a circuit diagram of a data processing circuit embodying the present invention. A data processor or microcomputer (100) is connected to a three-wire data bus TDATA, CDATA and RDATA of the type described in the above-referenced US Pat. 4 369 516 is described. The three-wire data bus provides a self-timed, asynchronous data connection between a transmitting microcomputer (not shown) and a receiving microcomputer (100), which may be located at a common location or may be spaced apart. For example, in radiotelephone application cases, a microcomputer may be located in the handset of the radiotelephone control unit, while the other microcomputer may be housed in the rack (or in the radio). The use of a three-wire bus in radiotelephone application cases is particularly advantageous since it is highly desirable to reduce the number of wires between the handset and the handset (or radio).

The data is preferably transmitted in blocks on the TDATA and CDATA signal lines from the sending microcomputer to the receiving microcomputer (100). The receiving microcomputer (100) may transmit data back to the transmitting microcomputer on the RDATA signal line.

In the preferred embodiment, a data block consists of eight bits of an address followed by eight bits of data. A data block on the RDATA signal line consists of eight bits of data, and is transmitted in synchronization with the receipt of the data portion of the data block from the sending microcomputer. The address portion of the data block may be used by the receiving microcomputer (100) to determine which data on the RDATA signal line must be returned, or to determine at what location the data portion of the data block is stored or received by the receiving microcomputer (100 ) should be used.

For radiotelephone use cases or in radio applications, the transmitting microcomputer in the holding part or may be housed in the fork of the radiotelephone control unit while the receiving microcomputer (100) may be located in the handset of the radiotelephone control unit. A suitable radiotelephone control unit is used in conjunction with a suitable radiotelephone transmitter in the Motorola operating manual no. 68P81039E25 titled Advanced Mobile Phone System 800 MHz High

-2AT396 315B

Capacity Mobile Radiotelephone described. This manual was published by Technical Writing Services, Motorola, Inc. 1301E. Algonquin Road, Schaumburg, Illinois 1979, published The receiving microcomputer (100) in the handset sends information about the three-wire bus relating to which push-button has been operated and what data is being displayed. When the receiving microcomputer (100) detects that a pushbutton has been operated in the handset, a binary one is applied to the RDATA signal line to allow the sending microcomputer in the holding part or in the fork to announce that new information is available. The sending microcomputer in the holding part or in the fork then sends a data block to the receiving microcomputer (100) in the handset, which returns the new information on the RDATA signal line.

According to the present invention, the microcomputer (100) is interrupted in response to each bit of the data block transmitted on the TDATA and CDATA signal lines. The microcomputer (100) is interrupted in response to a downward signal transition, which signal is applied to its interrupt input. In Figure 1, the interrupt input of the microcomputer (100) is connected to the output of the exclusive-OR gate (102). The microcomputer may be any commercially available microcomputer, such as the Intel Type 8048 microcomputer or the Motorola Type MC6805 microcomputer. When the microcomputer (100) is interrupted, the program control is transferred to the interruption computer program stored therein.

Figure 2 shows a general flow chart of the computer program which is executed when the microcomputer (100) is interrupted. At block (203), the program control is transferred to the interruption location which, in the preferred embodiment, has the hexadecimal address 003. Next, at the block (265), the microcomputer (100) executes the computer program designated LUCU. In the preferred embodiment, the LUCU computer program includes a number of subroutines for receiving, between the sending microcomputer in the holding part and in the fork and the receiving microcomputer in the handset of a radiotelephone control unit transmitted data block. These programs also ensure the transfer of data from the receiving microcomputer back to the sending microcomputer via the RDATA signal line. Since an interrupt is generated for each data bit, these computer programs are also executed for each data bit. Upon completion of these computer programs, the control program of the microcomputer (100) returns at block (330) to the execution of other computer programs, such as computer programs, which scan the keypad for actuated pushbuttons and display the selected data.

Figs. 3 to 9 are flowcharts of the computer programs executed by the microcomputer (100) in response to an interruption. The flowcharts of Figs. 3 to 9 provide those skilled in the art with detailed procedural steps by which actual computer instructions for a given microcomputer can be readily made. By analogy with an electrical circuit diagram, the flow diagrams according to FIGS. 3 to 9 are equivalent to an electrical circuit in which the exact quantities or Values ​​of the electrical circuit elements correspond to the creation of actual computer instructions for the blocks in the flowchart.

Figure 3 shows a computer program designated LUCU which is executed by the microcomputer (100) during an interruption. The LUCU program is executed on interrupts generated at the beginning of data bits and at the beginning of an idle state between data bits. Beginning with block (265), program control proceeds to block (266) where the contents of accumulator ACC are saved at storage location HLDACC. When returning or returning from the interrupt computer program, the contents of the accumulator are stored again

At decision block (273), a check is made to see if TD has the binary O state. The variable TD is the TDATA signal while the variable CD is the CDATA signal. When TD has the binary 0 state, the YES branch is selected to the computer program CHK1 of Figure 5 to determine if a binary O is Data bit has been received or whether the end of a data block has been reached. Otherwise, the NO branch of decision block (273) is taken. At decision block (274), a check is made to see if CD has a binary 1 state. If CD has a binary low state, the YES branch is taken to the IDLE computer program of FIG the idle state between the data bits has been determined

If CD does not have a binary 1 state, the NO branch is selected by decision block (274) to block (276), where the bit counter BITCNT is incremented by 1 because a binary 1 data bit has been received. Next, at block (279), the bit counter in the working register SHFT is saved. The accumulator ACC is then loaded with a binary 1 at the block (280). The register SHFT is then decremented by 1 at block (281). Subsequently, at decision block (281A), a check is made to see if SHFT has a binary 0 state. If so, the YES branch is selected to jump to the SHFTDONE computer program in FIG. Otherwise, the NO branch is taken to the computer program LOOP 1 in FIG. After initially receiving a frame, the bit counter BITCNT is set to 0 and incremented by 1 each time a bit of the data block cs is received.

-3AT396 315B

In the following, reference is made to FIG. FIG. 4 shows the computer program with the designation LOOP 1 (loop 1). At block (283), the contents of accumulator ACC are shifted one bit to the left. Thereafter, at block (284), SHFT is decremented by one. Continuing at decision block (284A), a check is made to see if SHFT has a binary O state. If this is not the case, the NO branch is selected back to block (283), in which the accumulator ACC is again shifted to the left by one bit. When SHFT is equal to zero, the received data bit is shifted to its proper location in the incoming data block, and the YES branch from decision block (284) to block (285) is chosen, at which the accumulator ACC uses an OR function is linked to the received data word RX. This operation puts the new data bit in place in the received data word RX. Subsequently, the control program continues with the SHFTDONE designated computer program according to FIG.

FIG. 5 shows the computer program designated CHK 1. The computer program CHK 1 is reached from decision block (273) in Figure 3 when TD has a binary O state. At decision block (288), a decision is made to determine if CD has a binary O state. If so, the YES branch is selected to go to the RESET (Reset) computer program in FIG. The RESET computer program is executed at the end of a data block, i. H. if both TD and CD have a binary O state.

If CD has no binary O state, the NO branch is taken from decision block (288) to block (289) where the bit counter BITCNT is incremented by one since a binary O data bit has been received. Subsequently, at block (292), the bit counter BITCNT is loaded into the working register SHFT. Subsequently, SHFT is decremented by one at block (293). Thereafter, at decision block (293A), a decision is made to determine if SHFT has a binary O state. If so, the YES branch is selected at block (294), where the accumulator ACC is cleared and program control continues to the SHFTDONE designated computer program in FIGURE 6. The YES branch from decision block (293A) is taken for the first bit of a data block.

If SHFT has no binary O state, the NO branch is taken from decision block (293A) to block (297), where the accumulator ACC is shifted one bit to the left. Thereupon SHFT is decremented by one at block (298). Then, at decision block (298A), a check is made to see if SHFT is equal to zero. If not, the NO branch is returned, leading back to block (297), where accumulator ACC is one bit again pushed to the left. If SHFT is equal to zero, the YES branch is selected by decision block (298A) to block (299), where the accumulator ACC is ANDed with the received data word RX. Since the received data bit has a binary O state, ANDing the received data bit with the received data word RX places the binary O bit in the received data word in place. The program control then proceeds to the computer program designated SHFTDONE in FIG.

Figure 6 shows a detailed flow chart of the SHFTDONE program. The SHFTDON computer program is started after a data bit has been received and shifted to its proper location in the received data word RX. Continuing at block (305), the received data word RX is saved in the memory of the microcomputer. Thereafter, at block 306, the interrupt control signal P26 is set equal to zero to allow an interrupt to be generated by the idle state of the TDATA and RDATA signal lines. In accordance with an important feature of the present invention, no further interruption is generated until the idle condition is reached.

Subsequently, at block (307), the accumulator is loaded with the bit counter BITCNT. The bit counter is 8 when the first bits representing the address portion of the data block have been received. The bit counter is 16 when the following eight bits representing the data portion of the data block have been received. At the subsequent decision block (309), a check is made to see if the bit counter is equal to 5. If so, the YES branch is taken to block (317) where the accumulator ACC is loaded with the received data word RX. The first five bits of the address portion of the data word are decoded in advance to determine, if possible, that a particular portion of the data must be sent by the receiving microcomputer (100) to the RDATA signal line. At the subsequent decision block (319), a check is made to see if the first five bits of the data part contain a predetermined status address. If so, the YES branch is selected to the block (323) where the service request flag RFS flag 1 is cleared. Subsequently, at block (327), the code for an actuated pushbutton key is loaded into the transmission buffer TX for subsequent transmission on the RDATA signal line. Thereafter, at block 329, the temporary TX buffer is cleared, whereupon program control returns from the interrupt computer program.

If the first five bits of the data portion of the received data block do not contain the predetermined status address, the NO branch is selected by decision block (319) to block (320) where an empty data word is stored in the accumulator ACC. Then at block (321) the empty one

-4AT 396 315 B

Word is also stored in the transmission buffer TX, whereupon the program control returns from the interruption computer programs.

If at decision block (309) the bit counter is not equal to 5, the NO branch is taken to decision block (312) where a check is made to see if the bit count equals 8 if not , the NO branch is taken to return from the interrupt computer programs. Otherwise, the YES branch is taken to the block (313) in which the accumulator ACC is loaded with the received data word RX. Subsequently, at block (314), the accumulator ACC is loaded into the address buffer ADDRS. Since the bit counter is 8, the entire address portion of the data block has been received and can be stored in the address buffer ADDRS. Thereafter, at block (315), the buffer for the received data word RX is cleared in preparation for receiving the data portion of the data block. Thereafter, the program control loops back from the interruption computer programs to process any subsequent data bits of the data block.

Figure 7 is a flow chart of idle computer program IDLE entered from decision block (274) of Figure 3 when the idle state between the data bits has been detected. Thereafter, at block (370), the interrupt control signal P26 is set equal to 1 to enable the generation of an interrupt by a subsequent bit of the data block. Thereafter, according to the present invention, no further interruption is generated until the next data bit is reached.

In the subsequent block (371) the accumulator is loaded with the bit counter BITCNT. Then, at decision block (373), a check is made to determine if the bit counter is equal to one. If so, the YES branch is taken from the block (381) where the RDATAS signal line P27 is set equal to zero to terminate any outstanding service requests RFS. Thereafter, the program control returns from the interrupt programs. If the bit counter is not equal to 1, the NO branch is taken from decision block (373) to decision block (375) where a check is made to determine if the bit counter is greater than or equal to eight , If not, the NO branch is taken to return from the interrupt computer programs. Otherwise, the YES branch is taken to the LUCU computer program in Figure 9 to give one bit from the transmit buffer TX to the RDATA signal line.

Figure 8 shows a detailed flow chart of the reset computer program RESET entered from decision block (288) in Figure 5 after a data block has been received by the receiving microcomputer (100). At block (346) the accumulator is replaced with the received one Address ADDRS loaded. Thereafter, at block (347), the contents of the accumulator are stored in a permanent register for the received address ADDRS. At block 348, the accumulator is loaded with the received data word RX. Thereafter, at block (349), the contents of the accumulator are stored in the constantly received data word register RXDATA. In preparation for receiving a subsequent data block, the bit counter BITCNT, the received address ADDRS, the received data word RX, and the transmission buffer TX at the block (351 ) deleted. Thereafter, at block (352), the interrupt control signal P26 is set equal to one to allow the interrupts for the transmission of the next data block.

Finally, the service request flag RFS FLAG 1 is checked at decision block (356) to see if it has a binary one state. If so, the YES branch is taken to block (359) where the RDATA signal line is set to a binary one if another pushbutton has been pressed or the previous (service) request has not been fulfilled , If no further pushbutton has been actuated, the RDATA signal line is set to a binary zero state. The flag 0 is then set to a binary one to indicate that a frame has been received. Thereafter, the program control returns from the interruption computer programs. If the flag 1 is not equal to a binary one, the NO branch is selected by decision block (356) to block (357), where the RDATA signal line P27 is set equal to zero. Thereafter, at block (360), the flag 0 is set to a binary one state to indicate that a data block has been received.

Thereafter, the program control returns from the interruption computer programs. When another button is actuated, the microcomputer (100) will again set the RDATA signal line to a binary one state to request that the sending microcomputer send a block of data to ascertain which button has been pressed.

Figure 9 shows a detailed flow chart of the computer program designated CULU, which is executed by the decision block (375) in Figure 7 whenever the bit counter BITCNT is greater than or equal to eight. The bit counter is greater than or equal to eight when the data portion of the data block has been received. At block (250), the accumulator ACC is loaded with the contents of the transmit buffer TX in preparation for a bit to the RDATA signal line. Subsequently, at block (251), the least significant bit of the accumulator ACC is masked. Thereafter, at decision block (251A), a check is made to see if the masked bit equals a binary one. If so, the YES branch is selected to block (254), where the masked bit is functionally linked to P27 OR-5AT396 315B, that is, the output port of the RDATA signal line. Otherwise, the NO branch is selected to block (252), where the masked bit is ANDed to P27. Subsequently, the accumulator ACC is loaded at the block (255) with the contents of the transmission buffer TX. Thereupon, at block (256), the accumulator ACC is shifted to the right by one bit to transfer the next bit to the least significant bit of the Transmit Sybuffer. Subsequently, at block (257), the contents of the accumulator ACC are set back into the transmission buffer TX. Now the program control returns from the interruption computer programs. After all eight bits of the data portion of the data block have been received, program control proceeds to the RESET computer program of FIG. 8 to prepare for receipt of a subsequent data block.

Briefly described has been an improved microcomputer controlled data receiver which receives a block of self-clocking data bits from two data signal lines by interrupting the receiving microcomputer in response to each data bit. Since interrupts are generated by each bit, the rate of data transfer may change from bit to bit or may be interrupted for varying time intervals without adversely affecting data reception. In addition, the interrupts can still be used by the microcomputer controlled data receiver to synchronize the return data. The improved data receiver in accordance with the present invention may be used to advantage in any suitable microcomputer configuration for receiving self-clocking, asynchronous data with a minimum of external circuitry.

The following computer programs have been coded in the mnemonic language of an Intel type 8048 microcomputer based on the flowcharts of Figs. The reference numerals of the blocks of the flowcharts of Figs. 2 to 9 correspond to similarly numbered instructions of the computer programs. The computer programs are attached to this application to clarify that the operations in the blocks of the flowcharts will provide sufficient information for a skilled person to readily encode the microcomputer instructions for each block of the flowcharts. In subsequent computer programs, the first column represents the command number, while the second column is the label and the third column contains the command code followed by the comment after the semicolon; Registeizuordnung

<td>12</td><td>SHFT</td><td>EQU</td><td>RI</td><td>temporary location for the bit counter</td>

<td>14</td><td>BITCNT</td><td>EQU</td><td>R2</td><td>received bit counter</td>

<td>15</td><td>HLDACC</td><td>EQU</td><td>R3</td><td>temporary ACC memory</td>

<td>16</td><td>TX</td><td>EQU</td><td>R4</td><td>; data to be transferred</td>

<td>17</td><td>ADRES</td><td>EQU</td><td>R5</td><td>• Received address</td>

<td>18</td><td>RXDATA</td><td>EQU</td><td>R6</td><td>received data</td>

<td>19</td><td>RX</td><td>EQU</td><td>R7</td><td>; entering data received</td>

; Part of the 3-wire program-LU to CU

<td>250</td><td>CULU</td><td>MOV</td><td>A, TX</td><td>TX data in ACC</td>

<td>251</td><td></td><td>JBO</td><td>SET</td><td>; is bit 0 a 1 or a 0?</td>

<td>252</td><td></td><td>ANL</td><td>P2, # 7FH</td><td>Sets P27 to 0</td>

<td>253</td><td></td><td>JMP</td><td>outdone</td><td></td>

<td>254</td><td>SET</td><td>ORL</td><td>P2, # 80H</td><td>Sets P27 to 1</td>

<td>255</td><td>outdone</td><td>MOV</td><td>A, TX</td><td>; Load ACC with the word to be transferred</td>

<td>256</td><td></td><td>RR</td><td>A</td><td>; Shift TX 1 bit</td>

<td>257</td><td></td><td>MOV</td><td>TX, A</td><td>Save the Word</td>

<td>258</td><td>RETRNN</td><td>JMP</td><td>RETRN</td><td>; Return from the interruption</td>

<td>259</td><td>IDL</td><td>JMP</td><td>IDLE</td><td></td>

<td>260</td><td>REST</td><td>JMP</td><td>RESET</td><td></td>

<td colspan="4">; Part of the 3-wire program LU to CU</td><td></td>

<td>265</td><td>Lucu</td><td>SEL</td><td>RBO</td><td>; RAMBANK0</td>

<td>266</td><td></td><td>MOV</td><td>HLDACC, A</td><td>; save ACC</td>

<td>267</td><td></td><td>MOV</td><td>A, RI</td><td></td>

<td>268</td><td></td><td>MOV</td><td>RI, # STOREG</td><td></td>

<td>269</td><td></td><td>MOV</td><td>@ R1, A</td><td>R1 in the temporary memory</td>

-6AT396 315B

<td colspan="2">270</td><td>INC</td><td colspan="2">RI</td>

<td>271</td><td></td><td>MOV</td><td>A, R0</td><td></td>

<td>272</td><td></td><td>MOV</td><td>@ R1, A</td><td>R0 in the temporary memory</td>

<td>273</td><td></td><td>JNTO</td><td>CHK1</td><td>if T0 = 0, RX bit = 0 or; reset bit</td>

<td>274</td><td></td><td>JT1</td><td>IDL</td><td>; if T0 &amp; TI = 1, send idle bit check to LU</td>

<td>276</td><td></td><td>INC</td><td>BITCNT</td><td>lowered bit counter for RX data</td>

<td>278</td><td></td><td colspan="2">MOV A, BITCNT</td><td></td>

<td>279</td><td></td><td>MOV</td><td>SHFT, A</td><td>; save bit counters in SHFT</td>

<td>280</td><td></td><td colspan="2">MOV A, # 01H</td><td>T1 = 0, T0 = 1, bit = 1</td>

<td>281</td><td></td><td colspan="2">DJNZ SHFT, LOOP1</td><td></td>

<td>282</td><td></td><td>JMP</td><td>SHFTDONE</td><td></td>

<td>283</td><td>LOOP 1</td><td>RL</td><td>A</td><td>; push bit to the right place</td>

<td>284</td><td></td><td colspan="2">DJNZ SHFT, LOOP1</td><td></td>

<td>285</td><td></td><td>ORL</td><td>A, RX</td><td>save bit in RX</td>

<td>286</td><td></td><td>JMP</td><td>SHFTDONE</td><td></td>

<td>287</td><td>CHK1</td><td>JNT1</td><td>REST</td><td>if TI = 0, reset bit; if; T1 = 1, bit = 0</td>

<td>289</td><td></td><td>INC</td><td>BITCNT</td><td>Increased bit counter for RX data</td>

<td>291</td><td></td><td colspan="2">MOV A, BITCNT</td><td></td>

<td>292</td><td></td><td>MOV</td><td>SHFT, A</td><td>jrette bit counter to SHFT</td>

<td>293</td><td></td><td colspan="2">DJNZ SHFT, BITO</td><td></td>

<td>294</td><td></td><td>CLR</td><td>A</td><td>first bit of the RX word is 0</td>

<td>295</td><td></td><td>JMP</td><td>SHFTDONE</td><td></td>

<td>296</td><td>ΒΠΌ</td><td>MOV</td><td>, # OFEH</td><td></td>

<td>297</td><td>LOOP</td><td>RL</td><td>A</td><td>; push bit to the right place</td>

<td>298</td><td></td><td colspan="2">DJNZ SHFT, LOOP</td><td></td>

<td>299</td><td></td><td>ANL</td><td>A, RX</td><td>; save bit to RX</td>

; SHFTDONE stores the RX information and checks how many bits have been received

<td>305</td><td>SHFTDONE</td><td>MOV</td><td>RX, A</td><td>save RX word</td>

<td>306</td><td></td><td>ANL</td><td>P2, # 0BFH</td><td>; set P26 = 0, allow for idle bit interrupt</td>

<td>307</td><td></td><td>MOV</td><td>A, BITCNT</td><td></td>

<td>308</td><td></td><td>XRL</td><td>Α, # 05H</td><td>; Bit counter = 5?</td>

<td>309</td><td></td><td>JZ</td><td>STATCHK</td><td>if 0, check status address</td>

<td>310</td><td></td><td>MOV</td><td>A, BITCNT</td><td></td>

<td>311</td><td></td><td>XRL</td><td>Α, # 08H</td><td>BITCNT = 8?</td>

<td>312</td><td></td><td>JNZ</td><td>RETRN</td><td>if 0, save address</td>

<td>313</td><td></td><td>MOV</td><td>A, RX</td><td></td>

<td>314</td><td></td><td>MOV</td><td>R0, # ADDRS</td><td>; save the received address</td>

<td>315</td><td></td><td>MOV</td><td>@ RO, A</td><td></td>

<td>316</td><td></td><td>JMP</td><td>RETRN</td><td>Return from interruption</td>

<td>317</td><td>STATCHK</td><td>MOV</td><td>A, RX</td><td>; load ACC with RX address</td>

<td>318</td><td></td><td>XRL</td><td>A, # IAH</td><td>• comparisons with status address</td>

<td>319</td><td></td><td>JZ</td><td>STAT</td><td>if 0, status address</td>

<td>320</td><td></td><td>MOV</td><td>Α, # 80H</td><td>; load empty word into the TX buffer</td>

<td>321</td><td></td><td>MOV</td><td>TX, A</td><td></td>

<td>322</td><td></td><td>JMP</td><td>RETRN</td><td>; Return from interruption</td>

<td>323</td><td>STAT</td><td>CALL</td><td>LDFLG</td><td>; delete RFS-Hagge 1</td>

<td>324</td><td></td><td>ANL</td><td>A, # 0FDH</td><td rowspan="2">; delete RFS flag</td>

<td>325</td><td></td><td>MOV</td><td>@ RO, A</td>

<td>326</td><td></td><td>SEL</td><td>RB1</td><td>RAM Bank 1</td>

<td>327</td><td></td><td>MOV</td><td>Α, TXTMP</td><td>; put key code in the TX buffer</td>

<td>328</td><td></td><td>SEL</td><td>RB0</td><td>; RAM Bank 0</td>

<td>329</td><td></td><td>MOV</td><td>TX, A</td><td></td>

<td>330</td><td>RETRN</td><td colspan="2">MOV RI, # STOREG + 1</td><td>; RETRN again invites RI, RO in front of the</td>

Return from the interruption

-7AT396 315B

<td>332</td><td></td><td>MOV</td><td>A, R1 @</td><td></td>

<td>333</td><td></td><td>MOV</td><td>RO, A</td><td>; store RO again</td>

<td>334</td><td></td><td>DEC</td><td>RI</td><td></td>

<td>335</td><td></td><td>MOV</td><td>A, R1 @</td><td></td>

<td>336</td><td></td><td>MOV</td><td>RI, A</td><td>In turn, save RI</td>

<td>337</td><td></td><td>MOV</td><td>A, HLDACC</td><td>save ACC</td>

<td>338</td><td></td><td>RETR</td><td></td><td>Return from the interruption</td>

<td colspan="4">; The program RESET resets the conditions</td><td>if the transmission from LU to CU</td>

<td colspan="5">It also sets a flag indicating that the RX data is received and saves it</td>

<td colspan="5">received address and received data to ADRES and RXDATA.</td>

<td>345</td><td>RESET</td><td>MOV</td><td>RO, # address</td><td>; RX address and data received</td>

<td>346</td><td></td><td>MOV</td><td>A, @ R0</td><td></td>

<td>347</td><td></td><td>MOV</td><td>Adres, A</td><td>; save RX address</td>

<td>348</td><td></td><td>MOV</td><td>A, RX</td><td></td>

<td>349</td><td></td><td>MOV</td><td>RXDATA, A</td><td>save RX data</td>

<td>350</td><td></td><td>CLR</td><td>A</td><td></td>

<td>351</td><td></td><td>MOV</td><td>BITCNT.A</td><td>; delete BITCNT</td>

<td>352</td><td></td><td>MOV</td><td>RX, A</td><td>; delete RX</td>

<td>353</td><td></td><td>ORL</td><td>P2, # 40H</td><td>; set P26 = 1 to set the interrupt for the</td>

<td></td><td></td><td></td><td></td><td>RX data on the next transmission too</td>

<td></td><td></td><td></td><td></td><td>enable</td>

<td>355</td><td></td><td>CALL</td><td>LDFLG</td><td></td>

<td>356</td><td></td><td>J B1</td><td>SETRFS</td><td>; is RFS flag set?</td>

<td>357</td><td></td><td>ANL</td><td>P2, # 7FH</td><td></td>

<td>358</td><td></td><td>JMP</td><td>SETFLG</td><td></td>

<td>359</td><td>SETRFS</td><td>ORL</td><td>P2, # 80H</td><td>; Send RFS back</td>

<td>360</td><td>SETFLG</td><td>MOV</td><td>RO, # stack + 1</td><td>; STACK address with PSW (flag 0)</td>

<td>361</td><td></td><td>MOV</td><td>A, @ RO</td><td>jlade PSW in ACC</td>

<td>362</td><td></td><td>ORL</td><td>Α, # 20H</td><td>; set flag 0 = 1, data is received</td>

<td>363</td><td></td><td>MOV</td><td>@ RO, A</td><td>jrette to STACK</td>

<td>364</td><td></td><td>JMP</td><td>RETRN</td><td>^ Return from interruption</td>

; The program IDLE checks whether the data should be sent to LU. This happens at the beginning of IDLE (negative edge of the RX clock).

<td>370</td><td>IDLE</td><td>ORL</td><td>P2, # 40H</td><td>; set P26 = 1 to allow interruption for RX data</td>

<td>371</td><td></td><td>MOV</td><td>A, BITCNT</td><td></td>

<td>372</td><td></td><td>DEC</td><td>A</td><td></td>

<td>373</td><td></td><td>JZ</td><td>ENFRS</td><td></td>

<td>374</td><td></td><td>MOV</td><td>A, BITCNT</td><td></td>

<td>375</td><td></td><td>ANL</td><td>A, # 0F8H</td><td>; is BITCNT greater or = 8?</td>

<td>376</td><td></td><td>JNZ</td><td>CULUP</td><td>not 0; greater or = 8 output data after LU</td>

<td>378</td><td></td><td>JMP</td><td>RETRN</td><td>; Return from interruption</td>

<td>379</td><td rowspan="2">Pagei</td><td>MOVP</td><td>A, @ A</td><td>Part of the 8048 self-test</td>

<td>380</td><td>RET</td><td></td><td></td>

<td>381</td><td>ENFRS</td><td>ANL</td><td>P2, # 7FH</td><td>jsende LO after LU termination of the service request</td>

<td>382</td><td></td><td>JMP</td><td>RETRN</td><td></td>

-8AT 396 315 B