Memory access control apparatus

(42) Date of commencement of the patent: 15. 6.1989 (45) Date of issue: 25. 1.1990

<td>(30) Priority:</td><td>(73) Patent owner:</td>

<td>7. 7.1981 JP 106127/81.</td><td>SONY CORPORATION</td>

<td>(56) Documents: W0-A1-80 / 02755 U.S. Patent 4,104,624 U.S. Patent 4,141,933</td><td>TOKYO (JP).</td>

(54) MEMORY ACCESS CONTROL DEVICE cn

AT 389 773

WR 0079318

No. 389773

The invention relates to a microcomputer, and more particularly to means for controlling access to the memory which allows a central processing unit and the control for a CRT to temporarily (time-nested) access to a memory (in time-sharing).

In microcomputer systems, the output is often visualized by means of a cathode ray tube (CRT). The data to be displayed can be stored in a video RAM with direct access (VideoRAM), to which a control circuit for the cathode ray tube (CRT) controller has direct access (direct memory access operation, DMA operation).

The central processing unit (CPU) supplies the data to the video RAM for display. The cathode ray tube may flicker when the central processing unit CPU polls the video RAM at the same time as the CRT controller is seeking access to the video RAM in a DMA operation.

The aforementioned hacking on the screen of the cathode ray tube is undesirable and distracts from the operation of the microcomputer system.

Various methods have been proposed to avoid flickering on the screen. In one of these methods, the CPU had access to the video RAM during the return of the cathode ray if the image merge control had no access to the video RAM. In another known method, the kinescope controller and the central processing unit were allowed access to the video RAM in a time-sharing manner. A third method suggested letting the display on the picture tube last longer (cycle-steal).

However, these proposed methods were not entirely satisfactory for avoiding the image flare of the display tube. Thus, in the first method, the work of the CPU had to be interrupted to allow it access to the video RAM during the return of the cathode ray. If the CPU and the CR controller had timed access to video RAM, then high-speed RAM was essential. For example, if the system clock is 4 MHz, then the video RAM must have an access time of about 50 nsec. The cycle stealing method can be easily performed with a CPU having a synchronized bus, such as the 6800 type, in which the machine cycle is controlled by a single clock generator. However, it is quite difficult to perform such a cycle-steal operation when the CPU has a non-synchronized bus, such as Ziloglnc models 8080 or Z80A.

It is therefore an object of the present invention to provide a new memory access controller for use in microcomputer systems.

It is another object of the invention to provide a memory access controller in which a CRT circuit and a central processing unit have access to a random access memory, optionally in a time shared manner.

However, it is also an object of the invention to provide a memory access controller which allows a central processing unit connected to a non-synchronized bus and a kinescope controller to selectively access a random access memory.

According to an essential feature of the invention, the memory access control device is characterized in that the addressable memory devices are connected to one another via the address busbars, the upper 8-bit addresses of the addressable memory devices being connected to the lower 8-bit addresses of the 16-bit address bus lines, and the lower 8-bit addresses of the addressable memory devices are connected to the upper 8-bit addresses of the 16-bit address buses, and wherein the addressable memory devices correspond to the input / output interface addresses of the central processing device by receiving the input / output interface address. Output request signal associated with the memory access controller.

The above and other features, features and advantages of the present invention will become more apparent from the following description, which refers to a basic embodiment in conjunction with the drawings

Hiebei is Fig. 1 the block diagram of a microcomputer for use with the present invention; FIG. 2 Fig. 10 is a block diagram of a memory access controller according to an embodiment of the present invention; FIG. 3 FIG. 12 is a more detailed block diagram of a portion of the memory access controller of FIG. 2; FIG. 4A and 4B are timing charts showing the timing of a central processing unit having access to an input / output device according to the present invention; FIG. Fig. 5A is a simplified diagram for explaining the memory access assignment of a random access memory and a read only memory; the Fig. 5B and 5C are simplified diagrams for explaining the memory access assignment of a video random access memory in use in accordance with the present invention; FIG. 6 FIG. 5 is a simplified diagram illustrating the reproduction of an image on the screen of a CRT based on data stored in the video random access memory of FIGS. 5B and 5C are stored; FIG. 7 FIG. 4 is a simplified diagram for explaining in which type four bit data a location in the video random access memory shown in FIGS. 5B and 5C are assigned; the Fig. FIGS. 8A to 8L are timing charts for explaining the time interleaving operation of the central processing unit and the picture tube storage upon access to the video random access memory shown in FIGS. 5B and 5C; the Fig. 9A and 9B are timing charts for illustrating how the central processing unit with the video 2Nr. 389773

5B and 5C come to interrogate the data stored therein, and Figs. 10A and 10B are timing diagrams for explaining how the central processing unit obtains access to the video random access memory shown in Figs. 5B and 5C to write data in these.

As the Fig. 1, a microcomputer includes a central processing unit (CPU) (1) connected to a non-synchronized data bus and, for example, a Z 80A unit manufactured by Zilog Inc., and a clock frequency of 4 MHz. In the following, any reference to the CPU (1) will be directed to such a Z 80A CPU, which should be provided here for the purpose of illustration only. The microcomputer is further provided with a read-only memory (ROM) (2), which has a monitor program and a BASIC translator program incorporated and which - for example - 64 K 8-bit address spaces from OOOOH to FFFFH has, as shown in FIG. Furthermore, the microcomputer includes a random access memory (RAM) in which a user program can be written and which also serves as a work area for the CPU (1). It should be emphasized that the above-mentioned number of 8-bit address spaces is given by way of example only and that the invention is not limited to the embodiments given here. An 8-bit data bus (4), a lower 8-bit address bus (5L) and an upper 8-bit address bus (5H) are connected to the associated data terminals (Dg to Dy), to address terminals (Αθ to Ay ) or. to address terminals (Αθ to Ajj) of the CPU (1), the ROM (2) and the RAM (3) for transmitting information. Upper 8-bit addresses from (Αθ to Ajg) are supplied to the B register of the CPU (1), and lower 8-bit addresses from (Αθ to Ay) are supplied to the C register of the CPU (1). Data in the A register of the CPU (1) can be directly supplied to an input / output (I / O) address.

For controlling the reading of information from ROM (2) and RAM (3), CPU (1) provides a memory request signal (MREQ) and / or or a read signal (RD) to the associated inputs of a system controller (6) to derive a memory read-out signal (MEMR) which is supplied to the read terminal (R) of both the ROM (2) and the RAM (3). Similarly, in order to perform a write operation with respect to the RAM (3), a write signal (WR) is generated by the CPU (1), and the write signal (WR) and / or or the aforementioned memory request signal (MREQ) is supplied to the respective inputs of the system controller (6) to derive a memory write signal (MEMW) supplied to the write terminal (W) of the RAM (3).

An input / output (I / O) interface (7) (port) is connected to a keyboard (8). The data terminals (ϋθ to Dy) are connected to the data bus (4), and the address terminals (Αθ to Ay) are connected to the address bus (5L). In order to control the reading of information from the I / O interface (7), the CPU (1) provides an I / O interrogation signal (IORQ) and / or or a read signal (RD) to the system controller (6) to derive an I / O read signal (IOR) applied to the read terminal (R) of the I / O interface (7). Likewise, in order to perform a write operation with respect to the I / O interface (7), the CPU (1) supplies a write signal (WR) and / or or the I / O interrogation signal (IORQ) to the system controller (6) to derive an I / O write signal (IOW) supplied to the write port (W) of the I / O interface (7). The I / O interface (7) may have an address of, for example, (30H) to (FFH).

A video RAM (10) is provided to make the output of the CPU (1) visible. A video display controller (20) communicates with the video RAM (10) to visualize the data on a CRT (9). The video RAM (10) has assigned to it the addresses of 12 KB, which range from OOOOH to 2FFFH, as shown in FIG. 5B is shown. In the embodiment according to FIG. 1 a Z 80A CPU is used and this embodiment according to FIG. 1 can of the training types according to FIGS. 2 deviate to 10. In the presence of the Z80A CPU, the lower 8-bit address terminals (Αθ to Ay) of the video RAM (10) are connected to the upper 8-bit address bus (5H), while the upper 8-bit address terminals (Αθ to A_ls) of the video RAM (10) are in communication with the lower 8-bit address bus (5L). I / O read signals (IOR) and I / O write signals (IOW) coming from the system controller (6) are also supplied to the read terminal (R) and the write terminal (W) of the video RAM (10), as well as the I / O interface (7). The data terminals (ϋθ to Dy) of the video RAM (10) are connected to the data bus (4). The video display controller (20) sequentially reads the data stored in the video RAM (10) and displays it on the CRT (9).

ROM (2) and RAM (3) are assigned to the memory addresses of the CPU (1), while the video RAM (10) and the I / O interface (7) are assigned to the I / O interface addresses of the CPU (1). These address assignments are illustrated in FIGS. 5A and 5B. Concerning ROM (2), RAM (3) and I / O interface (7), all instructions coming from the CPU (1) can be performed from the A register. The data stored in the video RAM (10) is accessible to the (BC) registers of the CPU (1).

The video RAM (10) and the video display control device (20) will be hereinafter referred to

-3Nr. 389773 to FIGS. 5B and 5C. Referring to Fig. 5C, the video RAM (10) is constructed of three own RAMs, i. between a video RAM for graphical representations (Q-RAM), a letter-video RAM (C-RAM), and a programmable letter (character) generator video RAM (PCG-RAM). The addresses from OOOOH to 1FFFH are the Q-RAM, the addresses from 2OOOH to 27FFH are the C-RAM, and the addresses from 28OOH to 2FFFH are assigned to the PCQ-RAM.

As can be seen from FIG. 6 As can be seen, the Q-RAM is capable of rendering a graphical representation (level) comprising 100 rows and 160 columns of data, and the C-RÄM can provide a letter (character) representation (level) comprising 15 rows and 80 columns The two levels of the Q-RAM and the C-RAM can be superposed on each other to form a representation on the screen of the CRT (9). In the illustrated embodiment, the character of the first address of the Q-RAM (OH address) and the character of the first address of the C-RAM (2OOOH address) are superposed in the upper left corner of the screen (9S).

Referring to Fig. 9, one byte in Q-RAM represents two dots, with four bits associated with each of these points. One of these four bits corresponds to the color red (R), one corresponds to the color green (G), another corresponds to the color blue (B) and one corresponds to the luminance (L) of the dots. Each point can therefore have one of eight colors and each color can be light or dark.

In C-RAM, one byte corresponds to one code for a character; in PCQ RAM, one byte equals 256 patterns.

With the aid of FIGS. 2 and 3, the meaning of the signals used in the described embodiment is explained below:

(0): A clock pulse which has a frequency of 4 MHz in the illustrated embodiment. A signal (0) which is the inverted (0) is the clock for the CPU (1).

(0/2): a clock pulse at half the frequency of the clock pulse (fl), which is synchronized with the latter; in the embodiment shown, (575) is equal to 2 MHz.

(20): A clock pulse with twice the frequency of the clock pulse (5), and synchronized with this. In the embodiment, (20) is equal to 8 MHz.

(S / L): A signal for controlling a shift register in which shifting is performed when the register is in the H state and loading in the L state.

(OIH): A signal for controlling the input and / or output state of a data terminal of a RAM.

(ÜRÄT): A signal for decoding the address of the G-RAM using the address signals (Αθ to A ^ g).

(CRM): A signal for decoding the address of the C-RAM using the address signals (Αθ to Ajj).

(PCS): A signal for decoding the address of the PCG RAM using the address signals (Αθ to A_lg). _ (GRMS): A signal obtained from the signal (GRM) by filtering (windowing) the signals (0/2) and (0) and selecting the data bus driver of the G-RAM in the state L.

_ (CRMS): a signal derived from the signal (CRM) by filtering (windowing) from the signals (5) and (0/2) and selecting the data bus driver of the C-RAM in the state L.

_ (PCGS): A signal obtained from the signal (PCG) by filtering (windowing) the signals (5) and (0/2) and selecting the data bus driver of the PCG-RAM in the state L, (GRMWR ): A write pulse for the G-RAM.

(CRMWR): A write pulse for the C-RAM.

(PCGWR): A write pulse from the PCG RAM.

(VRMRD): A read signal supplied to a pair of flip-flops having the state L when CPU (1) extracts data from the video RAM.

(DIR): A signal for controlling the transmission direction of the data bus.

2, a G-RAM (11), a C-RAM (12) and a PCG RAM (13) are shown, each having an enable-terminal (θέ) and a write-control terminal (FIG. WE) and which are included in a video RAM. If the output control terminals (OE) are high, then data can be read out from RAM (11), (12) and (13). If the write control terminals (WE) are in the L state, then data can be written to the RAM (11), (12), (13). _

A system clock generator (21) generates the clock signals (5), (072), (20), the shift register control signal (S / L), and signals (CLK) and (SCLK), the latter of which will be explained later in more detail , The clock signal (0) is inverted in an inverter (1a) and supplied to the CPU (1).

Clock signals (0), (572), and (20) from a system clock generator (31) are supplied to a time interleave bus multiplex controller (22). System control signals (IORQ), (WR) and (RD) from the CPU (1) are also supplied to the controller (22) as signals (GRM), (CRM) and (PCG). The device (22) generates as output signals (VRMRD), (DIR), (GRMWR), (OIH), (CRMWR), (PCGWR), (CRM§), (GRMS) and (PCgS). The circuits to which these signals are supplied will be described in more detail below.

A CPU interface data bus driver (23) is connected to the data terminals (ϋθ to D?) Of the CPU (1)

-4Nr. 389773 connected via the data bus (4). The driver (23) includes a pair of D flip-flop circuits (23W) and (23R). In a preferred embodiment, the flip-flop circuits (23W) and (23R) are 8-bit flip-flops. The flip-flop circuits (23 W) and (23 R) operate as a read output and as a write input for G-RAM (11), C-RAM (12) and PCG-RAM (13). The write input (23W) latches data coming from the data bus (4) of the CPU (1) to the falling edge of the signal (DIR) and supplies it to the video RAM (10) when the signal (DIR ) has the value L, as shown in FIG. 10A is shown. The read input (23R) latches data coming from the video RAM 10 to the falling edge of the clock signal (0/2) and supplies the data to the data bus (4) when the signal (VRMRD) is Lute.

The data bus drivers (31, 32 and 33) are connected to G-RAM (11), C-RAM (12) and PCG-RAM (13) via the data buses (Pj, P₄ or. Pg) connected. The drivers (31, 32 and 33) are also connected to the CPU interface data bus driver (23) to bring data to the RAM (11), (12) and (13) and to lose weight. The driver (31) has a port (G) connected to the port (GRMS) of the multiplex controller (22). The driver (32) has a port (G) connected to the port (CRMS) of the multiplex controller (22). Likewise, the data bus driver (33) has a port (G) in communication with the port (PCGS) of the multiplex controller (22). The data bus drivers (31, 32, 33) operate as gates for the read and / or write when CPU (1) accesses the RAM (11), (12) and (13) via the data buses (Pj to Pg) , The controller (22) provides a signal (DIR) to the terminals (DIR) of the drivers (31, 32 and 33) to indicate the direction of the data flow thereafter.

A CRT (cathode ray tube) control circuit (34) is supplied with clock signals (0/2) from the system clock generator (21). The control circuit 34 has access to the RAMs 11, 12 and 13 through a direct memory access (DMA) operation so that the data stored therein can be displayed on the cathode ray tube (CRT) 9. The control circuit (34) generates address signals for accessing the RAM (11), (12) and (13) for this display operation.

Multiplexers (41, 42 and 43) are connected to the terminals (AB) of the RAM (11), (12) and (13) via the data bus lines (Pj, P₂ and P₃) connected. These multiplexers (41, 42 and 43) have inputs (C) connected to the address terminals (Αθ to Ajg) of the CPU (1) via the data buses (5L) and (5H). Furthermore, the terminals (D) of the multiplexers (41, 42 and 43) are in communication with the kinescope control circuit (34). These multiplexers (41, 42, 43) alternately supply addresses from the kinescope control circuit (34) and from the CPU (1) so that the control circuit (34) and the CPU (1) have access to the RAM (11), (12). and (13) the video RAM (10) in a time-shared manner. The multiplexers (41, 42 and 43) are supplied with the clock signal (0/2) from the system clock generator (21) as a timing signal. In a preferred embodiment, the multiplexers (41, 42 and 43) allow the kinescope control circuit (34) to gain access to the RAM (11), (12) and (13) when the clock signal (0/2) is set to L value is, and that the CPU (1) access to the RAM (11), (12) and (13) receives when the clock signal (0/2) has the value H.

As the Fig. 6 shows, between the associated address locations in the G-RAM (11) and in the C-RAM (12) a distance of 2OOOH exists. When the signal (VDA) is applied from the CRT control circuit (34) to the multiplexers (41, 42), the value of the signal is shifted by 2OOOH to match the pitch in the C-RAM (12). Accordingly, access to the G-RAM (11) and to the C-RAM (12) is given at the same time as the CRT control circuit (34) provides a single access address (VDA). In the following description as well as in FIG. 8th the CRT control circuit (34) supplies an address (M) for the signal (VDA).

The flip-flop circuits (51 and 52) are connected via the data bus lines (P₃ or P₄) to the G-RAM (11) and to the C-RAM (12). In a preferred embodiment, the flip-flops (51 and 52) are 8-bit flip-flops. The flip-flop circuit (52) latches data from the C-RAM (12) and uses this latched data as an address for the PCG RAM (13) to obtain therefrom a pattern corresponding to the data. Because the flip-flop (52) provides a delay in the data provided by the C-RAM (12), the flip-flop circuit (51) also provides a delay for the data coming from the G-RAM (11), so that this data is for display arrive at the same time as the data from the C-RAM (12).

The flip-flop (51) is connected to a shift register (61) with parallel input and parallel output; this shift register distributes one byte of graphic data (see FIG. 6) in two four-bit dots. A shift register (62) having a parallel input and a serial output is connected to the PCG RAM (13) and the data bus driver (33) via the bus (Pg) and converts the image signal of a one-byte character into a font signal , In a preferred embodiment, the shift registers (61 and 62) are 8-bit registers. The outputs of the shift registers (61, 62) are supplied to a multiplexer (63) to extract the graphic signal from the shift register (61) with the character signal from the shift register (62).

-5Nr. 389773 together. The multiplexer (63) outputs a three-color signal in which the graphic planes of FIG. 6 are combined and displayed by the CRT (9)

The shift registers (61 and 62) are supplied with shift register signals (S / L) from the system clock (21). The signal (CLK) from the system clock (21) is supplied to the flip-flops (51, 52) and the shift register (62). The signal from the system clock (21) (SCLK) goes to the shift register (61).

Referring to FIG. 3, the multiplexer (43), generally shown in FIG. 2, includes three individual multiplexers (431, 432, 433). The addresses (Ag to Ajj) from the address bus (5H) are supplied to the input terminals (1A to 4A) of the multiplexer (431). The address bits (Aj₂ to Ajg) come to the inputs (1A to 4A) of the multiplexer (432). The address hits (Αθ to A₂) go to the inputs (1A to 3A) of the multiplexer (433). From the C-RAM (12) coming data bits (ϋθ to Dy) and the DMA address (VDA) go via the flip-flop (52) in zeitgeschachtelter way to the inputs of the multiplexer (431, 432, 433). Data bits (Dq) are fed to the input (4B) of the multiplexer (431); Data bits (Dj to D₄) get to the terminals (1B) to (4B) of the multiplexer (432). Data bits (Dg to Dy) are applied to the terminals (1B) to (3B) of the multiplexer (433). The DMA address (VDA) includes raster addresses (RAq to RA₂) and arrives at the inputs (1B) to (3B) of the multiplexer (431). The clock signal (0/2) arrives at the inputs (S) of the multiplexers (431, 432, 433).

The address bits (Αθ to A₃) are supplied from the outputs (1Y to 4Y) of the multiplexer (431) to the inputs (Αθ to Ag) of the PCG RAM (13). The address bits (A ^ to Αγ) are applied from the outputs (1Y to 4Y) of the multiplexer (432) to the inputs (A ^ to Αγ) of the PCG RAM (13). The address bits (Ag to Α ^ θ) go from the outputs (1Y to 3Y) of the multiplexer (433) to the inputs (Ag to Α- ^ θ) of the PCG RAM (13).

The time interleave bus multiplexer control circuit (22), on the right side of FIG. 3 has inputs for the signals (0), (072), (20), (iORQ), (RD), (WR), (GRM), (CRM) as well as (PCG). The input signals (RD) and (IORQ) are applied to a NOR gate (100) whose output goes to the NAND gate (214). The output of a NAND gate (102), whose input is the signals (PCG), (CRM) and (GRM), comes to the NAND gate (214). The output of the NAND gate (214) is connected to the terminal (G) of the flip-flop (23R).

The signals (WR) and (IORQ) are applied as input to a NOR gate (101), which provides an output signal to the input (D) of the flip-flop (222). The clock signal (0) is inverted and applied to the clock input of the flip-flop (222). The outputs (DIR) and (DIR) from the flip-flop (222) go to the flip-flop (23W) and driver (33), respectively, and control the direction of data flow in the read and write operations with respect to the PCG RAM (13). _

A D flip-flop (221) is supplied at its input (CL), the output of a NAND gate (103), at whose inputs the signals (0/2), (0) and (20) are located. The NAND gate (104) has as inputs (0/2), (0) and (20) and gives its output to the terminal (PR) of the flip-flop (221). The output of the flip-flop (221) controls the signals which are applied to the drivers (31, 32 and 33).

A NAND gate (105) has at its inputs the signal (0) and an output signal from the terminal (Q) of the flip-flop (221). The output of the NAND gate 105 is input to the NAND gates 106, 107 and 108. A NOR gate (109) has the inputs (0/2) and (PCG) and its output is at the NAND gate (106) and the NAND gate (110). A NOR gate (111) has as inputs the signals (0/2) and (CRM) and provides an output to the NAND gate (107) and to the NAND gate (112). A NOR gate (113) has (0/2) and (GRM) as inputs; its output is at the NAND gates (108) and (114). A signal from the output (Q) of the flip-flop (221) is applied to the inputs of the NAND gates (110), (112) and (114). The NAND gate (106) outputs an output signal (PCGS) to the G terminal of the data bus driver (33). The NAND gate (107) provides the output signal (CRMS); the NAND gate (108) provides the output signal (GRMS). The NAND gate (HO) brings its output signal (PCGWR) to the input (WE) of the PCG RAM (13). The NAND gate (112) provides an output signal (CRMWR). The NAND gate (114) provides the output signal (GRMWR).

Referring to Figure 4A, the Z80A CPU of the embodiment described herein by way of example has six machine cycles (Mj through Mg) for performing a read or write command. The machines use three to six clock pulse periods (Tj to Tg) of the CPU (1). Fig. 4A illustrates the machine cycle (M₂), which covers the periods (Tj to T₃), as indicated by the I / O address on the address headers (Αθ to Aj₅). The CPU (1) checks a signal (WAIT) during (T₂), and if this is LOW, the machine remains in (T₂). (T_w) indicates (T₂) repeatedly by signal (WAIT). As shown in Fig. 4B, the signal (0/2) has half the frequency of the signal (0) and is to this

-6Nr. 389773 synchronous.

Fig. 8 is a timing chart for explaining the operation of an embodiment of the present invention. Fig. 8A shows the clock pulse (0/2) which is zero (LOW) during the period (T_c) and one (high) during the period (T_d). During the period (T._£), the CPU (1) has access to the video RAM (10) during the period (T_d), the CRT control circuit (34) has access to the video RAM (10) in a direct access (DMA) operation.

Fig. 8B shows that the DMA address (Mj.j) during the periods (T_c) and (T._d) is produced. In the following periods (T_c and T._d), the next address (M ·) of the signal (VDA) is generated.

If FIGS. 8B, 8C and 8D are considered together, it follows that the CPU (1) during the period (T_c) the manifolds (Pp P₂, P3 and P₄), as indicated in the said figures by the dotted areas. During the period (Tj), when the CRT control circuit (34) has access to the video RAM (10), the collective lines (Pj to P₄) the address (Mj_j) as shown in Fig. 8B. In the next, subsequent period (T._c), the CPU (1) occupies the bus lines (Pj to P₄) while the CRT control circuit (34) in the period (T_d) the manifolds (Pj to P₄) with the address (Mj) claimed.

While with (T_c), the signal (0/2) is L and the address buses (5A and 5L) are connected through the multiplexer (41) to the address terminal (AB) of the G-RAM (11), as well as via the multiplexer (42) the address terminal (AB) of the C-RAM (12), as shown in FIG. 8C and in FIG. 2 can be seen. According to FIG. 8D, the data bus (4) is connected to the readout and write-in interfaces (23W) and (23R), via the driver (31) to the data terminal (DB) of the G-RAM (11) and via the driver (32) to the Data connection (DB) of the G-RAM (12). Accordingly, during the period (T_d) Data with address (Mj_j) is read out from the G-RAM (11) and from the C-RAM (12) by a DMA process.

As shown in Fig. 8E, the clock signal (CIK) at the end of each period (T_d) Zu, at which time the data is latched to the flip-flop circuits (51 and 52) of the G-RAM (11) and the C-RAM (12), respectively.

Referring to Figs. 8F, 8G and 8H, the flip-flop circuits (51 and 52) and the data buses (P5 and Pg) contain the data address (Mj ").₂) during the periods (T_c) and (T._d) which is delayed by one clock pulse after the data address (Mj_j) on the bus lines (Pj to P₄).

The data from the flip-flop circuit (51) is supplied to the shift register (61), and as shown in Fig. 81, a shift / load signal (S / L) is supplied to the shift register (61). When the shift / load signal (S / L) is at L, data is input to the shift register (61) (the shift / load signal (S / L) goes low when the period (T_d) into the period (T._cgoes over). When the shift register (61) is applied with a shift pulse (SCLK) as shown in Figs. 8J and 8K, the register (21) generates the three color signals (R, G and B) and the luminance signal (L). which the upper 4-bits of the during the period (T_cMake locked data. (The shift pulse (SCLK) occurs at the beginning of each of the periods (T_c) and (T._d) as shown in Fig. 83). During the period (T._d) the shift register (61) generates the three color signals (R, G and B) and a luminance signal (L), thus producing the lower 4-bits of the same data as described above. The signals (R, G, B and L) are fed to the multiplexer (63) for display on the CRT (9).

During the period (T._d), data from the flip-flop circuit (52) and signals (RAq to RA₂) constituting parts of the DMA address signal (VDA) are supplied through the multiplexer (43) to the address terminal (AB) of the PCG RAM (13), the data being read out and supplied to the shift register (62). The shift / load signal (S / L) and the clock signal (CLK) are supplied to the shift register (62), from which the data are serially read out, as shown in FIG. 8L is shown. The data read out in series comes, as already described, to the multiplexer (63). As a result, the multiplexer (63) on the CRT (9) generates three color signals by mixing the graphic plane with the character plane of FIG. 6th

Figs. 9A and 9B are timing charts illustrating the operation of the CPU (1) in reading out data from the PCG RAM (13). In Fig. 9A, the period (Tj) having the period (T_d) is synchronized when the clock signal (0/2) is H and the CRT control circuit (34) has access to the PCG RAM (13). At the beginning of the period (T._w), the CPU (1) reads data from the PCG RAM (13). During the period (T.₂) read data to the data bus driver (23R) in the following period (T_w) as indicated by the arrow in Fig. 9A between the lines drawn with (Pg) and (23R).

Referring to Fig. 9B, the machine state is Tj = T_d in Tj = T_c passed. In the periods (Tj and T3), the signal (0/2) is low, indicating that the CPU (1) is the collector (Pg) for accessing the

-7Nr. 389773

PCG RAM (13) claimed.

Figs. 10A and 10B illustrate the timing when the CPU (1) writes data into the PCG RAM (13). In Fig. 10A, the period (Tj) is in synchronism with the period (T ^), while in Fig. 10B, the period (Tj) having the period (T_c) is synchronized,

At the beginning of the period (T._w) in Fig. 10A, the signal (DIR) decreases to latch the data from the CPU (1) to the write input of the flip-flop (23W). The data is sent to the data terminal (DB) of the PCGRAM (13) during the period (T₃) when the signal (PCGS) is at L level.

In Fig. 10B, the clock signal (0/2) during the period (T_w) to (L) indicating that the CPU (1) is writing data to the PCG RAM (13).

According to the invention, random data in the PCG RAM (13) can not be undesirably written. The signal (PCGS) is not limited to the period (Tj), so that the driver (33) can not be selected and the data address is not determined. The signal (DIR) is (H) during the periods (Tj and T₂), whereby the driver (33) can not take effect to write any data into the video RAM (10),

A CPU of type Z80A has a set-up time of 50 nsec and a hold time of 0 nsec. An establishment time for data in the present invention can be calculated as follows:

125 n sec - Delay time for digit (23R), compared to the rise of the clock signal (0/2) = 125 n sec - 28 n sec = 97 nsec

After 97 n sec is larger than the setup time of 50 n sec for the CPU (1), data stored in the PCG RAM (13) can be read out, as shown in Figs. 9A and 9B.

After a direct memory access is performed in a time-geschachtelter way for the video RAM (10), the picture tube (9) can not flicker. The video RAM (10) is connected to the (I / O) address of the CPU (1) so that no reduction in the operating speed of the CPU (1) can occur if the video RAM (10) for the display has direct access to the memory As the Fig. 4 can be removed, the I / O address of the CPU (1) remains the same over three or more clock periods, d. H. over 750 n sec or longer. Accordingly, the CPU (1) and kinescope control circuit (34) have access to the memory for a period of 375 n sec, and the video RAM (10) therefore need not be a high-speed RAM.

According to FIGS. 1 and 2, ROM (2) and RAM (3) are assigned to own memory control sections of the CPU (1) while the video RAM (10) is assigned to an I / O section thereof. In this way, the video RAM (10) can be allocated from the (BC) register pair of the CPU (1) in response to (I / O) commands are addressed. Accordingly, as a result of such allocation with respect to ROM (2), RAM (3) and RAM (10), the programmable portion or work area provided in the RAM (3) is not a video RAM area Because the area of ​​the video RAM 10 can be made as large as 32K bytes, a high resolution graphics function such as 640x400 pixels is possible. It is to be noted that the commands given from the CPU (1) to ROM (2) and RAM (3) may be similar to those used in conventional microcomputers, while the I / O commands are easy for the video RAM (10) can be used.

In the following, work instructions for a Z80A CPU will be discussed with respect to transferring data between an outer I / O port (7) and the CPU (1) (and in conjunction therewith RAM (3)). It should be noted previously that the Z80A CPU includes at least A, B, C, D, E, H and L general-purpose registers and transmission of 8-bit data between an outer I / O port (7) and one or more of these Register takes place via the data bus (4). Corresponding address commands are transmitted via the 16-bit address bus, which is formed by the upper 8-bit address bus (5H) and the lower 8-bit address bus (5L). More specifically, the following commands can be used:

1-1 IN A, n

This command transfers 8-bit data to an input port designated by the number ji (n = 0 - 255) to the A register of the CPU.

1-2 OUT η, A

This command transfers 8-bit data from the A register of the CPU to an output port designated port number n. It should be noted that with these instructions, the 8-bit data from the A register appears at both the data terminals (ϋθ to Dy) and the address terminals (Ag to Aj $). In such a case, the lower 8-bit address terminals (Αθ to Ay) are supplied with address commands and indicate the port number ti.

-8Nr. 389773

Π-l INr, (C)

This command transfers data to a port (determined by the port numbers) designated by the BC register pair on an register, the r register being one of the A, B, C, D, E, H and L registers.

Π-2 OUT (C), r

The command transfers data from the jr register to the port (determined by the port number n) designated by the BC register pair. The data for the j * register appears at the data ports (ϋθ to Dy); the C register contains information from the address terminals (Αθ to Ay) corresponding to the port number n ^ and the B register contains information from the address terminals A8 to Al5 corresponding to the I / O device connected to the designated port. After eight bits of information are contained in the G-register, a maximum of 256 (0-255) I / O devices can be connected to each port.

As will be seen below, the following block transfer instructions can also be used with the CPU (1):

m-1 INIR, INDR

With these instructions, a plurality of data bytes, i. i, a block of data to be transferred from a port n to main memory. In such a case, the BC register pair is used to determine the port number (C register) and the number of bytes to be transmitted (B register). The data block is transferred to a memory location whose address is determined by the HL register pair. For example, the last address port to which the data is to be transmitted is stored in the HL register pair. The B register is then used as a counter and counts down to zero. Specifically, the value in the B register is continually reduced by one and during each decrease by one, one byte of the block is transferred. When the value stored in register B has become zero, all bytes of the block are transferred from the corresponding I / O port designated by the C register,

ΙΠ-2 OUR, OTDR

With these instructions, a block of data can be transferred from main memory to an I / O port designated by the C register. The HL register pair and the B register are used in the same way as described above.

It should be noted that the upper 8-bit address terminals (Ag to Aj ^) are different from the I / O address terminals (Αθ to Ay) of the I / O port (7), so that the CPU (1) intervenes between the video -RAM (10) and the I / O port (7).

Having described a particular embodiment of the present invention with the aid of the drawings, it is clear that the present invention is in no way limited to this particular embodiment and that many modifications and variations are possible for the skilled person without the scope of the invention, such he is given by the description and the claims, would have to be exceeded.