Device for static phase error compensation in a phase-lock loop system with a symmetrical structure

A device lock loop phase comprising a phase comparator (PC) having first and second inputs receiving respectively first and second clock signals (Clkref and Clkdly), and first and second outputs provide, respectively, first and second logic signals (Up and Dwn), a block conversion time-voltage symmetrical having at least first and second inputs receiving respectively the first and second logic signals (Up and Dwn) and first and second outputs providing, respectively, a voltage (Vup, Vdwn, Vdiff + and Vdiff-) which is a function of the first and / or second logic signals (Up and Dwn), and a processing block voltage , having first and second inputs receiving, respectively, first and second voltages be treated (Vup, Vdwn, Vdiff + and Vdiff-), characterized in that further comprises first (I1P1 and I1P2) and second (I2P1 and I2P2) pairs of switches opening / alternate closure according to first and second phases (P1 and P2), interleaved between the first and second outputs of the conversion block time-voltage symmetrical, on the one hand, and the first and second inputs of the processing block voltage, moreover, a third (I3P1 and I3P2) and fourth (I4P1 and I4P2) pairs of switches opening / alternative closure according to the first and second phases (P1 and P2), arranged upstream of the first and second inputs of the phase comparator (PC) and steering means, suitable for governing the opening / closing of the first to fourth switch pairs so connect during the first phase (P1) the first clock signal (Clkref) to the first input of the comparator and the second clock signal (Clkdly) to the second input of the comparator, and the first output of conversion block to the second input of processing block, and the second block output conversion to the first input of block treatment, and during the second phase (P2), the first clock signal (Clkref) to the second input of the comparator and the second clock signal (Clkdly) to the first comparator input and the first output of conversion block to the first input of the processing unit and the second conversion block output to the second input of processing block.