Synonym control means for multiple virtual storage systems

© Start of patent period: 1984 11 15 Longest possible duration:

© Issued: 1985 07 10 © inventor:

© dependence:

© Pamphlets considered to delineate the prior art:

017 QtQ TW

U.S. Patent 3,781,808 U.S. Patent 3,902,162

Nr.378273

The invention relates to a memory device with a plurality of virtual address spaces, each of which page or page and segment tables are assigned and contain common of all address spaces virtual memory areas with the same virtual addresses, and at least one contained in a memory side table (DLAT) whose Entries have a field for identifying the respective address space (address space identification).

In systems with virtual addressing, performance enhancements are often made use of so-called DLAT Dynamic Lookaside Address Translation (DLAT) tables. These are fast, in particular associative, memories that store the virtual and real addresses of pages that have recently been addressed. Examples of DLAT can be found in US Pat. Nos. 3,725,874, 3,781,808 and 3,902,163.

In virtual systems with multiple address spaces, the address translation side table encounters the problem of synonymous entries (DLAT synonyms). For example, with multiple address spaces, each user is assigned a different address space; For security reasons, no access should be made from one private address space to another. Since system program routines (eg in the IBM OS / VS2 Release 2 MVS operating system) are required by all programs in all address spaces, so far these shared programs and data have been assigned to one or more segments in each of the address spaces. When a user working in his private address space requested access to shared programs, he addressed those programs within his own address space. However, this separate addressing compromised system performance because the shared programs and data are translated into processor by different DLAT entries. If, for example, two users simultaneously need the same operating program, then this program is written to the main memory page by page and translated for the user's address space. Now, if the other user needs the same program, it will not be written to main memory again, but it will be translated independently for that user's address space. The translation for each individual address space thus led to the undesirable result that too many translation operations were carried out and that a waste of the scarce number of available DLAT entries occurred, since for the l different users of the common programs and data each particular DLAT Entries (ie DLAT synonyms) were generated.

The invention therefore has the object of specifying a device of the aforementioned type, are avoided with the synonymous entries in the address translation side tables (DLAT).

This object is achieved in that for generating a DLAT entry sensing circuits the segment or Querying page tables for the presence of a signal corresponding to a particular bit position, which is set when pages are shared, that the sensing circuits are connected to DLAT charging circuits which in the case of a shareable page in their DLAT entry as access indicator one bit (common Memory area) and that test circuits are connected to the outputs of the DLAT memory, checking, on each access to a selected entry of the DLAT memory, the presence of the access indicator and applying outputs to combination circuits which receive another input from a virtual address comparison circuit; in the presence of the access indicator and correspondence between the virtual address to be translated in the LAR and the virtual address in the selected DLAT entry, independently of the address space identifier of the currently active address space, to transmit the real address (RA) from the selected DLAT entry to a selection gate.

The invention proposes for each segment table entry (STE) or alternatively for each page table entry (PTE) in each private address space, a display (common address area) indicating whether the segment or page contains programs and data private to the address space are assigned or can be shared by all address spaces. This entry in the translation tables is also called the permission indicator. Each entry in the address translation subtables (DLAT) contains a memory indicator shared / private, which is set according to the bit in the STE or PTE used for the address translation for the DLAT entry. This DLAT entry is also called an access indicator

No.378273 called. When the DLAT entry is read, the private / shared memory indicator determines whether the DLAT can be used only by the address space identified in the DLAT or by all address spaces.

The prevention of synonym entries in the DLAT increases system performance by not only requiring 5 fewer translation procrars, but also increasing the number of available DLAT entries (which is already relatively small anyway); The DLAT thus accommodates more translated addresses so that an overflow with the then complicated DLAT administration occurs less frequently. For the shared system routines continue no multiple copies must be kept in main memory. Access to shared system routines is greatly facilitated by the hardware device proposed by the invention.

In the following the invention is described in its basic features; Their details will be explained later with reference to an embodiment. The invention is used in a processor that allows concurrent addressability for the most recently used pages in multiple address spaces through its DLAT entries. The DLAT addressability for different address spaces is usually achieved by providing in each DLAT entry an address space identifier field which uniquely identifies the address space associated with a page; this page is identified by the real page frame (PFRA) address field in the same DLAT entry for receiving the translated page address. Later accesses to data in a translated page addressed by a DLAT entry can be done quickly if the

DLAT entry for addressing the data in main memory or in a working memory (oache) without re-translation of the virtual address is used. Circuits to support these operations, which are used in, for example, the IBM S / 370 Model 168 CPU computing system, are described in U.S. Patent No. 3,781,808.

The invention uses in each segment or page table entry and in each DLAT entry a common memory indicator loaded during translation of the segment table or page table entries to indicate whether a page being addressed via a DLAT entry , Accesses from all address spaces in the system are possible, or access to the page can only be made through the address space identified in the DLAT entry.

The DLAT loading controllers detect this common storage area indicator in each segment table entry (or in each page table entry, corresponding to the design of the virtual addressing in a system under consideration). The common memory indicator is preferably executed as a bit position in each segment table entry. In the other embodiment, this indicator represents a bit position in each page table entry.

An address translator senses the state of the bit common memory area during the translation process in a translated segment table entry (or page entry) and sets the common memory space indicator in the DLAT entry to which the translation result is written to indicate whether the data is in the DLAT entry translated page can be shared or is a private page. If the indicator is not set in the table entry, the translated page is private; in this case, an identifier for the single address space which may use this DLAT entry is also set in this DLAT entry to prevent use by other address spaces. If the common memory bit area is set in the table entry, the DLAT receives an indicator indicating that no address space identifier check is to be made so that this DLAT entry can be used by each address space.

For the invention, it is essential that in the so-called hash addressing (determination of the address of a DLAT entry using individual fields of the virtual address, possibly using an algorithm) no bits from the address space identifier are used, as in the DLAT hash addressing in the prior art is the case (eg

in the aforementioned U.S. Patent No. 3,781,808). This usual hash addressing would not make the invention executable since then same virtual addresses in different address spaces would not address the same pair of DLAT entries. The invention therefore uses only bits from the virtual address for hash addressing but not bits from the address space identifier.

- 4 - No.378273

The read-out DLAT controllers typically sense the address space indicator in each read DLAT entry. For the invention, the DLAT controllers must also sense the common memory area indicators in each read DLAT; this bit would cause a fault condition in conventional processors. If a shared memory area indication is detected in a DLAT and all other conditions are met in the DLAT, the DLAT read control circuits pass the access request with the real address PFRA from the DLAT to the main memory access controllers, which accesses the main memory or the main memory (cache). effect.

The DLAT read controls are extended by the invention in two ways:

1. They establish address space security by rejecting requests for DLAT translations from address spaces whose address space indicator does not match the address space indicator included in the DLAT or

Second they allow all address spaces to use the DLAT translation by ignoring the address space indicator in the DLAT.

Each address space is represented in the system by a segment table defined for the processor by a segment table start address (STO). Each STO represents a real address with the beginning of the segment table. In a system, a very large number of STOs may be available. If any STO is to be used, it is activated by placing it in a control register (CR); it is also given as the next entry in a stack (STOK) for segment table start addresses.

For each STO in the STOK an indicator is available, a so-called STO ID, u.zw. as an index for the STOK. Each STO in each STOK entry and register CR includes 32 bits (one full word). An STO can be included in more than one entry in the STOK. The stack STOK is used to reduce the number of bits required for the address space identification in the DLATs and thus to decrease the DLAT size. Smaller DLATs generally work faster than big ones. For example, a STOK with up to 29 STOs requires only 5 bits for an STO ID to identify an address space; this avoids having to use all 32 bits of the STO. Each time a new STO causes the STOK stack to overflow it will be reset and all DLAT inputs simultaneously; the new STO will be used at the beginning of the STOK and a corresponding DLAT entry will be translated.

An embodiment of the invention will now be described with reference to drawings. Fig. 2 is a block diagram of a preferred embodiment, Fig. 2 shows the main memory allocation in a second embodiment, Fig. 3 shows the formats for control registers, segment table entries and page table entries used in the prior art, Fig. 4A shows a new format of the segment table entry for a 4B shows a new format for the page table entry for another embodiment of the invention, FIG. Fig. 5 shows details of a STOK and its address space identifier (STO DI) control means in the embodiments; Fig. 6 shows the format of each pair of associated DLAT entries which can be accessed with a single DLAT hash address; Details of a translator used in the embodiments, Fig. 8 Details of the DLAT read controls Fig. 9 shows the DLAT charge control in detail.

Fig.l shows a block diagram of a preferred embodiment. A block STOK and controllers -5- includes a control register -CR1- which contains the active segment table start address (STO) which is being used by the virtual addresses of the processor at that time; these virtual addresses are in the logical address register (LAR) -61-, thus indicating the current access address. The controllers -5- also contain a stack for segment table start addresses (STOK) -50- into which each active STO is sequentially read as soon as it is loaded into -CR1-. The address spaces represented by the STOs in STOK are the only address spaces that are represented at this time by entries in the DLAT -6-. Each entry in the STOK has an index value of -2 to 30-. These index values ​​are used as STO identifiers (STO ID). The currently active STO in the STOK is indicated by the STO ID in a pointer register (PTR REG) -51-. The STO ID contained in the pointer register -51- thus points to the STOK entry with the same STO as that contained in the -CR1-. It

No. 378273, only the STO ID -2 to 30- are used, since with an index size of 5 bits, corresponding to the values ​​0 to 31, the values ​​0.1 and 31 in the DLAT for indicating the special conditions invalid STO, no dynamic address translation or shared memory area are used. The latter value is used in the invention to indicate in the DLAT that it is addressing a page that can be accessed by all address spaces. A bigger one

For example, STOK with more STO IDs can be provided if an STO ID with θ

Bits are selected, with which 61 STOK entries (2 -3) can be identified.

The component -54- in Fig.l indicates an overflow of the STOK -50-, if all entries -2 to 30- are occupied and another STO is to be written in STOK. Circuit -54- generates the overflow signal when STO ID -30- is in the register -51- and when searching STOK entries -2 to 30 no next active STO is found in -CR1-. The overflow signal from the circuit -54- is applied to the DLAT load circuits -9- to reset all DLAT entries.

The structure of the DLAT -6- corresponds to that of the IBM System / 370 M168 CPU, except that more entries are provided here. DLAT -6- in Fig.l is an associative memory with two sets, in one half of which the DLAT table 0 is contained with 64 entries denoted 00 to 063 and the other half of which contains the DLAT table 1 also 64 entries and the designations 10 to 163. A DRR register -6B- contains the address of the currently selected pair of DLAT entries. The address of the DDR register -6B- is generated by the hash circuit -6A- in which the bits 9 to 20 of the virtual address in LAR-61- are processed to generate the hash address.

Fig. 6 shows the format of the pair of selected entries addressed via the DRR register. Thereafter, each entry contains an STO ID derived from either the pointer register -51 or a common memory bit C in the segment table entry (STE) used to translate the DLAT entry. With the exception of the extra bit C common memory area in the STE, the form of all entries in segment tables, page tables, CR 0 and 1 corresponds to the system control programs MVS (Multiple Storage Systems) in the OS / VS2 Release 3.7 operating system for an IBM S / 370 M168 data processing system.

The translation of the virtual address in the LAR -61- is usually done by a translator -7- in which the component -SX- of the address leads to the desired STE entry by adding it to the STO address of the segment table in Fig.l. The start address for the page table (PTO) is located in the selected STE and is used by the translator to address the page table entry (PTE), designated PTE-g in FIG. PTE-g is addressed in the page table at location PTO + PX. The real or absolute address of the desired page is found in the PFRA field of the selected PTE and then given by the translator -7- to the load controller -9- and then placed in the absolute address field (RA) in the selected DLAT.

4 shows the novel STE format with bit C (common memory area) in bit position 30; this format is used in the segment table of FIG. Fig. 3 shows the PTE format used in the page table in Fig.l.

When bit C is set to 1 in the STE format, the segment table entry indicates that it is a segment of a shared memory area; this includes all the pages in the page table which is addressable within that STE by means of the PTO address. If bit C is set to 0, then STE defines a private segment, ie it may only be addressed by the address space defined by the STO with which the relevant segment table is addressed.

In Fig. 6, the virtual address (VA) field in the selected DLAT entry also includes bits 8 through 14 from the virtual address in LAR-61- to include this virtual page address in the DLAT of all other virtual page addresses in other DLAT entries. To distinguish entries in which the hash address is always part of the distinguishing features for the virtual addresses contained in the DLAT. The even-key and odd-key fields in the DLAT entries are memory protection keys for the first half and second half of the page, that is, the first 2K bytes and the second 2K bytes of the page if they are 4K bytes in total. The devices for loading the key fields in DLAT -6- does not belong to the subject of this invention;

No. 3,778,273 in the prior art, they are included, for example, in the central unit IBM S / 370 M168 CPU.

DLAT loading occurs whenever the processor has an address in LAR 61 and the read controllers determine that no DLAT entry addresses the page requested by the address in LAR -61-. The absence of such a DLAT entry is reported to the DLAT read controllers -8- in Fig.l via a signal DLAT exception on line -87A- to the translator -7-. The DLAT read controls simultaneously compare all candidate fields of each pair of selected DLAT entries addressed by the hash address in register DRR with corresponding fields to which bits 8 to 14 of the virtual address in LAR - 61-, the STO ID from the pointer register -51- and the key field from the program status word (PSW). If one of the two DLAT entries 0 through 1 compared simultaneously in DLAT read controls -8- matches, the read controls select only the DLAT entry in which all the fields match. The selected DLAT entry then causes controllers -8- to issue a page frame address (RA) as signal on line -89A- to the memory access controllers -12- to initiate access to one or more bytes starting with the RA address that was found in the selected DLAT entry; this is concatenated with the displacement (D) from the LAR -61-.

If the DLAT read controls -8- find a shared memory indicator value of 31 in the STO ID field of the selected DLAT entry, the read controls -8- will ignore compare results unequal, since the STO ID value 31 for all STO ID values ​​will be the comparison result immediately enforces. This allows access to the virtual address LAR -61-, u.zw. regardless of which address space constitutes the access request (corresponding to the contents of the pointer register -51-).

Thus, the STO ID field is loaded with a value indicating whether this DLAT entry can only be used by the address space through which the entry was loaded, or whether it is from all address spaces, regardless of which one did the loading. After this general description of the preferred embodiment, its individual components will be described in more detail.

STOK and controls 5

Figure 5 shows a preferred embodiment for the stack STOK and the associated controllers -5-. The registers -CR0 and CR1- contain the formats shown in Fig. 3, in which bits 8 to 25 of CR represent the active STO address, and bits 8 and 9 in CR 0 indicate the page size (eg, 2K bytes or 4K bytes) and bits 10 and 11 are the segment size, eg 64 K bytes or 1000 K bytes. These bits of the register -CRO- are also written when loading an entry in STOK 50.

The controllers ensure that STOK 50 only contains an STO value once. Valid STO values ​​in STOK 50 are contained in entries 2 through x-1, where x is determined by the contents of a FIFO register -52-. All STOK entries from the index in FIFO register -52- to index 30 are considered invalid.

When a new STO value is loaded into CR1, STOK 50 is searched to determine if that STO is currently stored in STOK 50; if so, the index of this entry is written to pointer register -51- to indicate active STO ID on lines -51C-. If no entry for the active STO in CR1 is contained in STOK, the STO in CR1 is loaded into stack STOK using the index in FIFO register -52- and the FIFO register is set to the next STOK ID value.

The STOK is searched whenever a new STO value is read into CR1. To search, the contents of pointer register -51- are set to STO ID2, corresponding to the first entry in the STOK. Thereafter, the content of the entry 2 is read out and compared with the current STO stored in CR1. If it matches, the STO entry 2 corresponds to the new STO and thus to STO ID2. The match is reported by compare circuit CMPR 56 on line -56A-to gate - 51B-which in turn outputs the contents of pointer register -51- as active STO ID on lines -51C-.

If there is no match, comparison circuit -56- outputs a corresponding signal on line -56B-, the content of pointer register -51- changes to the next one

Nr.378273

- Set 7 STO ID value and compare the corresponding next entry in STOK 50 in comparison circuit -56- with the STO in CR 1. This sequence of steps continues until the comparison matches, or until the STO in CR 1 is loaded into an entry determined by FIFO 52.

The search of the STOK ends when the compare circuit CMPR 53 determines that the contents of the pointer register -51- is equal to the value of the FIFO register -52-. In this case, the active STO in CR1 is not included in any entry of STOK 50, and therefore it is written to the stack STOK at the location currently designated in FIFO register -52-; but this register is then equal to the pointer register -51-. The analog-to-coincidence flag -53- is also provided to the OR gate 58, which in turn provides a Write STO signal to the STOK 50 input gate circuits which inputs the active STO values ​​from CR0 and 1 into the entry designated by FIFO enroll.

The signal match of the comparison circuit -53- continues to set the FIFO register -52- to the next following STO ID value.

Finally, there may be occurrences that in STOK 50 all entries 2 to 30 are occupied with STOs. Then, if a new STO value is loaded in CR1 and there is no STO value in the STOK entries 2 to 30 in a search as described above, then the pointer register -51- is finally set to the value 31; Circuit 54 then determines that this value is greater than 30 and outputs a clear DLAT on line -54A-, invalidating all DLAT entries. The output of circuit -54- also serves to reset the pointer register -51- to the value 2 to address the first entry in STOK 50. In addition, the output signal of the circuit -54- is applied to a delay circuit -57-, whose delay is just so large that it corresponds to the time required to erase all DLAT entries; the delayed signal then passes through an OR gate -58- and causes the writing of the new STO value in the STOK entry 2.

Translator 7

Except for the latch circuit -67- common memory area and the input gate circuits, the translator shown in Fig. 7 corresponds to that used in the central unit IBM S / 370 M168 CPU. The inputs of the translator include the logical address register (LAR) -61-, also shown in FIG. 1, and a translate input register (T1R) -62-. In LAR -61- the virtual addresses are given from the instruction unit of the processor, in register TIR -62- the STOs from register -CR1- as well as the STE and PTE are read from the main memory separately. The position of the common memory bit C in a STE is determined by an output port -62C- which senses bit position 30 in TIR -62-. The output port -62C- is connected to the input for setting the latch circuit COM STG-67-common memory area and sets this circuit when bit C is set; otherwise the locking circuit is reset. The output line -67A- indicates the position of the DLAT charge control latch circuit 9, which sets the common memory area value (COM signal) 31 to the STO ID of a currently selected DLAT entry when BIT C sets common memory area is. If bit C is suspended, the latch circuit -67- is reset and the controllers 9 load the STO ID from the pointer register -51- into the selected DLAT.

The output of the translator -7- supplies the addresses STO + SX or PTO + PX, which are required to read the STE or PTE. The value PFRA + D is not generated by the translator, but is created by concatenating the real address RA from the selected DLAT and the D value from the LAR -61-; this concatenation is done directly in the memory access controllers -12- so as to more quickly generate the byte addresses in a page that is being addressed via a DLAT entry at this time.

A timer -68- controls the timing in the translator. The clock is triggered by a DLAT exception signal on line -67A- by the DLAT read controllers -8-. If no DLAT entry is found, the clock will terminate its operation by generating a load DLAT signal on line -68A- indicating that a PFRA from the PTE is available for writing to the selected DLAT entry.

Nr.378273

DLAT charging control 9

The DLAT charge controller in Fig. 9 includes a plurality of gating circuits for loading the various fields in the selected DLAT. Known (and not shown) LRU circuits select the DLAT entry to be loaded. The circuit for loading the key fields (odd and even) is not shown because it corresponds to that in the IBM S / 370 M168 CPU system. In Fig. 9, the common memory signal generating circuit COM ID GEN 91 is composed of an AND gate supplied with a common memory area signal on line -67A- and a DLAT load signal on line -68A-. The generating circuit -91- then generates bits of 1 on five lines to represent the binary value 31. These lines are routed via OR gate -96- to the STO ID field in the selected DLAT entry.

Line -67A- also outputs the signal common memory area of ​​the latch circuit -67- to an inverter -97- whose output signal blocks a gate STO ID -92- to prevent the active STO ID from passing from the pointer register via line -51C- reaches the OR gate -96-. Thus, when bit C is asserted, the output of OR gate -96- may be only the value 31 at which the common identifier ID for the selected DLAT is displayed.

If the bit for the common memory area is at zero, the circuit -91- does not produce an output signal and the inverter -97- activates the gate circuit -92-; in this case, the STO ID on lines -51C- enters the five-bit STO ID field in the selected DLAT entry via the OR gate -96-.

The port guarding -VA93- routes the LAR bits 8 through 14 on line -61A- into the field -VA- of the selected DLAT, thus enabling identification of the virtual address VA. Similarly, gating circuit -RA94- directs the real address portion PFRA on line -66B- of Figure 7 to the RA field in the selected DLAT.

DLAT reading control 8

The DLAT read controller in Fig. 8 holds two identical DLAT read control circuits -80 and 86- to which the pair of selected DLAT entries in the DLAT tables 0 and 1 are fed. Each circuit -80 and 86- includes a plurality of comparison circuits. For example, comparison circuit -81- in circuit -80- compares the STO ID of the selected DLAT to the active STO ID from pointer register -51- to determine if the DLAT address belongs to the requesting address space. If there is a match, a signal is applied to output line -81B- to OR gate -81A-. Otherwise, no signal is generated on line -81B- and so indicated that the DLAT address does not belong to the requesting address space. However, according to the teachings of the invention, an AND gate -82- is incorporated as a shared memory detector circuit which determines whether the STO ID in the selected DLAT is the shared memory indicator -31-. The circuit -82- is an AND gate which requires all five STO ID input signals to be 1 (corresponding to binary 31) when an output signal is to be given to OR gate -81A-, which does not equal the condition in circuit -81- bridged. Thus, the OR gate -81A- provides an active output if either the received STO IDs are equal or if the DLAT entry is the common ID indicator COM.

A virtual address compare circuit 83 compares the VA fields in the selected DLAT with bit positions 8 through 14 in LAR-61-. If matched, DLAT will translate this virtual address provided that OR gate -81A- issues an address space signal which activates link circuit -84- for DLAT 0, which in turn provides an output to gate circuit -85A- which outputs the absolute address (FIG. RA) from the selected DLAT via an RA register -85-. The real address then passes from the RA register to an RA select gate circuit -89-. The output signals of gate circuits -85A- and output -80A- of circuit -84- also activate a gate circuit -84A- to select the even or odd key from the DLAT entry as input to the key processing circuits 88- ,

The read controls -86- for DLAT 1 comprise identical circuits as the just-mentioned no.378273

The DLAT read controls -80 and 86- (which simultaneously receive the outputs of the two DLATs of the pair selected by the hash address) make the decision as to which DLAT entry of the pair (if at all) corresponds to the current address request in LAR-61- and the pointer register -51-. Only one of the lines -80A or 86A- may be active at a given time, since with a pair of DLAT entries, only one of the two circuits at a time may have a comparison result that is required to activate the respective line. Similarly, only one of the circuits -80 or 86- may provide an output via the gate circuit -85A- to -RA-. The real address -RA- comes as an input to an RA selector gate circuit -89- which, however, can only leave it when the key in the selected DLAT entry is equal to the PSW key received from the key circuits -88- , Upon coincidence of the PSW key and the DLAT key, a signal is generated on line -88A- which turns RA selector gate circuit -89- on and passes the real address -RA-to to the memory access controllers, which in turn provide access to accomplish the main memory. However, if the keys differ in comparison in circuits -88-, a signal on line -88B- indicates a memory protection violation; this signal is passed to the interrupt circuits of the processor and gate -89- prevents access.

OR gate -87- has a complementary output signal indicating that neither input -80A nor 86A- indicates the selection of a DLAT entry 0 or 1 of the pair. The signal on the output line -87B- generates a DLAT exception signal indicating that the virtual address in LAR-61- does not correspond to a current DLAT entry and thus the translator translates the virtual address into a fake page address for a page which may be contained in main memory. If the page is not in main memory, an input / output operation must be performed to transfer the page from an input / output device to main memory before the translator can create a DLAT entry with the translated address.

Common side embodiment

In the embodiment described so far, a common segment indicator has been incorporated into those STEs common to all address spaces, ie all segment tables; all pages in a common segment (ie, the page tables) are implicitly included in the common segment without requiring a special indicator in the page tables. A single bit C for a common segment thus provided the plurality of pages in that segment to all address spaces.

The shared page embodiment relates the shared memory area to the level of the page rather than to the level of the segments. However, in both embodiments, the entry for the shared memory identifier in the DLAT only refers to the page shown by the DLAT entry.

The second embodiment thus makes it possible to define individual pages of a segment as pages with shared access for all address spaces, while other pages in the same segment can be restricted to a single address space. The determining factor which allows pages of other address spaces to be accessed is controlled by setting a shared memory bit C in the page table entries (PTE) and not in the segment table entries (STE). This is illustrated in Fig. 2, where bit C for the shared memory area is represented in an entry PTE-g in the page table i. Thus, the pages represented in the page table can be selectively provided to either one or all of the address spaces by setting or not setting the indicator bit C in the common memory area of ​​the PTE; the STE can thus also have the usual format shown in Figure 3. The new PTE entry in Fig. 2 is shown in Fig. 4B.

The only difference at the circuit level to handle the PTE bit C in FIG. 2 (and not the STE bit in FIG. 1) is shown in FIG. 7, in which the output circuit -62D- of the register TIR is used Condition of the PTE bit 23 to be sensed; an output circuit -62C- need not be present.

All other circuits in Figures 5, 6, 7, 8 and 9 are not changed. The value 31

No.378273 is also used here as an indicator for the common memory area in DLAT, but here it automatically leads to the control of the common access on a page basis and not on a segment basis.

It is understood that the common memory indicator used in the DLAT need not have the value 31, but may take any value unique in all DLATs. For example, it may also be a special indication bit in each DLAT, which is set according to the value of the bit in the translated STE or PTE.