Untitled record

<img file="AT377645B_D0001.tif" />

AUSTRIAN © Int.Cl «: H01L 029/72

PATENTAMT ® AT PATENTSCHRIFT ® Nr.377 645 ® Patentee: SONY CORPORA ΓΙΟΝ TOKYO, JAPAN © Subject: SEMICONDUCTOR COMPONENT © Addendum to Patent No.

© Elimination from:

Registered: 1973 27, 10840/73 © Exhibition priority:

©©© Union Priority: JAPAN (JP) 1972 12 29

48-551 CLAIMED © Beginning of patent period: 1984 08 15 Longest possible duration:

© Issued: 1985 04 10 © inventor:

© dependence:

AI 377 64ö © Pamphlets considered as delineate from the state of the art:

<td>US-PS</td><td> 3591430</td><td>OE-A</td><td> 1564509</td><td>GB-PS</td><td> 1160429</td><td>DE-OS</td><td> 2048737</td>

<td>US-PS</td><td> 3512056</td><td>DE-GS</td><td> 1764765</td><td>US-PS</td><td> 3544863</td><td>DE-OS</td><td> 1614383</td>

<td>DE-GS</td><td> 2364753</td><td>OE-AS</td><td> 1297237</td><td>DE-AS</td><td> 1639067</td><td>CH-PS</td><td> 526860</td>

<td>CH-PS</td><td> 473478</td><td>CH-PS</td><td> 492307</td><td>CH-PS</td><td> 491502</td><td>CH-PS</td><td> 484519</td>

<td>CH-PS</td><td> 474862</td><td>DE-OS</td><td> 1917013</td><td>FR-PS</td><td> 2130399</td><td>US-PS</td><td> 3500141</td>

<td>US-PS</td><td> 2822310</td><td>DE-CS</td><td> 2320563</td><td>OE-A</td><td> 2364752</td><td></td><td></td>

Nr.377645

The invention relates to a semiconductor device having a first region of a first conductivity type whose thickness is smaller than the diffusion length of the minority carriers in the same, a second zone of a second, opposite to the first conductivity type, which completely surrounds the first zone within the semiconductor device, a third First conductivity type zone completely surrounding the second zone within the semiconductor device, a fourth zone of the second conductivity type formed in the first zone, first, second and third electrodes disposed on the first, second and third zones, respectively, wherein the first and second zones are contiguous to form a PN junction and when this PN is polarized Passage in the forward direction majority charge carriers of the first zone via the second to the third zone.

It has been customary to provide transistors with a highly doped emitter region. There are also known for high-frequency operation transistors, which have a low impurity concentration in the emitter and in the collector region. An example of this is described in U.S. Patent No. 3,591,430. In this prior publication, it is also proposed to cover a substantial portion of the emitter region with a high impurity concentration region and also the collector region with a second high impurity concentration region. In the said US-PS is not explained, however, that the diffusion length or depth of diffusion of the minority carrier must be greater than the width or Width of the emitter region, nor is it stated there that the minority carrier reflected by the built-in field should substantially equalize the injected minority carrier diffusion current flowing from the base through the emitter.

Nor does this American patent teach how to obtain the final profile or distribution of impurity concentration nor what width or width the base or emitter should have. Nothing is said about the conditions for epitaxial growth (such as temperature or precipitation and velocities). It only mentions something about the prediffusion condition, which, however, does not give any inference and no picture of the final construction.

In the production of conventional bipolar transistors, it has hitherto been customary to use a double-diffusion technique for the formation of the emitter-base junction. From the theoretical point of view, as well as from experiments, the doping concentration for the emitter is chosen to be higher than for the base. As this difference becomes larger, the emitter efficiency or emitter efficiency also becomes larger and approaches more and more the value one. However, a higher doping increases the lattice defects and dislocations in the semiconductor substrate. As a consequence of a strong doping, the diffusion length or depth of the minority carriers in the doped region decreases. However, lowering the doping, in accordance with the previously known embodiments of transistors, results in a decrease in the gain.

From US Pat. No. 2,822,310 a semiconductor device is known, in which a fourth zone of the collector zone is arranged and in which the gradient of the minority carriers is to be reduced by the fact that the total thickness is chosen to be greater than the diffusion length of the minority carrier. The fourth zone thus does not have an injector effect in this known semiconductor component, and neither the current amplification factor nor the noise characteristics can thereby be significantly improved.

The invention is thus based on the object of providing a semiconductor component which is substantially improved in terms of its characteristic characteristics, which is distinguished, above all, by a very substantial increased current amplification factor with greatly improved noise characteristics. The component should also have a high breakdown voltage at low thermally induced characteristic value deviations , Finally, it is an object of the invention to design the semiconductor device to be created in such a way that the manufacture and use as an integrated circuit together with conventional transistors, including the complementary transistors, is possible.

Specifically, the invention thus relates to a semiconductor device having a plurality of junctions, as are provided, for example, in a bipolar transistor or a thyristor, and more particularly relates to such a device with low impurity number 377645

3 concentration in the emitter region and with an effective minority carrier diffusion length which is substantially larger than the width of the emitter region, in combination with a built-in

Barrier which generates minority carriers to be injected into the emitter region which substantially equalize minority carriers injected into the emitter region from the base region and so maintain a substantially flat profile of the injected minority carriers. The impurity concentration of the collector region is set low to ensure a high breakdown voltage.

For conventional transistors, it is believed that the minority carrier diffusion length is on the order of 1 to 2 pm. On the other hand, for the multi-junction semiconductor device of the invention, the minority carrier diffusion length is 50 to 100 μm. The current amplification factor of a conventional transistor is usually about 500, while the semiconductor device of the invention can achieve values ​​of 3000 or more.

The object of the invention is to provide a semiconductor device with multiple transitions, which has a high h_pEValue (current amplification factor) with low noise characteristic. This semiconductor device should have a low impurity concentration in the emitter region and a minority carrier diffusion length that is substantially larger than the width of the emitter and that has a low recombination velocity.

This object is achieved in a semiconductor device of the type mentioned in the present invention that the total thickness of the first and fourth zone is smaller than the diffusion length of the minority carriers in the first zone and preferably 2 to 5 pm, that further the thickness of the fourth zone is smaller than the thickness of the first zone is, the fourth zone is left floating, ie having no terminal electrode, the current injected from the fourth zone into the first zone is substantially equal to that of the second

Zone is in the first zone injected current, and thus compensated for and that finally the concentration of the minority carriers in the first zone and the fourth zone is substantially above the equilibrium concentration.

The invention is explained below with reference to the drawings, for example. FIG. 1 shows a partial schematic sectional view of a semiconductor component (npn transistor 30) according to the invention; FIG. 2 shows an exemplary impurity profile for the semiconductor component according to FIG. 1 and the illustration of the minority carrier concentration in the emitter region; 3 is a partial sectional view of an integrated circuit chip including an npn transistor according to the invention and an additional pnp transistor of conventional design, both of which together form a complementary pair of transistors in the integrated circuit chip; Figures 4, 5 and 6 of the partial sectional view of Fig.l similar partial sectional views to illustrate other embodiments of the invention; 7 shows the graphical representation of the (related to mass) emitter current gain (h_FE) as a function of the collector current; 8 shows the representation of the noise factor as a function of the frequency at an input impedance of 1000 ohms; Figure 9 shows the representation of the noise factor as a function of frequency at an input impedance of 30 ohms; Fig. 10 is a noise value representation for illustrating the noise factor as a function of the collector current; 11 is a graph of emitter current gain (h_gE) above the temperature.

A preferred embodiment of the invention is shown in Fig.l as npn transistor. A substrate -1-, in particular a silicon substrate, is heavily doped with antimony. The doping concentration is preferably 4χ10¹⁸ At / cm³, This gives a specific resistance⁴⁵ of about 0.018 cm. It has been found that this value can vary between 0.008 and 0.012 β cm for this doping. The thickness of the substrate is preferably about 250 μm.

An n-type silicon epitaxial layer -2- is deposited on the substrate -1- for use as a collector together with the n⁺formed conductive substrate. The epitaxial layer -2- is relatively low doped with antimony, but sufficient to a doping concentration of 50 7 χ io¹'At / cm³ to reach. The specific resistance is about 8 to 10 Ω cm. The epitaxial layer is preferably about 20 pm thick.

A p "-type silicon epitaxial layer -3- is then deposited on the n⁺conductive layer -2- formed as an active base for the transistor. As a dopant, boron may be provided in such an amount as to provide a doping concentration of 1 × 10 -7 atm / cm³ results. The specific resistance is then 1.5 8 cm. The thickness of the layer -3- is about 5 pm.

An n-type silicon epitaxial layer -4- is then formed on the p~-type layer -3- as an emitter region. This layer -4- is lightly doped with antimony, with the doping concentration being about 5.5χ10¹⁶ At / cm³ is. The specific resistance is about 1 slcm. The thickness of this layer -4- is about 2 to 5 pm.

On the n-type layer -4- is then an emitter contact area an n⁺-leading diffusion layer applied. This layer -5- is doped with phosphorus, with a surface contamination concentration of 5χ10²⁰ At / cm³ and has a depth of about 1.0 pm.

A heavily doped n⁺conductive diffusion region -6- is then provided as a cladding for the collector region, and this region -6- penetrates the p ~ -type base layer -3- and the n-type collector layer -2-. As an impurity phosphorus is provided, and the doping is about 3 χ 10¹⁵ At / cm³ as an area concentration. A p-type region -7- penetrates through n-type emitter layer -4- into p-type base layer -3- which surrounds and confines emitter -4-. The doping is carried out with boron and results in a surface concentration of 7 χ 10¹⁹ At / cm³, A p⁺The conductive region -8- is formed in the region -7- as a base contact region by diffusion, wherein the region -8- is highly boron-doped, and an area concentration of about 5 χ 10¹⁸ At / cm³ having. The penetration depth of the region -8- is about 1.8 pm.

A passivating silicon dioxide layer -206- surrounds the upper surface of the device.

An aluminum collector electrode -9- is on the n⁺conductive substrate -1- formed. An aluminum base electrode -10- is provided on the base contact area -8-. On the emitter contact region -5-, an emitter electrode -11- is formed of aluminum. A p⁺Conductive Range -200- (Injector Zone) is in the n^-diffused emitter region -4- to produce a pn junction between this region and the emitter -4-. The region -200 is boron-doped and is produced simultaneously with the formation of the base contact region -8-. The doping concentration is 5 χ 10¹⁸ At / cm³ and the depth of the range -200- is about 1.8 pm.

From the above, it can be seen that the n-type layer -2- and the p-type layer -3- form a collector-base junction -12-. The p~-type layer -3- and the n-type layer -4- form an emitter-base junction -13- and the n-type layer -4- and the additional p⁺- conductive region -200- form, as already mentioned, an additional pn junction -14-. The distance between the emitter-base junction -13- and the additional pn junction -14- is preferably 2 to 5 pm.

3 shows a second embodiment of the invention, in which the npn transistor according to FIG. 1 is arranged in an integrated circuit together with other semiconductor elements, for example a pnp transistor. The integrated circuit shown has two different types of transistors, for example complementary transistors, an npn transistor -21- and a pnp transistor -22-. These two transistors are fabricated in a p-type silicon substrate. As already explained with reference to FIG. 1, the npn transistor -21- has a heavily doped collector region -1-, a lightly doped collector region -2-, a low-doped base region -3-, a low-doped emitter region -4- , a heavily doped emitter contact region -5-, a collector junction region -6-, a collector contact region -15-, a base junction region -7-, a base contact region -8-, an additional region -200-, a collector electrode -9-, a base electrode -10- and an emitter electrode -11-.

The pnp transistor -22- has a p-type collector -33-, an n-type base -34-, a p⁺emitter region -38-, a p-type collector junction region -37-, a p⁺conductive collector contact area -48-, an n⁺conductive base contact area -35-, a collector electrode -39-, a base electrode -40- and an emitter electrode -41-.

Transistors -21 and 22- are electrically isolated from each other by pn junctions.

Nr.377645

A p-type isolation region -50- is connected to the p-type substrate -20- and surrounds the npn and pnp transistors -21 and 22-, respectively.

Three n-type regions -31, 32 and 36- together form a cup-like isolation region surrounding only the pnp transistor -22-. In this integrated circuit becomes a

Plurality of pairs or trios of transistors simultaneously generated, for example, the n⁺conductive regions -1 and 31- by selective diffusion into the p-type substrate -20-. The n "-type regions -2 and 32- are generated by epitaxial growth. The p^-The npn transistor -21- conducting region -3- and the p'-conducting region -33- of the pnp transistor -22- are driven either by epitaxial growth or by selective growth

Diffusion generated. The n "-type region -4- of the npn transistor -21- and the n-type region -34- of the pnp transistor -22- are manufactured by epitaxial growth. The n⁺conductive areas -6 and 36- are generated by diffusion. The p-type regions -7 and 37- are made by Difussion. The p⁺conducting region -8- of npn transistor -21-, the additional p⁺conducting region -200- of the transistor -21-, which serves as an injector, and the p⁺conductive region -38- of the pnp transistor -22- are made by diffusion, as are the n⁺- Leading areas -5, 15 and 35-.

Fig. 4 shows a third embodiment of the invention in which an additional area -201- is connected to the base terminal area -7- and base -3-. The base electrode -10- may be disposed not only at the base terminal region -7- but also at the additional region -201-. The effective base resistance is lowered because the holes are transported both over the emitter region -4- and over the base terminal region -7- to the base region -3-.

Fig. 5 shows a fourth embodiment of the invention in which an MIS (metal-insulator-semiconductor) device is applied to the surface of the low-doped emitter -4-. An aluminum gate electrode -42- and a silicon dioxide layer -41- together with the emitter region -4- form the MIS arrangement. By applying a predetermined voltage to the gate electrode -42-, a barrier -202- appears under the insulating layer -41-. This results in a blocking layer, a depletion layer or an enrichment layer.

Fig. 6 illustrates a fifth embodiment of the invention in which a Schottky³⁰ Barrier layer -203- is formed on the surface of the low-doped emitter region -4-. To form the Schottky barrier layer, a suitable metal -51-, for example platinum, is deposited on the n^-conductive emitter region -4- knocked down.

Fig. 2 illustrates the impurity profile and the minority carrier concentration in the emitter of the semiconductor device according to Fig.l. The upper part of Figure 2 shows the n⁺conductive silicon³⁵ substrate -1-, the n^--conducting collector range -2-, the p~-type base region -3-, the emitter region -4- and the p⁺conductive area -200, which serves as an injector. The impurity concentration in each of these regions is illustrated in the middle section of the illustration, while the lower part illustrates the injected minority carrier concentration in the emitter region, which consists of the base region -3- and the pn junction -14-, the region -200 and the Emitter region -4-, giving combined injected minority carrier current. In particular, the inclined gradient line -101- shows the component of the minority carrier injected from the emitter-base junction -13, while the gradient line -102- illustrates the component caused by the additional pn junction -14- by the injected minority carrier current. As a result, since the injected minority carriers flow in opposite directions, the result is a substantially flat or even gradient line. This characteristic feature is primarily responsible for ensuring that very high emitter current gain (i.e. _FE) can be achieved at very low noise. To explain this in further detail, it should be noted that the minority carriers (the holes) injected through the emitter-base junction -13- are the additional one⁵⁰ reach transition -14- to enter the additional injector zone 200. On the other hand, the p⁺injector region 200 holes into the n-type emitter region -4- and these holes pass through the emitter region and reach the emitter-base junction -13 * - since the width of the emitter (W_e) is smaller than the diffusion length

No. 377645 in the n ~ -type emitter region -4-. If the hole injection from the p-type injector zone is large enough, the hole current from the additional transition -14- to transition -13- compensates for the hole current from the transition -13- to the additional transition -14-. This compensation leads to the substantially flat hole distribution in the n^-emitter region and reduces the hole current from base region -3- to emitter region -4-.

The arrangement explained above with reference to FIG. 1 results in a high h_FECharacteristic with low noise. To explain this result obtained, it should be noted above all that the (related to mass) emitter current amplification (h_FE) is one of the most important transistor parameters. This size is generally given α

<img file="AT377645B_D0002.tif" />

where α is the current gain at grounded base. The current gain a is given to α = α *. β. υ (2) where α * is a collector multiplication ratio, β is a base transport factor, and v is the emitter-side efficiency.

For example, for an npn transistor, the emitter efficiency is given too

Jn 1 υ = - = - (3)

Jn + Jp 1 + Jp / Jn where Jn denotes the electron current density resulting from the electrons injected via the emitter-base junction from the emitter to the base, and Jp characterizes a hole current density of those holes passing through the same transition from the base to the emitter be injected in the reverse direction.

The decrease of Jp causes the value of υ to become approximately unity according to Equation (3), the value of o becomes very large according to Equation (2), and the value of h _fE according to equation (1) also becomes very large.

The low noise characteristics can be explained as follows:

The lattice defect or dislocation is greatly reduced since the emitter-base junction is formed by the low-doped emitter region -4- and the likewise low-doped base region -3-. The impurity concentration of the low-doped emitter region -4- should be limited to a value that is about smaller than 10 with respect to the noise characteristics, the lifetime τ and the minor particle carrier diffusion length Lp¹⁸ At / cm³.

Another factor that leads to a low noise level is that the emitter current flows in the low-doped emitter region -4- and also the low-doped base region -3- largely in the vertical direction.

The high emitter current gain (h_FE) (in the case of a ground-referenced emitter) for the device according to FIG. 1 is illustrated in FIG. 7 by two lines 104 and 105. The two curves represent experimental values ​​obtained on two different transistors. These differences in the two curves arise only from the different planar configuration of the emitter. Both curves, however, show the very high emitter current gain.

FIG. 8 illustrates the noise behavior as a function of frequency for the semiconductor device of FIG. 1 when the input impedance is 1000 ohms, the collector current is 1 mA and a collector-emitter bias voltage of 6 volts is applied. The value of the noise factor is represented by line 106. In contrast, line 107 shows the noise factor for a typical conventional transistor with extremely low noise levels.

FIG. 9 shows a representation similar to FIG. 8, with the line 108 at the ratios

7-1077645 illustrates the semiconductor component according to FIG. 1 and the line 109 shows the noise factor for a known semiconductor component. The curves of Fig. 9 are based on an input impedance of 30 ohms, but the collector current and the voltage between collector and emitter were the same as those shown in Fig. 8.

10 shows a noise map Rg versus lc (collector current) for the noise behavior of a typical known transistor and for the semiconductor device according to FIG. 1, where the noise line 110 represents the ratios for a typical known semiconductor device and the line 111 shows the noise behavior of the semiconductor device according to FIG .l. Both representations are related to a noise value of 3 dB (F = 10 Hz, V_CE = 6V).

Finally, FIG. 11 shows the representation of the values ​​for Δ h normalized to 25 ° C. _EE above the

Temperature.

hpp (T) - h "(25 ° C)

FE h_pE (25 ° C)

The illustration is understandable without further explanation, if it should be noted that the line 112 refers to a known device, while the line 113 represents the Ver15 ratios in the semiconductor device according to Fig.l.

For a person skilled in the art, it will be apparent from a consideration and from a comparison of FIG.

8, 9, 10 and 11 that with the invention a very significant improvement over the prior art has been achieved.

The term essentially flat, which was used to represent the ratios at the minor carrier concentration over the active emitter region, shall be understood to mean that the sum of the minority carriers injected from the active base region into the active emitter region, on the one hand, and that in the emitter, respectively Lock in the reverse direction moving minority carrier on the other hand in the active emitter region is substantially constant. This is shown for the emitter part in Figure 2 by the line 103, which extends substantially horizontally.

In the subject invention, the low recombination rate is not only obtained by the mentioned barrier, but also results from a built-up in the emitter zone inner field. The explanation for this follows from the following:

The electron current density Jn is given to q. Dn. Np Jn = 30 Ln

The hole current density on the other hand results in q. Dp. Pn jp = Lp where Ln is the electron diffusion length in the p-type base, Lp is the hole diffusion length in the n-type emitter, Dn is the electron diffusion constant, Dp is holes 35 diffusion constant, and Np is the minority electron concentration in the p-type base in the equilibrium state with Pn the minority hole concentration in the p-type emitter in the equilibrium state, with v the voltage applied to the emitter-base junction, with T the temperature, where q is the electron charge and k is the Boltzmann constant.

The ratio value δ of Jp and Jn is then:

qv t kT ,, (e -1) (4) qv (e ^kT -1) (5)

No.377645 logo CNRS logo INIST ^JP - ^ln DP Pn

Jn Lp Dn Np (6)

It follows

W Dp Na Lp Dn N _D (7)

If the two ratios are replaced, the result is

Pn &lt;N

Np N_d where with the impurity concentration in the base region, with N_D the impurity concentration in the emitter region and W is the base width which limits the electron diffusion length Ln in the base region.

The carrier diffusion constants Dn and Dp are functions of carrier mobility and temperature, and can be set essentially constant.

The built-in field is formed in the emitter between the lightly doped emitter region -4- and the heavily doped emitter contact region -5- and acts in such a direction that the hole current from the emitter-base junction -13- is reflected against the transition -14-. If the internal emitter field is large enough, the diffusion current at holes against the emitter contact region -5- is compensated and becomes nearly equal to the field drift current at holes.

The additional barrier and the inner field therefore contribute to achieving the low recombination velocity at the interface, ie the value for Lp in equation (7) is not limited by the width or width of the emitter.

Although the invention has been explained with reference to an npn transistor, a corresponding structure for a pnp transistor and its characteristics will be apparent to those skilled in the art. It should also be noted that the invention can advantageously be applied by simple transfer of the above-described measures to a semiconductor thyristor of the npnp type.