Method and apparatus for optimized parallel testing and access of electronic circuits

Claims a parallel testing structure (PTA), convenient for visits multiple electronic circuit (i.e. in), for optimizing the debugging, or programmable configuration circuit. PTA, connected with the PTB test controller comprises parallel test bus, and connected with the PTB multiple addressable PTB controllers; each addressable PTB controller the coupling to visited corresponding electronic circuit is. Testing the controller is made of generator at least one control signal, a start to the corresponding addressable PTB controller is PTB of the corresponding addressable PTB controller for is provided with a connection the parallel scanning access of electronic circuit. A clock, each addressable PTB controller is composed is a scanning protocol, order to act according to a testing the controller and control signal access on PTB transmission of with a connection corresponding electronic circuit, and responded the visiting the corresponding electronic circuit, and is PTB to the first controller transmission result scanning data.