A method of and a circuit arrangement for the generation and inductive transmission of fm signals

Start of patent duration: Longest possible duration: Issued on: Inventor:

Detfurth

1979 05 15

1980 01 10

IDEAL BERND

FEDERAL REPUBLIC OF GERMANY © Dependence:

© Pamphlets considered to delineate the prior art:

354 315

- 2 No. 354315

The invention relates to a circuit arrangement for generating a stepped, periodic

A voltage at which the envelope of a single voltage step represents a 1/4 period of a sinusoid.

Such circuitry is needed, for example, in an apparatus for generating and transmitting FM signals in an electronic traffic guidance system for providing a stepped, periodic voltage as the output voltage for generating a sinusoidal voltage. In such a traffic guidance system there is a desire to simplify the individual circuits as much as possible in view of a space and cost-saving construction of the required vehicle and road devices, with largely digital components are to be applied, to enable a structure in an integrated circuit.

The object of the invention is therefore to provide a circuit arrangement of the type described above, in which the Auslangen is found with the smallest possible number of modules and yet exactly symmetrical Spannungsstreppen arise, as they are required for the generation of an exact sine wave voltage.

This object is achieved in that the circuit arrangement comprises a counter and a controlled logic state of the output signals of the counter logic circuit, with a downstream network of resistors is connected in parallel, wherein the resistor network is followed by a further resistor to which a supply voltage can be applied is that the resistors are sized in number and in their values, that in a stepwise switching of the resistors in the order of increasing resistance values ​​by means of the logic circuit between the parallel-connected resistors and the downstream resistor during the first half of the value range of the counter, a rising voltage step is formed and that during the second half of the value range, the individual resistors through-connected in reverse order become.

In the circuit arrangement according to the invention thus one and the same resistor network is used both in the rising and in the falling voltage staircase, so that on the one hand for the generation of the stepped, periodic voltage only as many resistors are needed as for the generation of a single Spannungsstreppe, and on the other successive Spannungsstreppen are exactly symmetrical. For the conversion of the stepped, periodic voltage thus only a sign reversal of every second consisting of a rising and falling voltage staircase period and a smoothing need to be made.

An exemplary embodiment of the invention, in which the circuit arrangement according to the invention serves as a converter in a device for generating and inductive transmission of FM signals in a traffic guidance system, is explained in more detail below with reference to the drawings. 2 shows the block diagram of the vehicle device, and FIG. 3 shows the circuit diagram of the device according to the invention for generating and inductive transmission of FM signals, as in both the transmitter of the road device as well as in the transmitter of the vehicle device is present.

The illustrated traffic guidance system consists essentially of vehicle devices installed in vehicles and road devices attached to roads. A vehicle unit contains the modules Receiver Transmitter - 2--, Cycle Control - 3--, Address Switch - 4--, Display Unit - 5-- and

Ferrite antenna --6--. A road device placed at traffic-critical decision points such as motorway exits, intersections, triangles, and intersections includes the assemblies road loop -7--, receiver -8--, transmitter -9--, cycle control -10-- , Address memory --11 and transmission device --12-- to a central traffic computer --13--.

The data exchange between the road device and the vehicle device takes place via an induction loop inserted into the roadway -7-- and a ferrite antenna attached to the vehicle - 6--.

The input, output and storage of information takes place both in the road device and in the

Vehicle device purely digital. For transmission via the loop -7-- or the ferrite antenna --6-- a binary information is converted into a pulse width modulation and then into a frequency modulation. Two frequencies are used which are obtained by a switchable frequency divider - 14 - from a quartz-stabilized oscillator - 15--. Its frequency of 4.433 MHz is divided by a total of 40 and by 30, so that one receives the two frequencies f = 111 kHz and f = 148 kHz, o

- 3 No. 354315

All occurring binary information is encoded using the frequencies f and f as follows:

The state Low (L) is represented by a signal of seven periods with the frequency of 148 kHz and 16 periods with the frequency of 111 kHz, the state High (H) is represented by a signal of 22 periods with the frequency of 148 kHz and 6 periods with the frequency of 111 kHz shown.

A so-called starting step is represented by a signal of 30 periods with the frequency of 148 kHz and 6 periods with the frequency of 111 kHz.

For the purpose of exchanging information between road device and vehicle device, the road device continuously sends phone steps that are identical to the start step just described.

If a vehicle equipped with a vehicle device is located above an induction loop -7-, the call steps are taken and evaluated by the vehicle device. The call steps are used to turn off the vehicle receiver -1- and simultaneously turn on the vehicle transmitter -2-, which in turn transmits a destination address set in the address switch -4- of the vehicle to the road device.

The address switch -4- is set up as a four-digit hexadecimal code coding switch. Accordingly, a destination telegram is 16 bits long. With this telegram length there are 65536 destinations.

The telegram starts with a start step, which switches off the transmitter -9- of the road device and switches on the receiver -8-. Then the 16 blt of the target telegram are transmitted, u.zw. three times in succession, whereby two consecutive telegrams are checked for identity.

Thereafter, the switchover takes place automatically in the vehicle to receive and in the road device to send. The road device sends a start step and an instruction telegram containing direction, speed and special instructions, consisting of 8 bits, also three times in a row. This completes the data transfer.

The block diagrams of the road device and the vehicle device will be described in outline below. Since the electronics of the road device of the vehicle device is largely the same, identical reference numbers are used for identical components in both devices.

A signal received via the induction loop -7- passes through a low-pass filter -16-, an amplifier -17- and a limiter -18- which brings it to a rectangular form with TTL level, and an AND gate -19- to a counter -20-, with which the two frequencies f and f are determined in a period duration measurement. The counting frequency is the natural frequency of the oscillator -15-, which is connected to an input of the AND gate -19-. A decoder -21- of counter -20- provides a pulse for each period. These pulses are counted in a period counter and, on the one hand, in a start step detection circuit, the information start step, if present, is detected; on the other hand, the information Low and High are obtained in a bit recognition circuit.

If a start step that a vehicle has sent is detected by the start step detection circuit -23-, the latter interrupts the call step act transmitted from the road device by means of a call step act circuit -25- and a changeover circuit -26- included in the cycle control -10- , The receiver -8- of the road device remains switched on until the destination address of the vehicle has been received three times.

The 16-bit target address is, as already mentioned, sent three times by the vehicle. Of the bit detection circuit -24- the signal passes on the one hand via a bit counter -27- to an input of an AND gate -28-, on the other hand, it is serving as a 16-bit buffer -29- shift register and an input of a Exclusive-OR gate supplied -30-. The output of the 16-bit latch -29- is connected to a second input of the Exclusive-OR gate -30- and to a memory -31-. The output of the Exclusive-OR gate -30- is connected to a flip-flop -32-. The outputs of the flip-flop -32- and the memory -31- are at other inputs of the AND gate -28-. If the bit counter has counted from -27 to sixteen and two consecutive telegrams contained in the signal were identical, the telegram content is forwarded to the memory -31-, and the destination address contained in the telegram enters via the AND element -28- Storage and programming unit -33-.

- 4 No. 354315

The storage and programming unit -33- is constructed so that in it the incoming

Destination addresses are assigned to the associated direction instructions. After taking a

Destination address is via a connection from the output of the And-element -28- to an input of

Switching Circuit -26- Switches the road device from Receive to Send.

From the storage and programming unit -33- belonging to a destination address direction statement, including any additional information is passed to a parallel-to-serial converter -34-, so that in the storage and programming unit -33- space for new instructions is created received by the central traffic computer -13- via the transmitter -12-. As transmission means between the transmission device -12- and the central traffic computer -13- can be used on highways already existing telephone lines.

The. The instruction telegram taken from the parallel-to-serial converter -34- has a circumference of 8 bits and is composed as follows: 2 bits for one direction instruction, one additional bit. Out of the eight possibilities of these three bits, the encodings for directional instructions are obtained without additional instruction and directional instructions with the additional instructions target out, goal accomplished and wrong direction on; 2 bits for a recommended speed, 2 bits for a road condition report, 1 bit not yet used.

As already mentioned, a road device transmits in idle mode, ie when there is no data exchange with a vehicle, ongoing call trains with intervening receive pauses in which a vehicle can respond after receiving a call step. The transmission of the call steps as well as the transmission of instruction messages is controlled by the cycle control -10-. It consists essentially of the Anrufschrittaktschaltung -25-, the Umsteuerschaltung -26-, the parallel serial converter -34-, a coding counter -35-, a bit counter -36- and a data chart counter -37-.

The Anrufschrittaktschaltung -25- ensures that while the coding of a call step, the transmitter -9- of the road device remains turned on and after sending the receiver -8- is turned on for a short time. The telegram counter -37- causes a telegram consisting of a start step and the instruction applied to the parallel-to-serial converter -34- is sent three times.

The 8 bits of the instruction are applied in parallel to the parallel-to-serial converter -34- and are interrogated serially via the bit counter -36-, and they reach the coding counter -35- as states Low or High in parallel. The latter converts it into the period number of the frequencies f and f corresponding to the states and is counted with the transmitted frequency. After reaching the necessary for low or high oscillation number f ^ of the encoder counter -35- a switching signal to the tin transmitter -9- belonging switchable frequency divider -14- from, so that then sent on with the frequency f.

At the output of the switchable frequency divider -14- arise the frequency-modulated telegram pulses mentioned above. These square waves are at an input of an AND gate -38-, whose second input is connected to an output of Umsteuerschaltung -26-. The second output of Umsteuerschaltung -26- is connected to an input of the AND gate -19-.

From the output of the AND gate -38- enter the square waves in a transducer -39-, where they are transformed into sinusoids. The sine waves are amplified in a transmitter output stage -40- and transmitted via the road loop -7- to the vehicle.

It will now be explained the block diagram of the vehicle device, as far as it deviates from that of the road device.

Receives the vehicle unit a call step of the road device, the signal received from the ferrite antenna -6- passes on already described in the road device components of the vehicle receiver - 1- to the period counter -22-, then in a call step detection circuit -41-. From there, a signal is applied to an input of an OR gate -42- whose output is connected to the reversing circuit -26-. The Umsteuerschaltung -26- causes a turn off the receiver -1- and a simultaneous turn on the transmitter -2-.

As already mentioned, at the address switch -4- a destination address is set, the 16 bit of the parallel-serial converter -34- lie parallel. As with the road device, the instruction telegram, a destination telegram is now sent from the vehicle unit, wherein the cycle control -3- of the vehicle 5 Nr.354315 device differs from that of the road device only in that a bit counter -43- is designed for 16 bit and that the output of the telegram counter -37- is connected directly to an input of the Umsteuerschaltung -26-, so that the Anrufschrittaktschaltung -25- deleted. After the transmission of a destination telegram three times, the telegram counter -37- ensures that via the reversal circuit -26- the transmitter -2- is turned off and the receiver -1- is turned on for at least the time for the transmission of three telegrams, so that a Instruction telegram of the road device can be received.

The transmitter -2- of the vehicle unit is identical to the transmitter -9- of the road device.

Now receives the vehicle device an instruction message of the road device, which is known to consist of 8 bits and is sent three times in succession, so the telegram enters the bit detection circuit -24-, where again the information about the states low and high is obtained.

The output of the bit detection circuit -24- is evaluated up to the AND gate -28- in the same way as in the roadside device, with now only a bit counter designed for 8 bit -44 and an 8-bit latch -45 - as well as a memory designed for 8 bit -46- use.

If two consecutive instruction telegrams are identified as identical, the telegram content is visually displayed via the output of the AND element -28- on a display field -47-. If the instruction telegram contains, for example, the direction statement to the left and the additional instruction fog, the left directional arrow and the text fog light up on the display field -47-. A three-tone generator -48- and a loudspeaker -49- indicate the arrival of an instruction telegram.

Via a connection from the output of the AND element -28- to a second input of the OR element -42- the receiver -1- of the vehicle device is switched off after the reception of the instruction telegram by means of the reversal circuit -26-.

As a rule, the instructions on the display field -47- are retained until a renewed exchange of data takes place between the vehicle unit and another road unit. However, the display field can also be previously deleted by hand by means of a switch -50- the instruction message is deleted in the memory -46-.

After the block diagrams of the road device and the vehicle device have been described, the circuit for generating and inductive transmission of FM signals will be described below, which is used both in the transmitter -2- of the vehicle unit and in the transmitter -9- of the road device used ,

The new transmitter consists essentially of the following components: oscillator circuit -51-, first frequency doubler circuit -52-, switchable frequency divider -53-, second frequency doubler circuit -54-, converter -55-, power amplifier -56-.

In the oscillator circuit -51-, in which the quartz oscillator -15- is preceded by a parallel circuit of a variable capacitor -57- and a fixed capacitor -58- and a parallel circuit of a first resistor -59- and a first inverter -60-, a third capacitor -61- and, as well as a parallel circuit of a second resistor -62- and a second inverter -63- are connected in series, A digital clock signal having the natural frequency of the quartz oscillator -15- of 4.433 MHz is generated.

The clock signal present at the output of the oscillator circuit 51 is supplied to a clock output -Βχ- via an inverter 64 and to an input of a NAND gate 65 -65. At a second input of the NAND gate -65- there is a command signal supplied via an input -C-.

The output of the NAND gate -65- leads to the first frequency doubler circuit -52- and is there on the one hand with an input of an inverter -66-, on the other hand via a first capacitor -67- with an input of a NOR gate -68- connected. The first capacitor -67- is followed by a grounded first resistor -69-. The output of the inverter -66- is connected via a second capacitor -70- to a second input of the NOR gate -68-. The second capacitor -70- is connected to a grounded second resistor -71- downstream. At the output of the NOR gate -68-, which simultaneously feeds the output of the first frequency doubler circuit -52-, there is a digital clock signal of 8.866 MHz,

- 6 No. 354315

The digital clock signal of 8.866 MHz is fed to a count input -B- of a 4-bit binary counter -72- of the '7493 type (see Siemens Data Book 1974/75, Volume I, Digital Circuits MOS, page 178), which is the centerpiece the frequency divider circuit -53- forms.

It should be noted that in the 4-bit binary counter -72-. the output is not connected to the counting input -B-, so that the 4-bit counter -72- only counts from zero to seven, ie registers eight periods of the counting frequency.

Depending on whether a state L or state H of a signal is present at an input - D-, the frequency divider circuit -53- divides the clock frequency of 8.866 MHz by 8 or by 6. This is done in the following manner: The outputs - and Q_c- of the 4-bit binary counter -72- are at the inputs of a NAND gate -73-, the output Q_D at the entrance of an inverter -74-. The outputs of NAND gate -73- and inverter -74- are connected to the inputs of another NAND gate -75-.

By this logic operation, state L appears at the output of NAND gate -75- for decimal numbers zero through two, state H for decimal numbers three through seven. As will be shown, the 4-bit binary counter becomes -72 - Reset by six by the six corresponding to the decimal number state. Thus, for the decimal numbers zero to two, the state L is present at the output of the NAND gate -75- and the state H for the decimal numbers three to five. This means that there is a total of 6.866 MHz counting frequency. It is fed to one input of a NAND gate.

At the counter output ^-Q.sup.- which, as is known, has the state L from zero to three and the state H from four to seven, the 8.866 MHz counting frequency of eight can be tapped directly and fed to one input of a NAND gate -77-.

The counter outputs -Q_c and Q_D"Are still at the inputs of a NAND gate -78-, which is followed by an inverter -79-, whose output to the first Rücksteüeingang -R₀.j-- of the 4-bit binary counter -72-.

The input -D- of the circuit is connected to an input of a NAND gate -80- and via an inverter -81- to an input of a NAND gate -82-. The output of the NAND gate -75- is connected through an inverter 83 to a second input of the NAND gates -80 and 82-. The outputs of NAND gates -80 and 82- are at the inputs of a bistable flip-flop made up of NAND gates -84 and 85-. The output of the NAND gate -84- is connected to one input of the NAND gate -76- and to the second reset input -R ^ -^- 4-bit binary counter -72- connected.

The output of NAND gate -85- is at an input of NAND gate -77-,

After describing the circuit, the operation of the frequency switch circuit will now be explained. It is assumed that at the input - D - and thus at an input of the NAND gate -80- the state L is present. This causes a state H. regardless of the state of the other input at the output of the NAND gate -80-.

The state L at the input -D- causes a state H at the first input of the NAND gate -82- because of the inverter -81-. Since at the output of the NAND gate -75- from the second to the second state L and from three to seven the state H prevails, because of the inverter -83- at the second inputs of the NAND gates -80 and 82- from Nuu to two the state H and from three to seven the state L.

Let it be assumed that the output of the NAND gate -85- has the state H, so that this state is also at one input of the NAND gate -77-. The output of the second NAND gate -84- of the flip-flop then has the state L, so that the NAND gate -76- is disabled. At its output in this case is the state H.

Thus, the eighth gate counted at the first input of the NAND gate enters the second frequency doubler circuit through a NAND gate 86, whose inputs are connected to the outputs of the NAND gates 76 and 77-. 54-, and it is in the frequency control circuit -53- constantly geteüt eight.

Consider now the case where the circuit input -D-, and thus the one input of the NAND gate -80-, assumes the state H. Since, for the decimal numbers zero to two, the second input of the NAND gate -80- also has the state H, the state L appears at the output

No. 354315

Again, the bistable flip-flop tilts, so that at the output of the NAND gate -84- the state H occurs, while the output of the NAND gate -85- assumes the state L and the NAND gate -77- blocks.

There are now both at an input of the NAND gate -76- and at the second reset input -R ^ - di^e States H, so that the signal at the other input of the NAND gate -76- passes through the NAND gate -86- in the second frequency doubler circuit -54-. By the logical combination of the 4-bit counter -72- with the NAND gate -78- and the inverter -79- takes the first reset input R_Q] then the state H, if both the counter output Q_c as well as the counter output -Qβ- has the state H; this is the case for the six decimal number. Since the reset inputs R_oil and R ^ are internally linked by an AND gate, in the present case the 4-bit binary counter -72- is reset at the six decimal number, and the six-divided counting frequency of 8.866 MHz enters the second frequency doubler circuit -54-.

A reappearance of the state L at the input -D- causes a switching of the Teüungsverhältnisses to eight.

The division ratio may only be changed in the frequency divider circuit if it is ensured that the period duration after the keying has a duration predetermined by the division ratio. This is always the case in the zero position of the counter.

Since the second frequency doubler circuit -54- is identical to the first -52-, it need not be discussed in more detail. Its output is connected to the count input -A- of a second 4-bit binary counter -87- in the frequency converter -55-.

The two frequency doubler circuits -52, 54- are used because the quadruple clock frequency of a color carrier crystal is needed for the design of the present circuit.

Since in the 4-bit binary counter -87- the output "Q ^" is connected to the second count input -B-, the counter can count from zero to fifteen. The outputs -Qß and Qß- are connected to the inputs of a NAND gate -88-, the output of which via an inverter -89- with the reset inputs Rqp ^ ο2 ~^verbun<len is. This logic operation resets the 4-bit binary counter -87- for the binary number HLHL, which is known to correspond to the decimal number ten.

The outputs -Q ^, Qß »Qß and Qß are connected via logic gates - 90 to 108-, which consist of NAND and NOR gates, with resistors -R connected in parallel_x to R₅- connected. The resistors -R_x to R_s- Are on the other hand to a connecting line -109- to the power amplifier -56-. Between a voltage source U_ß of 5 V in this example and connecting line -109- there is another resistor -R₆-. By the type of wiring, the gates -90 to 108- act as a sequential switch, the one with the frequency of the clock signal at the counter input -A- one of the resistors -R_x to R₅- switches through.

By wiring the 4-bit binary counter -87- with NOR and NAND gates, the lowest count outputs and the highest count at the inputs of the resistor -R_x- are upstream NOR and NAND gates, the outputs for the second lowest count and for the second highest count at the inputs of the resistor -R₂- are connected upstream NOR and NAND gates, etc., the circuit acts like a forward / reverse counter, counting from zero to four, with the count four being evaluated twice.

For example, is the resistor - R_x- Connected, applies to the voltage at the connecting line 109 U_x/ Uß = R_x/ R₆ + R_x, In the next counting step - R₂- switched through and it applies U₂/ Uß = R₂/ R₆ + R₂, In the fifth counting stage (count four) - R_s- switched through and it applies U₅/ Uß = R₅/ R₆ + Rs · In the sixth counting stage is also - R_s- switched through, in the seventh -R₄- and in the tenth -R_x-.

The resistors - R_x to R_s and R₆- Are dimensioned so that the voltages U. (i = 1.. .5) such U₅ increase and then back to U_x decrease, that a rising and falling staircase form, wherein the envelope of the two stairs represents half a period of a sinusoid. Thus, at the output of the transducer, there is a stepped voltage, the envelopes representing the individual positive half-waves of a sinusoidal oscillation. Thus, an already sinusoidal signal with a frequency divided by a factor of 10 is obtained from a purely digital signal at the output of the second frequency doubler.

- 8 No. 354315

Because of the use of purely ohmic resistors in the resistor network of the converter, the circuit has an aperiodic behavior, so that no transients occur when switching from a frequency f to a second f.

The output signal of the converter supplied via the connecting line -109- to the output stage -56- ⁵ Is amplified in two connected as emitter follower transistors -110, 111- and then placed on a center tap of the primary winding of an output transformer. The primary winding consists of two winding halves -112, 113-. In this embodiment, each of the winding halves has -112, 113- twenty turns.

Parallel to the two winding halves -112, 113- is a parallel circuit of a resistor ¹⁰ -114- and a capacitor -115-. The winding half -112- is connected via an output transistor of a power driver -116-, the winding half -113- connected via an output transistor of a second power driver -117- to ground. The two power drivers -116, 117- belong to a digital module of the type 49700 (see Siemens data book 1974/75, volume I, digital circuits MOS, page 289), which consists of two AND-power drivers -116, 117- and two NAND links -118, 119-¹⁵ with two inputs each.

At each one input of the NAND gates -118, 119- is the signal present at the command input -C- which has been supplied to the NAND gate 65-. At the second input of the NAND gate -119- is the output of a flip-flop -120- whose input is connected to the output of the NAND gate -88- in the converter -55-. As already explained, is located at the output of the NAND gate²⁰ A rectangular signal having a frequency divided by a factor of ten with respect to that of the signal applied to the counting input -A- of the 4-bit binary counter -87-. During a period of the frequency at the output of NAND gate -88- and thus at the input of flip-flop -120-, exactly one half cycle of the stepped voltage supplied via connecting line -109- to output stage -56- falls. As a result, fall two Haibperioden the staircase voltage in one²⁵ Period of the output at the flip-flop -120- lying square wave signal.

In this exemplary embodiment, the signal present at the command input -C- has the meaning state H = transmitter on and correspondingly state L = transmitter.

It is assumed that a state H, which is thus applied to each one input of the NAND gates -118, 119-. If the square wave at the output of the flip-flop -120- also has a state H,³⁰ then this causes a state L at the output of the NAND gate -119- and thus at the second input of the NAND gate -118-. This results in a state H at the output of the NAND gate in

Power driver -117- and the output transistor becomes conductive. Likewise, a state H results at the output of the NAND gate -118- and thus a state L at the output of the NAND gate in

Power driver -116-, so that its output transistor is disabled. A half wave at the³⁵ Center tap between the two winding halves -112, 113- adjacent stepped voltage thus causes a current flowing through the winding half -113- to ground.

During the subsequent half cycle of the stepped voltage, the square wave at the output of the flip-flop -120 has the state L, which in an analogous manner now opens the output transistor belonging to the power driver -116 and blocks the output transistor belonging to the power driver -117-. During this half-period of the staircase-shaped voltage flows

Current over winding half -112- to ground.

With the aid of the winding halves -112, 113-, the control via the flip-flop -120- and the digital device of the type 49700, the step-shaped voltage is transformed with an envelope of positive half-waves into a voltage with a sinusoidal envelope.

⁴⁵ Due to the inherent capacitance of the output transformer as well as the parallel connection of the resistor -114- and the capacitor -115- a smoothing of the stepped voltage is achieved, so that a pure sine wave is transmitted.

Due to the selected type of control of the output transformer with the flip-flop -120- and the digital device type 49700 is additionally achieved that in a state L on the command⁵⁰ input -C-, ie at a state transmitter off, both transistors in the power drivers -116,

117- are locked so that losses are prevented by a flow of currents.

In the present output stage, which works as push-pull output, one comes out with only one analog amplifier part.

- 9 No. 354315