Clock domain crossing fifo

The method and equipment which transmit data to an asynchronous receive-clock domain from a source clock domain are brought about. The first processing circuit located in the source clock domain connects writing address information to the above-mentioned data, and a clock generation machine generates a transmit-clock signal in a source clock domain synchronizing with a source clock. The first processing circuit transmits data equipped with the above-mentioned clock signal and the tied-up writing address information to the second processing circuit in a receive-clock domain further. In a receive-clock domain, the second processing circuit writes in data in the address which shows the storage element corresponding to the tied-up writing address information. The second processing circuit reads the above-mentioned data from a storage element synchronizing with a receiving domain clock while carrying out a clock input at a storage element synchronizing with the transmit-clock signal which answers the write-in enable signal from a source clock domain, and is accompanied by the above-mentioned data.