Nova Patents
AT348389T

Segmented metal bitlines

Abstract

The storage unit array structure of integrated - circuit is a metal bit line of the clapboard. The storing unit and right and device volatility storage unit, the floating gate, flash memory EEPROM, or a EPROM storage unit. Connection with the metal the memory cells bit line, and metal bit line of the clapboard. According to hopes according permits configuring (e.g., programming) or reading the storage unit is the each fragment turning on the voltage. The programming voltage can be is higher than the integrated - circuit VCC high voltage. By and metal bit line segment a fragment, wherein a fan between the position of the noise and improving performance and reliability, and each of the comparing a long metal bit line (i.e. fragments is test and a containing to a such operation) to reduce the parasitic capacitor to reduce the power consumption.

Term

No projected expiry on record.

  1. Priority
  2. Filed
  3. Granted
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22 members in 10 offices

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Priority claims
DocumentOfficeKindDate
96058601United States of AmericaA

Members22

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DocumentOfficeKind
WO03028033A2World Intellectual Property Organization (WIPO)A2
AU2002330054A1AustraliaA1
US6552932B1United States of AmericaB1
WO03028033A3World Intellectual Property Organization (WIPO)A3
US2003206450A1United States of AmericaA1
TW561584BTaiwan Province of ChinaB
KR20040051587ARepublic of KoreaA
EP1430482A2European Patent Office (EPO)A2
CN1556995AChinaA
US2005002232A1United States of AmericaA1
US6856541B2United States of AmericaB2
JP2005505088AJapanA
US6922358B2United States of AmericaB2
US2005232010A1United States of AmericaA1
EP1430482B1European Patent Office (EPO)B1
US7158409B2United States of AmericaB2
AT348389TThis recordAustriaT
DE60216782D1GermanyD1
DE60216782T2GermanyT2
CN100490001CChinaC
JP4310189B2JapanB2
KR100914264B1Republic of KoreaB1