Nova Patents
AT344550T

Selectable clocking architecture

Abstract

A method of providing a first clock signal in (54) and a second the clock signal is connected to the serial switch circuit and conversion a switch circuit the data memory (52). With first and second clock signal having selecting with a reference clock signal synchronization. With the clock with the first or the second synchronous clock. A with a selecting the synchronous circuit is placed in the first working method in order to make the first clock and a reference clock synchronization or out of the second working method in order to make the second clock and a synchronous clock.

Term

No projected expiry on record.

  1. Priority
  2. Filed
  3. Granted
  4. Today

17 members in 10 offices

This recordMember, by publication datePriority claim

Priority claims1

Priority claims
DocumentOfficeKindDate
11770202United States of AmericaA

Members17

Family members, oldest first
DocumentOfficeKind
US2003190003A1United States of AmericaA1
CA2480222A1CanadaA1
WO03088500A1World Intellectual Property Organization (WIPO)A1
AU2003226122A1AustraliaA1
TW200306086ATaiwan Province of ChinaA
TWI223506BTaiwan Province of ChinaB
EP1493233A1European Patent Office (EPO)A1
JP2005522799AJapanA
US6925575B2United States of AmericaB2
CN1659786AChinaA
EP1493233B1European Patent Office (EPO)B1
AT344550TThis recordAustriaT
ATE344550T1AustriaT1
DE60309459D1GermanyD1
DE60309459T2GermanyT2
CA2480222CCanadaC
JP4156529B2JapanB2