AT344550T
Selectable clocking architecture
Abstract
A method of providing a first clock signal in (54) and a second the clock signal is connected to the serial switch circuit and conversion a switch circuit the data memory (52). With first and second clock signal having selecting with a reference clock signal synchronization. With the clock with the first or the second synchronous clock. A with a selecting the synchronous circuit is placed in the first working method in order to make the first clock and a reference clock synchronization or out of the second working method in order to make the second clock and a synchronous clock.
Term
No projected expiry on record.
- Priority
- Filed
- Granted
- Today
17 members in 10 offices
Priority claims1
| Document | Office | Kind | Date |
|---|---|---|---|
| 11770202 | United States of America | A |
Members17
| Document | Office | Kind | |
|---|---|---|---|
| US2003190003A1 | United States of America | A1 | |
| CA2480222A1 | Canada | A1 | |
| WO03088500A1 | World Intellectual Property Organization (WIPO) | A1 | |
| AU2003226122A1 | Australia | A1 | |
| TW200306086A | Taiwan Province of China | A | |
| TWI223506B | Taiwan Province of China | B | |
| EP1493233A1 | European Patent Office (EPO) | A1 | |
| JP2005522799A | Japan | A | |
| US6925575B2 | United States of America | B2 | |
| CN1659786A | China | A | |
| EP1493233B1 | European Patent Office (EPO) | B1 | |
| AT344550TThis record | Austria | T | |
| ATE344550T1 | Austria | T1 | |
| DE60309459D1 | Germany | D1 | |
| DE60309459T2 | Germany | T2 | |
| CA2480222C | Canada | C | |
| JP4156529B2 | Japan | B2 |
1 legal event, as the office reported them to INPADOC
Events
| Event | Code | |
|---|---|---|
| Ceased as to paragraph 5 lit. 3 law introducing patent treatiesCeasedRER | RER |
Numbers
- Application
- 3746561
Titles2
- German
- ARCHITEKTUR FÜR WÄHLBARE TAKTUNG
- English
- ARCHITECTURE FOR SELECTABLE ACTIVITY
Classification
- CPC, 3
- H03M9/00
- H04L7/02
- H04L25/05
- IPC, 4
- G06F1 12
- H03M9 00
- H04L25 05
- H04L7 02