Bit-detection arrangement and apparatus for reproducing information

Describing involves analog signals (AS) transforms into a digital signal (DS) bit-detecting device of the invention. Analog signal (AS) is fed to the quantizer (11). The quantizer (11), S1 output signal is fed to the phase discriminator (PD1). To sample the output signal S1. Phase discriminator (PD1) PH2 depending on the output signal in the output phase difference between the signals S1 and C2 the clock signal. If C2 of the clock signal frequency is approximately equal to the output frequency of the signal S1, then the phase discriminator (PD1) PH2 output signal slowly changes. Therefore, analog-digital converter ADC (13) by the clock signal C1, sampling the output at a slower rate. Clock signal C1 through C2, divided by the factor n clock signal from the clock signal C2, where n is an integer greater than 1. C2 clock cycle of the clock signal by phase difference, the analog-digital converter ADC (13) of the processed signal interpolates PrS. This can be done in different ways. Specific cases including those with discrete-time implementation of digital phase-locked loop oscillator DPLL (2). The resulting phase difference is bit judgment (3) using the output of the sample.