Capacitance level measurement circuit and system

A measurement circuit capacity level (28) comprising: a control circuit including: a power port (136) couplable to a constant current source (110); detector port (162) couplable to a threshold detector (130); probe port (134) couplable to a probe capacitor (21); a reference port (132) couplable to a reference capacitor (44); a plurality of switches (111, 112, 113, 114) are activatable to couple alternately said power port (136) to said probe port (134) and to said reference port (132); said control circuit being configured to generate alternately a signal waveform linear ramp having a slope that is proportional to the magnitude of the ability of a probe capacitor (21) and a reference capacitor (44) coupled to said probe port (134) and said reference port (132); in which the parasitic capacitance between the reference capacitor (44) and the probe capacitor (21) substantially eliminates maintaining tension across said reference capacitor (44) at the same level through said probe capacitor (21) during level measurements.